9 results about "Translation lookaside buffer" patented technology

The application discloses a kind of translation lookaside buffer table entry processing method, system, medium and product, applied to processor technical field, comprising: when process switching, determine the non-critical table entry corresponding to the process before switching in translation lookaside buffer, obtain target non-critical table entry;The target non-critical table entry is stored in the first cache corresponding to processor core, and the target non-critical table entry is deleted from the translation lookaside buffer;The recovery deadline corresponding to the process before switching issued by operating system is acquired;Based on the recovery deadline, before switching back to the process before switching, the target non-critical table entry is written back to the translation lookaside buffer from the first cache.This way, in the case of guaranteeing the process before switching fast recovery, the hit rate of translation lookaside buffer table entry can be improved, and then the processor performance is improved.

An electronic device may include: a processor including a first core and a second core, the first core and the second core being configured to execute a process; and a main memory configured to store a page table corresponding to the process. The first core includes: a first translation lookaside buffer (TLB) configured to store a first portion of the page table; a page table walker configured to perform a page table walk operation to look up the page table; and a TLB check predictor configured to store a check weight table and, based on the check weight table, transmit a TLB check request to the second core. The second core includes a second TLB configured to store a second portion of the page table.

Techniques for implementing a translation lookaside buffer for a L0 cache are described. In some examples, a translation lookaside buffer for a L0 cache (L0 TLB) comprises a L0 TLB hit predictor and an L0 TLB array, wherein the L0 TLB hit predictor is to: predict when a physical address translation of a linear address is found in the L0 TLB array based on previous L0 TLB hit indications, provide the physical address translation of a linear address from the L0 TLB array when the physical address translation of a linear address is found in the L0 TLB array, and cause a determination of the physical address translation of a linear address using an entity other than the L0 TLB array when the physical address translation of a linear address is predicted to not be found in the L0 TLB array.

The application provides a memory management method and a memory management unit. The memory management unit comprises an address conversion and control module and a translation lookaside buffer (TLB) structure. The TLB structure comprises an L2 TLB and a local buffer. The local buffer adopts a full-connected structure and comprises a plurality of entries. Each entry stores a group of related page table entries. The method comprises the following steps: the address conversion and control module sends a received first virtual address to the local buffer and the L2 TLB; the local buffer queries a first target page table entry corresponding to the first virtual address from the plurality of entries based on the first virtual address, and determines a first query result based on whether the first target page table entry is queried from the plurality of entries; the first query result comprises a physical address corresponding to the first virtual address or a query miss; the L2 TLB queries the first target page table entry corresponding to the first virtual address based on the first virtual address; and the L2 TLB and the local buffer query in parallel. According to the application, the address conversion efficiency can be improved.

Disclosed herein are filtering remote data synchronization barrier (DSB) instruction execution in a processor-based device. In some example aspects, the processor-based device provides a plurality of processors, including an issuing processor and a remote processor. The remote processor receives a translation lookaside buffer (TLB) invalidate (TLBI) instruction from the issuing processor, the instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies a filtering criterion, the filtering criterion specifying a condition under which the remote processor is not required to execute the DSB instruction. If the remote processor determines that the TLBI instruction satisfies the filtering criterion, the remote processor forgoes execution of a DSB operation corresponding to the DSB instruction and issues an early DSB acknowledgement to the issuing processor.

The application relates to the technical field of computer virtualization and cloud computing, in particular to a server virtualization system based on a virtual machine, which comprises a bottom-layer virtual machine manager, a state monitoring module, a jitter quantification module and a decision scheduling module; the state monitoring module collects hardware performance counter data, current physical resource utilization and virtual machine resource request data, and analyzes kernel-level running state data; the jitter quantification module extracts central processing unit context switching frequency, translation lookaside buffer failure times and last-level cache contention indexes, and generates scheduling jitter entropy values; the decision scheduling module compares the scheduling jitter entropy values with a preset dangerous threshold value, executes a dynamic resource allocation scheme based on a deep reinforcement learning model below the threshold value, and executes a static locking degradation scheme when the threshold value reaches or exceeds the threshold value, so that the instability risk of a virtual machine monitor can be actively inhibited.

Techniques for broadcast translation lookaside buffer invalidation are described. In some examples, an instance of a single instruction includes fields for a single instruction having fields to indicate one or more operations to perform, an identifier of a first source operand, and, in some examples, an identifier of a second source operand is to be handled by execution circuitry. The execution circuitry of a first hardware thread is to execute the decoded instruction according to the fields to indicate one or more operations to broadcast a command to a plurality of hardware threads to cause an invalidation one or more translation lookaside buffer (TLB) entries for each of the plurality of hardware threads in accordance with a value of the first source operand and / or a value of the second source operand.

The application discloses a translation look-aside buffer (TLB) verification method, device and equipment and a storage medium. The method comprises the following steps: after receiving a target TLB verification request, performing instantiation processing on a pre-constructed heterogeneous TLB bottom encapsulation model according to attribute information of the target TLB; constructing a verification environment and a verification case corresponding to the target TLB according to an instantiation processing result corresponding to the heterogeneous TLB bottom encapsulation model and a standardized interface corresponding to the heterogeneous TLB bottom encapsulation model; and running the verification case according to the verification environment corresponding to the target TLB to obtain a verification result corresponding to the target TLB. The technical scheme of the embodiment of the application can improve the verification efficiency of the TLB and the accuracy of the verification result.

In one example of the present technology, an input / output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.