56 results about "Translation lookaside buffer" patented technology

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

Provided in the embodiments of the present disclosure are an address translation method and apparatus, and an electronic device and a storage medium. The address translation method is applied to an address translation apparatus, the apparatus comprising multiple sets of translation lookaside buffers, wherein each of the multiple sets of translation lookaside buffers is configured to store page table information for translating a virtual address into a physical address. The address translation method comprises: in response to obtaining a first virtual address translation request, determining a target translation lookaside buffer from multiple sets of translation lookaside buffers on the basis of a first mapping algorithm, wherein the first virtual address translation request comprises an object virtual address; and accessing page table information in the target translation lookaside buffer, in order to translate the object virtual address into an object physical address. The method further comprises: acquiring access frequency information for each of the multiple sets of translation lookaside buffers; on the basis of the access frequency information, determining whether the first mapping algorithm is required to be updated; and in response to the first mapping algorithm being required to be updated, updating the mapping algorithm to a second mapping algorithm.

A system-on-chip and an operation method of the system-on-chip are provided. The system on chip includes: a translation lookaside buffer (TLB) storing a portion of address translation information for translating between a virtual address and a physical address; a core executing the instruction and accessing the TLB; a page table traversal unit that performs a page table traversal operation of searching for a page table storing address translation information; and a static page management (SPM) circuit that, when a physical address is obtained from a virtual address included in static address translation information corresponding to a static page among the address translation information, stops an access to check the TLB or stops a page table traversal operation.

Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors including an issuing processor and a remote processor. The remote processor receives, from the issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies filtering criteria, which specify conditions under which execution of the DSB instruction by the remote processor is unnecessary. If the remote processor determines that the TLBI instruction satisfies the filtering criteria, the remote processor foregoes execution of a DSB operation corresponding to the DSB instruction, and issues an early DSB acknowledgement to the issuing processor.

The present application relates to devices and components, including apparatus, systems, and methods for scheduling delivery and execution of page fault or permission fault exceptions. A memory management unit may receive a virtual address associated with an execution mode and initiate a virtual-to-physical translation operation. The MMU may detect a first condition associated with a search of the virtual address in a translation lookaside buffer (TLB). In response to the detection of the first condition, MMU may start a timer. MMU may detect a fault exception associated with the translation operation of the virtual address and determine that a second condition is satisfied. In response to detecting the second condition, the MMU or the reorder buffer exception monitor may deliver the fault exception based on the timer.

The invention discloses a permission adjustment method, device and equipment and a computer readable storage medium, and is applied to the technical field of computing, and the method comprises the steps: obtaining the access frequency of a heap area in a virtual address, the number of errors of physical address permission detection, and the code exception jump condition; determining a corresponding control signal according to the access frequency, the error number and the code exception jump condition; the control signal comprises an authority change signal and a process freezing signal; dynamically adjusting the physical memory authority of the memory management unit according to the control signal; the dynamic adjustment includes adjusting read or write or execution permissions of the physical page, and disrupting an access sequence of the translation lookaside buffer cache. According to the method, the limitation that traditional static permission configuration cannot adapt to the dynamic running state of the process is solved; and the MMU cannot detect and block hostile attacks in real time, so that the safety and the flexibility of MMU authority management are improved.

For managing a translation lookaside buffer (TLB), an example computing device is deployed with virtual machines (VMs) by using a virtual machine monitor and has multiple CPU cores, where the VMs include a common VM running a common execution environment and a secure VM running a trusted execution environment (TEE) instance. In an example, in response to a target request for modifying a secure memory, the common execution environment sends an inter-processor interrupt (IPI) to one or more CPU cores that run the secure VM. Control data corresponding to the secure VM include a TLB control field set to a target value that indicates that all TLBs of the VM are flushed when exiting from the secure VM. In response to the IPI, the one or more CPU cores exit from a secure mode, and flushes all TLBs of the VM based on the target value.

The application provides a method, device, electronic equipment and computer program product for increasing the storage information density of a translation lookaside buffer. In the method, when an address translation request of a first virtual address is received, a plurality of continuous address mapping data is obtained according to the first virtual address, each address mapping data containing a mapping relationship between a virtual address and a physical address; when the plurality of continuous address mapping data satisfies a preset merging condition, the plurality of continuous address mapping data is merged into one merged entry; the merged entry is stored in the translation lookaside buffer, and a target physical address corresponding to the first virtual address is returned to an address request unit according to the merged entry. Thus, by merging the plurality of continuous address mapping data into a single entry and sharing the same high-bit part, the storage density of the effective address mapping is significantly improved while keeping the physical capacity of the translation lookaside buffer unchanged.

The application discloses a kind of translation lookaside buffer table entry processing method, system, medium and product, applied to processor technical field, comprising: when process switching, determine the non-critical table entry corresponding to the process before switching in translation lookaside buffer, obtain target non-critical table entry;The target non-critical table entry is stored in the first cache corresponding to processor core, and the target non-critical table entry is deleted from the translation lookaside buffer;The recovery deadline corresponding to the process before switching issued by operating system is acquired;Based on the recovery deadline, before switching back to the process before switching, the target non-critical table entry is written back to the translation lookaside buffer from the first cache.This way, in the case of guaranteeing the process before switching fast recovery, the hit rate of translation lookaside buffer table entry can be improved, and then the processor performance is improved.

Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a TLB, comprising multiple TLB entries each comprising a tag and a plurality of data portions, and further comprises a memory management unit (MMU). The MMU is configured to receive a memory access request comprising a VA, and determine that a TLB access to the TLB for a page VA of the VA results in a miss. In response, the MMU generates a TLB entry, wherein the tag of the TLB entry comprises the page VA, the plurality of data portions comprises a corresponding plurality of page PAs, a first data portion thereof comprising a page PA corresponding to the page VA, and one or more second data portions thereof comprising corresponding PAs of next sequential page VAs following the page VA.

A method includes executing, by a processor core, a first task; scheduling, by a scheduler, a second task to be executed by the processor core upon completion of executing the first task; responsive to scheduling the second task, providing, by the scheduler, a prewarming message to a memory management unit (MMU) coupled to the processor core; and responsive to receiving the prewarming message, fetching, by the MMU, a page table specified by a page table base of the prewarming message.

An electronic device may include: a processor including a first core and a second core, the first core and the second core being configured to execute a process; and a main memory configured to store a page table corresponding to the process. The first core includes: a first translation lookaside buffer (TLB) configured to store a first portion of the page table; a page table walker configured to perform a page table walk operation to look up the page table; and a TLB check predictor configured to store a check weight table and, based on the check weight table, transmit a TLB check request to the second core. The second core includes a second TLB configured to store a second portion of the page table.

Techniques for implementing a translation lookaside buffer for a L0 cache are described. In some examples, a translation lookaside buffer for a L0 cache (L0 TLB) comprises a L0 TLB hit predictor and an L0 TLB array, wherein the L0 TLB hit predictor is to: predict when a physical address translation of a linear address is found in the L0 TLB array based on previous L0 TLB hit indications, provide the physical address translation of a linear address from the L0 TLB array when the physical address translation of a linear address is found in the L0 TLB array, and cause a determination of the physical address translation of a linear address using an entity other than the L0 TLB array when the physical address translation of a linear address is predicted to not be found in the L0 TLB array.

An MMU with prefetch functionality is provided. The MMU includes a first TLB, burst buffer, second TLB and control logic. The first TLB is configured to fetch a first set of one or more first page table entries based, at least in part, on a virtual address, and before a request to access a client address is received from a client. The burst buffer stores a plurality of second page table entries from a respective page table associated with a first page table address. A second translation lookaside buffer is configured to fetch a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer based, at least in part, on the virtual address, and before the request to access a client address is received from the client.

A system-on-chip includes a translation lookaside buffer (TLB) that stores a portion of address translation information for translating between virtual addresses and physical addresses, a core that executes an instruction and accesses the TLB, a page table walker that performs a page table walk operation of searching a page table that stores the address translation information, and a static page management (SPM) circuit that, when a physical address is obtained from a virtual address included in static address translation information corresponding to a static page among the address translation information, stops access to the TLB by the core or stops the page table walk operation.

The invention discloses a data loading method, device and equipment, and relates to the technical field of memory management.The method comprises the steps that by means of a memory management unit, when a target physical page frame number is not found in a conversion bypass buffer area, page table traversal is carried out, and a target physical page frame number is obtained; obtaining a target physical page frame number corresponding to virtual network index information in a virtual address of the loading instruction; according to the target physical page frame number and the offset, generating a physical address corresponding to the loading instruction, and obtaining target data corresponding to the physical address from a physical memory; sending the target data to a loading storage unit assembly line to complete data loading of the loading instruction; by utilizing the memory management unit, the same memory access channel can be reused to complete page table traversal and target data prefetching under the condition that the target physical page frame number is not found in the conversion bypass buffer area, so that the delay of searching data from a physical memory is reduced, the pause delay of a processor pipeline is reduced, and the performance is improved.

Method for disabling page replication entries in a data processing system with a plurality of processing elements, wherein the method comprises: Applying a delay (330) to a store reorder queue (SRQ) (229) cleanup cycle of a processing element; Clean up SRQ (229) during the delayed cleanup cycle; and Receiving a translation lookaside buffer invalidation (TLBI) instruction (302) from a connection linking the plurality of processing elements, wherein the TLBI instruction (302) is an instruction to invalidate an address lookaside buffer (TLB) entry (318, 328) corresponding to a virtual memory page and / or a physical memory section, wherein the TLBI instruction (302) is broadcast by another processing element, where by applying the delay (330) to the cleanup cycle of the SRQ (229) the amount of overlap between the cleanup cycle of the SRQ (229) and a deactivation cycle associated with the TLBI (302) is increased.

The application provides a memory management method and a memory management unit. The memory management unit comprises an address conversion and control module and a translation lookaside buffer (TLB) structure. The TLB structure comprises an L2 TLB and a local buffer. The local buffer adopts a full-connected structure and comprises a plurality of entries. Each entry stores a group of related page table entries. The method comprises the following steps: the address conversion and control module sends a received first virtual address to the local buffer and the L2 TLB; the local buffer queries a first target page table entry corresponding to the first virtual address from the plurality of entries based on the first virtual address, and determines a first query result based on whether the first target page table entry is queried from the plurality of entries; the first query result comprises a physical address corresponding to the first virtual address or a query miss; the L2 TLB queries the first target page table entry corresponding to the first virtual address based on the first virtual address; and the L2 TLB and the local buffer query in parallel. According to the application, the address conversion efficiency can be improved.

A processor and method for clearing a translation lookaside buffer (TLB) using a specified key identification code. An instruction is provided in an instruction set architecture (ISA) that specifies a key identification code for clearing a TLB. The instruction is converted into at least one microinstruction. A specified key identification code is supplied to a control logic circuit of the TLB via a memory order buffer (MOB) in response to a clear microinstruction in the at least one microinstruction, causing the control logic circuit to clear entries in the TLB that match the specified key identification code.

A method includes executing, by a processor core, a first task; scheduling, by a scheduler, a second task to be executed by the processor core upon completion of executing the first task; responsive to scheduling the second task, providing, by the scheduler, a prewarming message to a memory management unit (MMU) coupled to the processor core; and responsive to receiving the prewarming message, fetching, by the MMU, a page table specified by a page table base of the prewarming message.

The invention discloses an address management method and device, electronic equipment and a storage medium, and relates to the technical field of cloud computing and virtualization, the method comprises the following steps: in response to obtaining a memory access request sent by target external equipment, decrypting the memory access request to obtain a security tag and an access tag of the memory access request; and if it is determined that the security tag passes identity verification, the access tag passes permission verification, and address mapping information of the memory access request exists in the input / output translation lookaside buffer, obtaining a corresponding physical address through the input / output translation lookaside buffer. According to the technical scheme provided by the embodiment of the invention, the memory access request is comprehensively verified through the security tag and the access tag, fine-grained access control is realized, the access security of the physical memory is ensured, the acquisition efficiency of the address mapping information is improved through the input / output translation lookaside buffer, and the access security of the physical memory is ensured. And the delay time of physical address translation is reduced.

A memory page management method, system, and apparatus, a device, and a computer non-volatile readable storage medium are provided. The method includes acquiring a target virtual address of data to be accessed; performing a physical address lookup in a translation lookaside buffer based on the target virtual address; reading target data to be accessed from a physical address to be accessed if the corresponding physical address to be accessed is found in the translation lookaside buffer; and performing a parallel physical address lookup in a plurality of sets of uniformly addressed page tables based on the target virtual address if the physical address to be accessed is not found in the translation lookaside buffer, and reading the target data to be accessed from the physical address to be assessed if the physical address to be accessed is found.

The invention provides an address conversion method and data processing equipment, the data processing equipment comprises an address conversion module, a multi-stage query controller, a hierarchical extension decision unit and a shadow buffer, and the method comprises the following steps: the address conversion module determines a target query key in response to an address conversion request; the multi-stage query controller queries an initial translation lookaside buffer TLB structure stage by stage based on the target query key to obtain a query result, and the query result comprises a target page table item which is not queried or a target page table item matched with the address translation request; the hierarchical extension decision unit responds to the situation that the target page table item is not queried, each page table item in the initial TLB structure is migrated to a shadow buffer area, and the shadow buffer area which works stably is determined as an extended target TLB structure; the target TLB structure is used for next address translation.

Techniques for address translation are disclosed. A processor core is accessed. The processor core includes a memory management unit (MMU) and a unified translation lookaside buffer (TLB) within the MMU. The TLB is configured to support a plurality of page sizes, and the processor core is coupled to an external memory system. The TLB receives a lookup request for a virtual memory address, wherein the virtual memory address corresponds to a process running on the processor core. The TLB accesses a linked list that comprises a page size priority order for the plurality of page sizes. A lookup is performed in the TLB on the virtual memory address, and the lookup is conducted in the page size priority order. The linked list is updated, the updating moves a page size associated with the lookup to a location in the linked list, and a physical address is returned.

Filtering remote data synchronization barrier (DSB) instruction execution in a processor-based device is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors, including a publication processor and a remote processor. A remote processor receives, from a publication processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives DSB instructions from the publication processor. The remote processor determines whether the TLBI instruction satisfies a filtering criterion specifying a condition that does not require the remote processor to execute the DSB instruction. If the remote processor determines that the TLBI instruction meets the filtering criteria, the remote processor abandons execution of a DSB operation corresponding to the DSB instruction and issues an early DSB acknowledgement to the publication processor.

The invention provides a memory management unit, an address mapping method, a chip and electronic equipment. The memory management unit comprises: an arbitration module for receiving a circular address and an externally input virtual address, and determining a to-be-mapped virtual address according to the priority of the circular address and the virtual address; the translation backup buffer is used for storing a plurality of page table entries, performing matching with a to-be-mapped virtual address according to the mapping label array to obtain a label address, and reading a matched page table entry from the plurality of page table entries according to the label address; the mapping module is used for mapping a virtual address to be mapped into a physical address based on the matched page table item, and generating an indirect address based on the virtual address to be mapped when the virtual address to be mapped is not matched with the page table item; and the miss processing module is used for caching the to-be-mapped virtual address as a circular address when the to-be-mapped virtual address is not matched with the page table item, reading a new page table item from the outside based on the indirect address, and sending the new page table item to the translation backup buffer for storage.

Disclosed herein are filtering remote data synchronization barrier (DSB) instruction execution in a processor-based device. In some example aspects, the processor-based device provides a plurality of processors, including an issuing processor and a remote processor. The remote processor receives a translation lookaside buffer (TLB) invalidate (TLBI) instruction from the issuing processor, the instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies a filtering criterion, the filtering criterion specifying a condition under which the remote processor is not required to execute the DSB instruction. If the remote processor determines that the TLBI instruction satisfies the filtering criterion, the remote processor forgoes execution of a DSB operation corresponding to the DSB instruction and issues an early DSB acknowledgement to the issuing processor.

Using retired pages history for instruction translation lookaside buffer (TLB) prefetching in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device is provided. The processor-based device comprises a history-based instruction TLB prefetcher (HTP) circuit configured to determine that a first instruction of a first page has been retired. The HTP circuit is further configured to determine a first page virtual address (VA) of the first page. The HTP circuit is also configured to determine that the first page VA differs from a value of a last retired page VA indicator of the HTP circuit. The HTP circuit is additionally configured to, responsive to determining that the first page VA differs from the value of the last retired page VA indicator of the HTP circuit, store the first page VA as the value of the last retired page VA indicator.