102 results about "Translation lookaside buffer" patented technology

Circuitry and methods for reducing instruction translation lookaside buffer overheads for dynamic code libraries are described. In certain examples, a computer system includes an execution circuitry; a register to store a library context identifier value; and a memory management circuit to: determine, for an instruction comprising a virtual address, an entry in an instruction translation lookaside buffer that comprises a mapping of the virtual address to a physical address, and a library context identifier value, compare the library context identifier value from the register to the library context identifier value from the entry of the instruction translation lookaside buffer, and in response to the mapping being found for the virtual address and the library context identifier value from the register matching the library context identifier value from the entry of the instruction translation lookaside buffer, cause the execution circuitry to execute the instruction from the physical address.

The invention discloses a memory management unit, a processor and a page table caching method, and belongs to the technical field of computers. The memory management unit comprises a cache management module, a conversion backup buffer TLB module and a page table traversal PTW module; the TLB module is configured to cache a page table item; the PTW module is configured to query the page table according to the first virtual address under the condition that the TLB module is queried through the first virtual address and the TLB module is not hit; the cache management module is configured to merge 2n page table entries including a target page table entry to obtain a merged page table entry if the target page table entry corresponding to the first virtual address in the page table is valid and the page size indicated by the target page table entry is smaller than or equal to a merging threshold value; and caching the merged page table entry into a TLB module. The memory management unit provided by the invention can merge the effective page table entries corresponding to the pages smaller than or equal to the merge threshold, so that the utilization rate and hit rate of the TLB module are improved.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

The invention provides a data updating method which comprises the following steps: in response to a change in a translation lookaside buffer meeting a trigger condition, acquiring a plurality of virtual address ranges associated with the change; according to the plurality of virtual address ranges, a target update range is generated and stored in a target storage space, the target update range at least comprises each virtual address range, and the target storage space can be accessed by a plurality of target processors; and a target instruction is sent, the target instruction is used for indicating each target processor to interrupt the task being executed, the target update range is obtained from the target storage space, and the translation lookaside buffer corresponding to the target processor is updated according to the target update range.

An address translation system, method and device including a translation extension unit associated with a client and having a client address translation cache storing a client cache of the address translations. When virtual address of a translation request from the client is the same as the virtual address of an address translation of the client cache, the translation extension unit returns the physical address that is mapped to the virtual address according to the address translation to the client without transmitting the translation request to a memory management unit that maintains a page table of all the translations and a translation lookaside buffer with a subset of the translations.

Provided in the embodiments of the present disclosure are an address translation method and apparatus, and an electronic device and a storage medium. The address translation method is applied to an address translation apparatus, the apparatus comprising multiple sets of translation lookaside buffers, wherein each of the multiple sets of translation lookaside buffers is configured to store page table information for translating a virtual address into a physical address. The address translation method comprises: in response to obtaining a first virtual address translation request, determining a target translation lookaside buffer from multiple sets of translation lookaside buffers on the basis of a first mapping algorithm, wherein the first virtual address translation request comprises an object virtual address; and accessing page table information in the target translation lookaside buffer, in order to translate the object virtual address into an object physical address. The method further comprises: acquiring access frequency information for each of the multiple sets of translation lookaside buffers; on the basis of the access frequency information, determining whether the first mapping algorithm is required to be updated; and in response to the first mapping algorithm being required to be updated, updating the mapping algorithm to a second mapping algorithm.

In a microprocessor having an instruction execution unit and first and second sets of process execution resources, context information for a process next-to-be-executed by the instruction execution unit is loaded into a register file, translation lookaside buffer and first-level data cache of the first set of process execution resources during a first interval. During the first interval and concurrently with the loading of context information for the process next-to-be executed, the instruction execution unit executes a current process, including accessing context information for the current process within the register file, translation lookaside buffer and first-level data cache of the second set of process execution resources.

A method of reducing page walk latency resulting from a translation lookaside buffer (TLB) miss comprises providing a page fetch / walk logic module disposed between a coherent fabric and a memory controller. Upon receiving a notification of a TLB miss, performing, by the page fetch / walk logic module, a page table walk of a virtual address to produce a corresponding physical address. The method may further comprise forming, by a memory management unit, a TLB request that comprises a virtual address, and a request type field. The request type field may comprise (i) an indication that a TLB miss has occurred and (ii) a specification of a number of stages required of the page table walk.

Certain aspects of the present disclosure provide techniques and apparatus for translation lookaside buffer (TLB) compression. Embodiments include determining that a plurality of physical memory addresses, associated with a plurality of virtual memory addresses, are contiguous with one another and share one or more common address bits or one or more common attribute bits, wherein each respective physical memory address of the plurality of physical memory addresses corresponds to a separate respective physical memory page. Embodiments include generating a tag for an entry in a TLB, the tag representing the plurality of virtual memory addresses. Embodiments include associating, in the entry in the TLB, the tag with data comprising: a single instance of the one or more common address bits or the one or more common attribute bits of the plurality of physical memory addresses; and other bits of the plurality of physical memory addresses.

A system-on-chip and an operation method of the system-on-chip are provided. The system on chip includes: a translation lookaside buffer (TLB) storing a portion of address translation information for translating between a virtual address and a physical address; a core executing the instruction and accessing the TLB; a page table traversal unit that performs a page table traversal operation of searching for a page table storing address translation information; and a static page management (SPM) circuit that, when a physical address is obtained from a virtual address included in static address translation information corresponding to a static page among the address translation information, stops an access to check the TLB or stops a page table traversal operation.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., RISC-V), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

The present application discloses a data storage method, a search method and a device based on page coloring technology, which relates to the technical field of data storage. The method includes obtaining a virtual address corresponding to the data to be stored. According to the virtual address, if an entry of the virtual address in the main memory is not found in the translation lookaside buffer table, a target main memory page is randomly allocated for the virtual address in the main memory page, and the data to be stored is stored in the target main memory page. Then, according to the color preconfigured for the data to be stored, the data to be stored is stored from the target main memory page to the cache group corresponding to the preconfigured color in the cache. The method of the present application improves the technical effect of the utilization rate of the main memory and the cache space.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., RISC-V), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

A translation lookaside buffer invalidation (TLBI) instruction is described for instructing at least one translation lookaside buffer (TLB) to observe a TLB invalidation event. The TLBI instruction specifies TLBI domain information indicating, for each of two or more TLBI domains (including at least two non-overlapping TLBI domains), whether that TLBI domain is a target TLBI domain for which any TLBs are required to observe the TLB invalidation event or a non-target TLBI domain not required to observe the TLB invalidation event. TLBI broadcast control circuitry determines, based on the TLBI domain information specified by the TLBI instruction decoded by the instruction decoding circuitry, one or more TLBI request signals to be issued for instructing TLBs in one or more TLBI domains to observe the TLB invalidation event, and limits which TLBI domains are instructed to observe the TLB invalidation event based on the TLBI domain information.

Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides a plurality of processors including an issuing processor and a remote processor. The remote processor receives, from the issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) instruction indicating a request to invalidate a TLB entry of a plurality of TLB entries of a TLB of the remote processor. The remote processor also receives a DSB instruction from the issuing processor. The remote processor determines whether the TLBI instruction satisfies filtering criteria, which specify conditions under which execution of the DSB instruction by the remote processor is unnecessary. If the remote processor determines that the TLBI instruction satisfies the filtering criteria, the remote processor foregoes execution of a DSB operation corresponding to the DSB instruction, and issues an early DSB acknowledgement to the issuing processor.

Compressing a translation lookaside buffer (TLB) tag using a TLB metadata buffer in a processor-based device is disclosed herein. In some aspects, a processor-based apparatus provides a memory management unit (MMU) that includes a TLB and a TLB metadata buffer that includes a plurality of TLB metadata buffer entries that store corresponding TLB metadata. The MMU is configured to select a TLB metadata buffer entry for accessing the TLB of the processor-based device. After selecting the TLB metadata buffer entry, the MMU stores a pointer to the TLB metadata buffer entry as an active TLB metadata pointer. When the MMU subsequently receives a memory access request including a virtual address (VA), the MMU generates a TLB entry for the VA in the TLB and stores the active TLB metadata pointer as part of a TLB tag of the TLB entry in place of the TLB metadata of the TLB metadata buffer entry.

The present application relates to devices and components, including apparatus, systems, and methods for scheduling delivery and execution of page fault or permission fault exceptions. A memory management unit may receive a virtual address associated with an execution mode and initiate a virtual-to-physical translation operation. The MMU may detect a first condition associated with a search of the virtual address in a translation lookaside buffer (TLB). In response to the detection of the first condition, MMU may start a timer. MMU may detect a fault exception associated with the translation operation of the virtual address and determine that a second condition is satisfied. In response to detecting the second condition, the MMU or the reorder buffer exception monitor may deliver the fault exception based on the timer.

A translation lookaside buffer invalidation (TLBI) instruction is described for instructing at least one translation lookaside buffer (TLB) to observe a TLB invalidation event. The TLBI instruction specifies TLBI domain information indicating, for each of two or more TLBI domains (including at least two non-overlapping TLBI domains), whether that TLBI domain is a target TLBI domain for which any TLBs are required to observe the TLB invalidation event or a non-target 10 TLBI domain not required to observe the TLB invalidation event. TLBI broadcast control circuitry determines, based on the TLBI domain information specified by the TLBI instruction decoded by the instruction decoding circuitry, one or more TLBI request signals to be issued for instructing TLBs in one or more TLBI domains to observe the TLB invalidation event, and limits which TLBI domains are instructed to observe the TLB invalidation event based on the TLBI domain 15 information.

The invention discloses a permission adjustment method, device and equipment and a computer readable storage medium, and is applied to the technical field of computing, and the method comprises the steps: obtaining the access frequency of a heap area in a virtual address, the number of errors of physical address permission detection, and the code exception jump condition; determining a corresponding control signal according to the access frequency, the error number and the code exception jump condition; the control signal comprises an authority change signal and a process freezing signal; dynamically adjusting the physical memory authority of the memory management unit according to the control signal; the dynamic adjustment includes adjusting read or write or execution permissions of the physical page, and disrupting an access sequence of the translation lookaside buffer cache. According to the method, the limitation that traditional static permission configuration cannot adapt to the dynamic running state of the process is solved; and the MMU cannot detect and block hostile attacks in real time, so that the safety and the flexibility of MMU authority management are improved.

For managing a translation lookaside buffer (TLB), an example computing device is deployed with virtual machines (VMs) by using a virtual machine monitor and has multiple CPU cores, where the VMs include a common VM running a common execution environment and a secure VM running a trusted execution environment (TEE) instance. In an example, in response to a target request for modifying a secure memory, the common execution environment sends an inter-processor interrupt (IPI) to one or more CPU cores that run the secure VM. Control data corresponding to the secure VM include a TLB control field set to a target value that indicates that all TLBs of the VM are flushed when exiting from the secure VM. In response to the IPI, the one or more CPU cores exit from a secure mode, and flushes all TLBs of the VM based on the target value.

The application provides a method, device, electronic equipment and computer program product for increasing the storage information density of a translation lookaside buffer. In the method, when an address translation request of a first virtual address is received, a plurality of continuous address mapping data is obtained according to the first virtual address, each address mapping data containing a mapping relationship between a virtual address and a physical address; when the plurality of continuous address mapping data satisfies a preset merging condition, the plurality of continuous address mapping data is merged into one merged entry; the merged entry is stored in the translation lookaside buffer, and a target physical address corresponding to the first virtual address is returned to an address request unit according to the merged entry. Thus, by merging the plurality of continuous address mapping data into a single entry and sharing the same high-bit part, the storage density of the effective address mapping is significantly improved while keeping the physical capacity of the translation lookaside buffer unchanged.

The application discloses a kind of translation lookaside buffer table entry processing method, system, medium and product, applied to processor technical field, comprising: when process switching, determine the non-critical table entry corresponding to the process before switching in translation lookaside buffer, obtain target non-critical table entry;The target non-critical table entry is stored in the first cache corresponding to processor core, and the target non-critical table entry is deleted from the translation lookaside buffer;The recovery deadline corresponding to the process before switching issued by operating system is acquired;Based on the recovery deadline, before switching back to the process before switching, the target non-critical table entry is written back to the translation lookaside buffer from the first cache.This way, in the case of guaranteeing the process before switching fast recovery, the hit rate of translation lookaside buffer table entry can be improved, and then the processor performance is improved.

Exploiting virtual address (VA) spatial locality using translation lookaside buffer (TLB) entry compression in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a TLB, comprising multiple TLB entries each comprising a tag and a plurality of data portions, and further comprises a memory management unit (MMU). The MMU is configured to receive a memory access request comprising a VA, and determine that a TLB access to the TLB for a page VA of the VA results in a miss. In response, the MMU generates a TLB entry, wherein the tag of the TLB entry comprises the page VA, the plurality of data portions comprises a corresponding plurality of page PAs, a first data portion thereof comprising a page PA corresponding to the page VA, and one or more second data portions thereof comprising corresponding PAs of next sequential page VAs following the page VA.

An MMU with prefetch functionality is provided. The MMU includes a first TLB, burst buffer, second TLB and control logic. The first TLB is configured to fetch a first set of one or more first page table entries based, at least in part, on a virtual address, and before a request to access a client address is received from a client. The burst buffer stores a plurality of second page table entries from a respective page table associated with a first page table address. A second translation lookaside buffer is configured to fetch a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer based, at least in part, on the virtual address, and before the request to access a client address is received from the client.

An architecture of a computer processor providing a program counter (PC) for fetching instructions from a memory system comprises a program counter indexed address translation table (PCAT) having rows accessed with a program counter (PC) value, an entry in a row identifying a virtual memory address and a corresponding physical memory address. Translation between virtual memory addresses and the physical memory addresses is mediated by the PCAT holding the virtual and corresponding physical addresses. In some embodiments, this table can be accessed early in a fetch cycle and avoid likely translation lookaside buffer (TLB) misses.

Systems and methods are disclosed for logging guest physical address for memory access faults. For example, a method for logging guest physical address includes receiving a first address translation request from a processor pipeline at a translation lookaside buffer for a first guest virtual address; identifying a hit with a fault condition corresponding to the first guest virtual address; responsive to the fault condition, invoking a single-stage page table walk with the first guest virtual address to obtain a first guest physical address; and storing the first guest physical address with the first guest virtual address in a data store, wherein the data store is separate from an entry in the translation lookaside buffer that includes a tag that includes the first guest virtual address and data that includes a physical address.

A method includes executing, by a processor core, a first task; scheduling, by a scheduler, a second task to be executed by the processor core upon completion of executing the first task; responsive to scheduling the second task, providing, by the scheduler, a prewarming message to a memory management unit (MMU) coupled to the processor core; and responsive to receiving the prewarming message, fetching, by the MMU, a page table specified by a page table base of the prewarming message.

A neural processing device and a method of updating translation lookaside buffer thereof are provided. The neural processing device includes at least one processor module each of which includes at least one micro translation lookaside buffer (TLB), a hierarchical memory that is accessed by the at least one micro TLB, and a command processor configured to update the at least one micro TLB in a push mode by generating a first update signal which indicates update of the at least one micro TLB and transmitting the first update signal to the at least one micro TLB.

An electronic device and method with a single-level page table for obtaining physical addresses are disclosed. The operating method includes determining, in response to a process being executed, whether a mapping of a target physical address to a virtual address that the process is accessing is stored in a translation lookaside buffer (TLB); determining, in response to determining that the virtual address is not stored in the TLB, whether the process uses a single-level page table; and in response to determining that the process uses the single-level page table, obtaining the target physical address mapped to the virtual address based on accessing the single-level page table.

Certain aspects of the present disclosure provide techniques and apparatus for translation lookaside buffer (TLB) compression. Embodiments include determining that a plurality of physical memory addresses, associated with a plurality of virtual memory addresses, are contiguous with one another and share one or more common address bits or one or more common attribute bits, wherein each respective physical memory address of the plurality of physical memory addresses corresponds to a separate respective physical memory page. Embodiments include generating a tag for an entry in a TLB, the tag representing the plurality of virtual memory addresses. Embodiments include associating, in the entry in the TLB, the tag with data comprising: a single instance of the one or more common address bits or the one or more common attribute bits of the plurality of physical memory addresses; and other bits of the plurality of physical memory addresses.