System and Method to Invalidate Obsolete Address Translations

Abstract

A system and method for invalidating obsolete virtual / real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and / or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and / or processors or to multicast to designated cores and / or processors. The NCU may track completion of the demap operation across the cores and / or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention relates to multithreaded processors and, more specifically, to a hardware-based method for invalidating obsolete virtual to physical address translations and / or real to physical address translations.[0003]2. Description of the Related Art[0004]Modern computer systems typically include virtual memory space that is shared between multiple processors within a system. Virtual addresses are produced by the processors for each instruction fetch or load or store access to memory. Addresses within the virtual memory space are translated into physical memory addresses, which are used to access physical memory locations. These virtual to physical address translations are typically stored in page tables. In an effort to improve processor performance, a subset of the virtual to physical address translations stored in the page tables may be cached in translation lookaside buffers (TLBs). The TLBs may improve processor...

AI Technical Summary

Benefits of technology

[0007]Various embodiments of a system and method for invalidating obsolete virtual to physical address translations are disclosed. In some embodiments, translation lookaside buffers (TLBs) may be used to cache a subset of the virtual to physical address translations mapping virtual system memory t...

Problems solved by technology

A variety of system events may result in changes to the virtual memory space, thus rendering the virtual to physical address translations obsolete.

Processing software interrupts to support demapping operations across multiple cores within multiple processors in a system may require significant system overhead, which can result in decreased system performance.

As the number of cores within a processor and / or the number of processors within a system increases, the overhead required to process software interrupts for demap operations also increases, particularly for system applications that require frequent changes to the virtual memory space.

System events such as migration of virtual pages to disk storage may result in changes to the virtual memory space in a system, which may require that at least some of the virtual to physical address translations stored in one or more TLBs within a system are invalidated, or demapped.

In some embodiments, software may not be allowed to change the enabled status of a core when a global TLB demap request is in process.

Disabling a core during processing of a TLB demap operation may result in the system hanging, as the NCU may wait indefinitely for acknowledgment from the disabled core.

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