5 results about "Cache page" patented technology

This application relates to the field of memory access technology, and discloses a method, apparatus, electronic device, and storage medium for processing address access signals. The method for processing address access signals includes: configuring and generating a page height cache region in volatile memory; configuring at least one mapping register according to the page height cache region, such that the mapping register corresponds one-to-one with the page height cache pages; when it is determined that the address access signal is an access to non-volatile memory, traversing all configured mapping registers and determining whether the first page number of one of them is the same as the page number accessed by the address access signal; if not, keeping the page number accessed by the address access signal unchanged; if it is, remapping the page number accessed by the address access signal to the second page number stored in the matched mapping register. The address access signal processing method according to the embodiments of this application can optimize time overhead when processing address access signals.

A data query method, medium, equipment and program product based on a cloud search service, relate to the technical field of computers, and the data of all pages included in the file maintained by the cache page of the local cache file is stored, when a query request is received, the first offset information of the target page and the first file identifier to which the query request is directed are determined through the file metadata, the first offset information is used to point to the cache page in the local cache file for storing the pages included in the file, and the data corresponding to the target page is read from the local cache file based on the first offset information and the first file identifier. Since the first offset information for pointing to the cache page in the local cache file for storing the pages included in the file is included in the file metadata, each cache page corresponds to a piece in the local cache file, and the use of hash calculation can be avoided when data is read, thereby improving the performance of data reading.

This invention relates to the field of redundancy verification technology, specifically to an on-board intelligent AI data processing method for a dual-machine cold backup architecture, comprising the following steps: acquiring the task record sequence of the primary and backup channels, excluding paths based on node misalignment, identifying sequence difference segments, locating the corresponding structure, extracting cache pages and jump instructions to determine the connection direction, completing the jump chain, comparing variable paths to replace differing addresses, and inserting access numbers to complete the scheduling structure. In this invention, path filtering is performed based on the response timing differences of the primary and backup channels, structural matching is completed by combining the scheduling index and node misalignment relationships, the task segment order is located according to the primary task arrangement, jump breakpoints are extended according to page number trends, adjacent page directions guide jump chain completion, variable paths are filtered and replaced based on address consistency to construct path mapping, and the path access order is referenced to the scheduling rhythm to complete the structural connection. The task sequence maintains consistency in path continuation, jump connection, and variable path distribution.

The application discloses a graph processing system cache method, a controller and a system for a BFS algorithm, belongs to the technical field of performance optimization of a graph processing system, and comprises the following steps: based on the relationship between the access heat of a cache page and the number of unvisited vertices in the BFS algorithm, more accurate heat grading management is implemented on the cache page, when the cache is full, the page with low access potential is effectively eliminated, and the cache hit rate is improved; fragmented effective edge data is extracted from the cache page and separately stored in a cache managed in a fine granularity; by acquiring the proportion of the edge list of the vertex in the BFS algorithm task queue that has been resident in the cache, and in combination with the vertex out-degree and other attributes, the scheduling order of the vertex in the task queue is adjusted, and the data that has been resident in the cache is maximally utilized. The application can effectively improve the cache hit rate of the graph processing system when processing the BFS algorithm task, and further realizes the improvement of the access performance of the graph processing system.

Embodiments of the present application disclose a page caching method, device and equipment and a storage medium. The method comprises: when a page jump request is received, determining a to-be-cached page associated with the page jump request; updating a global page array according to a page identifier of the to-be-cached page, wherein the global page array is created in a storage instance of an interface construction framework project; and caching page information corresponding to the page identifier into a memory according to the page identifier contained in the global page array. By using the method, the page identifier of the to-be-cached page is dynamically maintained in the global page array, and the page corresponding to the page identifier contained in the global page array is dynamically cached into the memory according to the page identifier, thereby realizing unified management of the cached pages, solving the problem of manually updating the page cache, reducing the amount of code writing for the cached pages, and improving system performance and user experience.