Patents
Literature
Patsnap Eureka AI that helps you search prior art, draft patents, and assess FTO risks, powered by patent and scientific literature data.

17 results about "Cache page" patented technology

Method and apparatus for writing data to disk array in storage system

The embodiment of the invention relates to a method, equipment and a computer program product for writing data into a disk array in a storage system. The storage system includes a disk array. A method includes, in response to receiving a write request to write new data to a data block in at least one disk array group in a degraded mode of a disk array, reading old data stored in the data block and old check information stored in a check block associated with the data block. The method further includes determining new check information associated with the new data based on the old data, the old check information, and the new data. The method further includes writing the new data and the new check information into at least one cache page provided by a cache component in the storage system, the at least one cache page being allocated in a persistent memory in the cache component. In addition, the method further comprises the step of flushing new data and new verification information into the data blocks and the verification blocks in the at least one disk array group respectively.
Owner:EMC IP HLDG CO LLC

File caching performance improving method and system based on distributed storage

PendingCN121722325AInput/output to record carriersVirtual file systemFile system
The invention discloses a file caching performance improvement method and system based on distributed storage, and the method comprises the steps: firstly obtaining first file caching information of a to-be-cached file in a local caching node, the information comprises at least one of IO mode information generated through an improved virtual file system read-write function, cache page IO type marks and memory state information collected through a memory monitoring thread; inputting the first file cache information into a pre-trained first cache strategy model to obtain a file cache feature vector; the feature vector is sent to a remote storage node, the remote node inputs the feature vector and second file cache information of the to-be-cached file into a pre-trained second cache strategy model together, and a final cache instruction is obtained; and the local node executes cache strategy adjustment according to the instruction. According to the method, global collaborative intelligent optimization of the cache strategy is realized, and the cache hit rate and the system response performance are remarkably improved.
Owner:BEIJING YAN RONG TECH CO LTD

Method for memory management and device therefor

The application provides a memory management method and device, which can be used for fine management of process access conditions and traffic occupancy conditions of various cgroups in a physical host, a virtual machine or a container. The method comprises the following steps: recording all cgroups that read and write target data in a target cache page and the number of times that the cgroups read or write the target data in the target cache page through a first record table corresponding to the target cache page, so as to improve the accuracy of traffic statistical results of the cgroups. At this time, flow limiting is performed on the first cgroup based on the updated first record table, so that the flow limiting of the first cgroup is more fair and accurate.
Owner:HUAWEI TECH CO LTD

A large language model low-latency inference method based on dynamic inference graph optimization

The application discloses a large language model low-delay inference method based on dynamic inference graph optimization, and proposes a low-delay inference method based on dynamic inference graph optimization; a rewritable and replayable template inference graph is constructed, and a template library is established according to an input shape vector; during inference, a template is matched according to a distance threshold value, and only attention / forward subgraphs are locally recaptured when the threshold value is exceeded; a forward execution graph injects a key-value cache page pointer, a numerical precision and an adapter identifier, and is replayed; pre-populated and decoded subgraphs are divided to implement a graph-level scheduling; a key operator is switched between a standard / quick kernel and different precisions during operation; a page-level rollback of a speculative branch is realized through a shadow page table and a reference count, and a batch and a template selection are adaptively adjusted based on online indicators; compared with existing schemes, the application reduces recapture and startup overhead, suppresses tail delay and jitter, and improves hardware utilization and service stability.
Owner:FUJIAN SUDIAN INFORMATION TECH CO LTD

Page loading method, device, apparatus and storage medium

Embodiments of the present application provide a page loading method, device, apparatus and storage medium. In the embodiments of the present application, new configuration attribute information is added for a single-page application. For a scenario of returning to a first page from a second page, according to configuration attribute information of the first page, a holding attribute of the first page and a target cache page of the first page can be obtained. In a case where the holding attribute of the first page is persistent holding and the target cache page of the first page is the second page, according to an identifier of the first page, historical state information of the first page is obtained from cached historical state information, and the first page is loaded according to the historical state information of the first page, so that selective saving and loading of the historical state information of the first page are implemented, which helps to improve flexibility of loading of the first page.
Owner:上海瑞家信息技术有限公司

Algorithm module scheduling method

The invention relates to the technical field of algorithm module scheduling, and discloses an algorithm module scheduling method, which comprises the following steps of: firstly, acquiring a page size, a total page budget, a draft acceptance rate, a draft module service rate and a verification module service rate of a key value cache; calculating the expected length of the accepted prefix according to the draft acceptance rate, and determining the target draft drawing depth of the accepted prefix aligned with the integral multiple of the page size; calculating single-request peak page occupation according to the target draft depth, and obtaining the maximum concurrent micro-batch capacity in combination with the total page budget; further determining a beat period based on the service rates of the draft module and the verification module; and finally, mapping the requests to a fixed time coordinate and slot position according to an arrival sequence, and outputting a scheduling result containing the target draft depth and the mapping relationship. According to the method, the high utilization rate of the cache page can be realized under the condition that the page resources are fixed, the periodic fluctuation of the concurrent capacity is eliminated, and the overall execution efficiency and stability of a multi-module algorithm system are remarkably improved.
Owner:BEIJING DARONGXIN TECHNOLOGY GROUP CO LTD

Methods, apparatuses, electronic devices, and storage media for processing address access signals

This application relates to the field of memory access technology, and discloses a method, apparatus, electronic device, and storage medium for processing address access signals. The method for processing address access signals includes: configuring and generating a page height cache region in volatile memory; configuring at least one mapping register according to the page height cache region, such that the mapping register corresponds one-to-one with the page height cache pages; when it is determined that the address access signal is an access to non-volatile memory, traversing all configured mapping registers and determining whether the first page number of one of them is the same as the page number accessed by the address access signal; if not, keeping the page number accessed by the address access signal unchanged; if it is, remapping the page number accessed by the address access signal to the second page number stored in the matched mapping register. The address access signal processing method according to the embodiments of this application can optimize time overhead when processing address access signals.
Owner:BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD

Accelerated access method and system of memory

PendingCN121579386AMemory systemsAccess methodCache page
The invention discloses an accelerated access method and system for a memory, and the method comprises the steps: judging whether a read address hits a data cache page or not when receiving an access request and a read request of host equipment, and directly taking and returning data if the read address hits the data cache page; and if not, triggering data prefetching, prefetching data from the off-chip memory according to the configurable cache page capacity by taking the read address as an initial address, storing the data into the cache page, and returning the data of the read request at the time. When a write request is requested, judging whether a write address hits the data cache page or not, if yes, setting the corresponding data cache page to be invalid, and sending the write request to the off-chip memory to execute write operation; if not, the corresponding data cache page is kept valid, and the write request is sent to the off-chip memory to execute write operation. The invention aims to realize efficient, flexible and safe accelerated access to the off-chip memory; the problems that in the prior art, an effective acceleration mechanism for off-chip memory access is lacked, the cache structure capacity is fixed and lacks configurability and is difficult to adapt to different application requirements, and a data security risk exists due to an imperfect data consistency maintenance mechanism are solved, so that the execution efficiency of a chip system is improved. The adaptability of the system in different application scenes is enhanced, and the system reliability and the data security are ensured.
Owner:XIAN MICROELECTRONICS TECH INST

Dynamic quantization and memory management of key value caches for serving large language models

A key value (KV) cache paging scheme may improve memory management for a KV cache by storing KV cache pages having key tensors and value tensors for a fixed number of tags in a fixed size block in the KV cache of a worker. To further improve memory management, these schemes may be modified to achieve dynamic variable quantization. The quantization level of the KV cache page may be set based on the runtime importance score of the KV cache page. In addition, the quantization level of the KV cache page may be set based on the system load. And the final result is a scheme capable of realizing the high compression ratio of the KV cache page in the KV cache. The loading of more KV cache pages in the KV cache can bring higher reasoning throughput, higher system-level user capacity and higher end-to-end service availability.
Owner:INTEL CORP

Method and system for displaying organizational structure information

The invention belongs to the technical field of computers, and particularly relates to an organizational structure information display method and system. According to the method, the complete organizational structure tree data is loaded to the front end at one time, so that interaction delay caused by frequent network requests in a traditional lazy loading scheme is avoided, operations such as unfolding and folding of a user can be instantly responded on the basis of local data, and the user experience is improved for the loaded total data. Through a mode of dynamically removing visual elements corresponding to all brother nodes of a current target node, only a small number of nodes on a current focusing path need to be rendered at any moment, so that the situation of interface jamming caused by one-time full-amount rendering in a traditional mode is avoided, and through cache paging and a selected state, the page rendering efficiency is improved. And all child nodes under the father node are mounted again during the folding operation, so that the smooth unfolding, folding and batch operation experience is provided while the large-scale hierarchical data is efficiently processed.
Owner:SUZHOU WANDIANZHANG NETWORK TECH CO LTD

Data query method, medium, device and program product based on cloud search service

ActiveCN121009061BCache pageData query
A data query method, medium, equipment and program product based on a cloud search service, relate to the technical field of computers, and the data of all pages included in the file maintained by the cache page of the local cache file is stored, when a query request is received, the first offset information of the target page and the first file identifier to which the query request is directed are determined through the file metadata, the first offset information is used to point to the cache page in the local cache file for storing the pages included in the file, and the data corresponding to the target page is read from the local cache file based on the first offset information and the first file identifier. Since the first offset information for pointing to the cache page in the local cache file for storing the pages included in the file is included in the file metadata, each cache page corresponds to a piece in the local cache file, and the use of hash calculation can be avoided when data is read, thereby improving the performance of data reading.
Owner:BEIJING VOLCANO ENGINE TECH CO LTD

Intelligent AI data processing method on satellite of dual-computer cold backup architecture

This invention relates to the field of redundancy verification technology, specifically to an on-board intelligent AI data processing method for a dual-machine cold backup architecture, comprising the following steps: acquiring the task record sequence of the primary and backup channels, excluding paths based on node misalignment, identifying sequence difference segments, locating the corresponding structure, extracting cache pages and jump instructions to determine the connection direction, completing the jump chain, comparing variable paths to replace differing addresses, and inserting access numbers to complete the scheduling structure. In this invention, path filtering is performed based on the response timing differences of the primary and backup channels, structural matching is completed by combining the scheduling index and node misalignment relationships, the task segment order is located according to the primary task arrangement, jump breakpoints are extended according to page number trends, adjacent page directions guide jump chain completion, variable paths are filtered and replaced based on address consistency to construct path mapping, and the path access order is referenced to the scheduling rhythm to complete the structural connection. The task sequence maintains consistency in path continuation, jump connection, and variable path distribution.
Owner:BEIJING NORMAL UNIVERSITY

Cache management method and device, server and computer readable storage medium

This application discloses a cache management method, apparatus, server, and computer-readable storage medium, belonging to the field of storage technology. The method includes: a host determining the "hotness" information of multiple cache pages based on access information sent by multiple virtual machines; multiple virtual machines processing multiple cache pages based on the "hotness" information sent by the host, thereby reducing the memory footprint of cache pages on virtual machines and improving memory utilization efficiency. Because this method manages multiple cache pages using "hotness" information, the computational overhead is relatively small, enabling highly efficient cache management.
Owner:HUAWEI TECH CO LTD +1

Disk refreshing method and system for database cache page

The invention provides a disk refreshing method and system for database cache pages, and relates to the technical field of databases. A plurality of cache pages are arranged in a database cache layer, when a first cache page meets a disk refreshing condition, a second cache page is determined in a memory to serve as a data transfer page, access limitation on the first cache page is released immediately after data of the first cache page is synchronized to the second cache page, and disk refreshing operation is executed asynchronously by the second cache page. By adopting a lock replacement mechanism, the lock holding time of the source data page is shortened from a complete disk refreshing process containing disk IO to a data synchronization process only containing memory replication, and the locking time is remarkably shortened. In addition, one-time disk refreshing is carried out after the data of the multiple cache pages are merged and synchronized to the single cache page, and the IO mode of the disk is effectively optimized. According to the method, direct disk writing is replaced by memory data copying, so that the concurrency performance and throughput of a database system are greatly improved while the data consistency is ensured.
Owner:FUJIAN YANGTENG INNOVATION INFORMATION TECHNOLOGY CO LTD

BFS algorithm-oriented graph processing system caching method, controller and system

ActiveCN121071250BShardAlgorithm
The application discloses a graph processing system cache method, a controller and a system for a BFS algorithm, belongs to the technical field of performance optimization of a graph processing system, and comprises the following steps: based on the relationship between the access heat of a cache page and the number of unvisited vertices in the BFS algorithm, more accurate heat grading management is implemented on the cache page, when the cache is full, the page with low access potential is effectively eliminated, and the cache hit rate is improved; fragmented effective edge data is extracted from the cache page and separately stored in a cache managed in a fine granularity; by acquiring the proportion of the edge list of the vertex in the BFS algorithm task queue that has been resident in the cache, and in combination with the vertex out-degree and other attributes, the scheduling order of the vertex in the task queue is adjusted, and the data that has been resident in the cache is maximally utilized. The application can effectively improve the cache hit rate of the graph processing system when processing the BFS algorithm task, and further realizes the improvement of the access performance of the graph processing system.
Owner:HUAZHONG UNIV OF SCI & TECH

A file loading method, a computing device and a storage medium

The application discloses a file loading method, a computing device and a storage medium, and comprises the following steps: judging whether a first memory module corresponding to a first node where a process is located is constructed with a file cache page; if not, determining cache page information of the file according to file information of the file; judging whether the second node is the same as the first node; if not, migrating the process to the second node; allocating a file cache page in a second memory module; and loading the file into an internal storage according to the file cache page allocated in the second memory module. When the process needs to load the file and no file cache page is applied, the application judges whether a node where a historical file cache page of the file is located is consistent with the node where the process is located; the integrity of the file in the internal module is ensured; and the process is migrated to the node where the historical file cache page is located, so that the file is read and written according to the local memory of the node, and the read and write efficiency of the file by the multiple processes is improved.
Owner:UNIONTECH SOFTWARE TECH CO LTD