12 results about "Scalar processor" patented technology

A scalar processor associated with a vector processor reduces the quantization error for blocked data with a relatively small register size by predicting adjustments for shared scalars used in runtime quantization. The scalar processor provides a recommended scale value to the vector processor for scaling a block of data from a wide data type format to a narrow data type format. The scalar processor and the vector processor share a register at which the scalar processor stores the recommended scale value and from which the vector processor accesses the recommended scale value. The vector processor performs an operation to quantize at least a portion of the block of data by applying a scale value that is based on the recommended scale value.

This application provides an address comparison and checking method, scalar processor, and device for a compressed issue queue. The method acquires a first instruction and a second instruction from the compressed issue queue; and obtains an address comparison and checking result based on the address correlation between the first instruction and each second instruction. Furthermore, a comparison and checking result vector is formed, and this vector is updated in advance based on the instruction status in the compressed issue queue in the next cycle. This method, by obtaining the address comparison and checking result based on the address correlation between the first instruction and each second instruction, can flexibly support diverse memory access granularities with a small hardware area overhead while ensuring processor performance (timing). Additionally, by calculating the next state of the comparison and checking result in advance based on the enqueue / dequeue status of the issue queue determined in the current cycle, and updating it directly in the next cycle, it ensures a one-to-one correspondence between the address comparison and checking result and the new instruction position in the issue queue, while also optimizing timing.

A scalar of a display device of an information handling system includes a scalar processor and zero-gray luminance enhancer. The scalar processor generates image data by processing raw image data, including grayscale levels, received from the information handling system. The image data is used by the display device to control pixels of a display screen of the display device in rendering images on the display screen. The zero-gray luminance enhancer generates zero-gray enhancement values, each zero-gray enhancement value uniquely corresponding to one of the grayscale levels. The zero-gray enhancement values control luminance associated with the pixels.

A scalar of a display device of an information handling system includes a scalar processor and zero-gray luminance enhancer. The scalar processor generates image data by processing raw image data, including grayscale levels, received from the information handling system. The image data is used by the display device to control pixels of a display screen of the display device in rendering images on the display screen. The zero-gray luminance enhancer generates zero-gray enhancement values, each zero-gray enhancement value uniquely corresponding to one of the grayscale levels. The zero-gray enhancement values control luminance associated with the pixels.

The application provides a high-performance processing method and an electronic device. The method comprises the following steps: a scalar processor acquires instructions and parameters from a global memory; and the scalar processor calls a vector processor to execute a task based on the parameters after determining that an execution condition is met. According to the method provided by the application, after the scalar processor acquires the instructions and the parameters from the global memory, the scalar processor calls the vector processor to execute the task based on the parameters when it is determined that the execution condition is met, and then multiple heterogeneous cores are coordinately used to meet different computing requirements.

Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.

According to the automatic superscale processor design method based on the learning data dependency relationship, the superscale processor supporting instruction-level parallelism is automatically designed by learning data dependency between instructions, and the defect that dynamic dependency cannot be processed in the prior art is overcome. According to the technical scheme, dependency prediction is achieved based on a hardware-friendly machine learning model, and the most reusable state is selected from a high-dimensional processor state space through a state selector and stored in a small buffer area; and the state speculator is used for generating a hardware predictor by utilizing the selected state high-precision prediction dependence data and integrating the hardware predictor into the superscalar processor. The predictor is obtained by training a machine learning model S-BSD and comprises a state selector and a state speculator. According to the scheme, low-delay and high-precision prediction is achieved under the condition that hardware resources are limited, and parallel execution of multiple instructions is supported.

The application provides a scalar processor, a high-performance processor and an electronic device, the scalar processor comprising: a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit; wherein the synchronization unit is configured to synchronize the scalar processor and a vector processor. The scalar processor provided by the application synchronizes the scalar processor and the vector processor through the synchronization unit, thereby efficiently executing instructions.

A scalar processor (142) associated with a vector processor (140) reduces the quantization error for blocked data with a relatively small register size by predicting adjustments for shared scalars used in runtime quantization. The scalar processor provides a recommended scale value (210) to the vector processor for scaling a block of data from a wide data type format to a narrow data type format. The scalar processor and the vector processor share a register (206) at which the scalar processor stores the recommended scale value and from which the vector processor accesses the recommended scale value. The vector processor performs an operation to quantize at least a portion of the block of data (412) by applying a scale value that is based on the recommended scale value.

This invention belongs to the field of pipelined interaction chips, and provides a scalar-vector heterogeneous pipelined interaction chip and interaction method. The scalar-vector heterogeneous pipelined interaction chip includes a scalar processor, a vector coprocessor, and a cross-queue module. The scalar processor has a scalar pipeline, and the vector coprocessor has a vector pipeline. The scalar processor decodes the fetched vector instructions and divides them into two data streams. One data stream directly sends the vector instructions to the vector coprocessor for vector pipeline execution. The other data stream sends the vector instruction ID and the decoded scalar register number to the cross-queue module. The cross-queue module allocates an entry for each vector instruction requiring scalar operands, thereby achieving decoupled interaction between the scalar pipeline and the vector pipeline, significantly improving the execution efficiency of scalar threads and the overall system instruction throughput.

The application provides a method and device for processing an image. The method comprises: obtaining image data; calculating filter weight coefficients of the image data by using a first processing unit and a second processing unit, wherein the filter weight coefficients of the image data comprise filter weight coefficients corresponding to first data elements and filter weight coefficients corresponding to second data elements, the filter weight coefficients corresponding to the first data elements and the filter weight coefficients corresponding to the second data elements comprise a first part with the same value and a second part with different values, the first part is calculated by the first processing unit, and the second part is calculated by the second processing unit, wherein the first processing unit is a vector processor, and the second processing unit is a vector processor or a scalar processor. The application can use the first processing unit to perform the calculation of the data with the same value in the filter weight coefficients, so that the part that needs to be repeatedly calculated only needs to be calculated once, the amount of calculation is reduced, and the operation efficiency is improved.

The application provides a method for instruction fusion using a superscalar processor and related equipment. A decoding unit obtains first instruction control signals of multiple instructions to be executed, and sends the first instruction control signals to a fusion decoding unit. The fusion decoding unit determines, for any one of at least one instruction pair, that a first instruction in the any one instruction pair is an I-type instruction, a second instruction in the any one instruction pair is an I-type instruction or an R-type instruction, and judges whether there is an instruction pair matching the any one instruction pair in a plurality of preset instruction pairs. If there is, instruction fusion is performed under the condition that a source operand of the first instruction is equal to a destination operand of the first instruction and the destination operand of the first instruction is equal to at least one source operand of the second instruction, to obtain a fusion instruction. A fusion instruction execution unit executes the fusion instruction according to an operation logic of the fusion instruction.