24 results about "Scalar processor" patented technology

Processors, systems and methods are provided for thread level parallel processing. A processor may include a sequencer and a plurality of columns of vector processing units coupled to the sequencer. The sequencer may include a scalar instruction decoder, a vector instruction decoder, and a plurality of scalar processors configured to concurrently execute one or more scalar instructions decoded by the scalar instruction decoder to generate one or more vectors of parameters. The vector instruction decoder may be configured to decode one or more vector instructions to generate a set of configurations with the one or more vectors of parameters embedded as one or more vectors of immediate values and send the configurations to a target column. Each column of vector processing units may be configured to repeatedly execute the vector operations in the configurations using one or more respective elements of one or more vectors of immediate values per repetition.

The invention discloses an asynchronous parallel processing method and system for address correlation in a superscalar processor, after an instruction data packet enters a transmitting unit, instructions are sent to a corresponding transmitting queue according to the type of each instruction, the transmitting queue requests to transmit the instructions in a polling mode, and when the selected instruction meets a transmitting condition, the selected instruction is transmitted; in one round of instructions, the Load instructions are grouped by taking the Store instructions as boundaries, and the Load instructions in the groups are executed out of order; after the memory access instruction enters the memory access stage, when the Store instruction is executed, the Store instruction is temporarily stored in the buffer table, when the Load instruction is executed, whether address correlation exists between the current Load instruction and the Store instruction in the buffer table or not is detected, if the address correlation does not exist, the internal access number is accessed, and if the address correlation exists, the number is fetched from the buffer table. On the basis of the design of the asynchronous circuit, a memory access instruction part out-of-order execution and memory access instruction address correlation processing mechanism is introduced, the memory access instruction throughput efficiency of the superscalar processor is improved, and the instruction execution speed and processing efficiency are improved.

The invention provides a high-performance processor, a processor cluster and electronic equipment. The high-performance processor comprises a scalar processor, a vector processor and a local memory, the scalar processor and the vector processor share a local memory; the vector processor only accesses the local memory and is only called and executed by the scalar processor; connection is established between the scalar processor and the vector processor; the scalar processor is connected with the global memory; the scalar processor is used for acquiring instructions and parameters from the global memory; and after the scalar processor determines that the execution condition is met, calling the vector processor to execute the parameter-based execution task. According to the high-performance processor provided by the invention, after the scalar processor obtains the instruction and the parameter from the global memory, when the execution condition is determined to be met, the vector processor is called to execute the task based on the parameter, so that a plurality of heterogeneous cores are cooperatively used to meet different calculation requirements.

The invention provides a scalar processor, a high-performance processor and electronic equipment, and the scalar processor comprises an instruction fetching unit, a register renaming unit, an operation reservation stack unit, a storage reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit and a register file unit, a special vector register file unit; wherein the synchronization unit is used for synchronizing the scalar processor and the vector processor. According to the scalar processor provided by the invention, the synchronization of the scalar processor and the vector processor is realized through the synchronization unit, so that an instruction is efficiently executed.

The invention discloses a double-write-back embedded scalar processor micro-architecture, which belongs to the technical field of embedded scalar processors, and comprises an arbitration component for arbitrating a program counter value flowing into an assembly line; the instruction fetching part is used for acquiring instruction data; the decoding component is used for acquiring a memory access operation code and a memory access operand when the instruction is a memory access instruction, and acquiring a non-memory access operation code and a non-memory access operand when the instruction is a non-memory access instruction; the execution component is used for calculating a memory access address according to the memory access operand; executing the non-memory access instruction according to the non-memory access operation code and the non-memory access operand to obtain a non-memory access instruction execution result; the memory access component is used for executing the memory access instruction according to the memory access operation code and the memory access address to obtain memory access data; and the write-back component is used for executing write-back operation of the memory access instruction and / or the non-memory access instruction according to the memory access data and / or the non-memory access instruction. According to the double-write-back embedded scalar processor micro-architecture, the performance, reliability and flexibility of an embedded scalar processor can be improved, and power consumption can be reduced.

A scalar processor associated with a vector processor reduces the quantization error for blocked data with a relatively small register size by predicting adjustments for shared scalars used in runtime quantization. The scalar processor provides a recommended scale value to the vector processor for scaling a block of data from a wide data type format to a narrow data type format. The scalar processor and the vector processor share a register at which the scalar processor stores the recommended scale value and from which the vector processor accesses the recommended scale value. The vector processor performs an operation to quantize at least a portion of the block of data by applying a scale value that is based on the recommended scale value.

This application provides an address comparison and checking method, scalar processor, and device for a compressed issue queue. The method acquires a first instruction and a second instruction from the compressed issue queue; and obtains an address comparison and checking result based on the address correlation between the first instruction and each second instruction. Furthermore, a comparison and checking result vector is formed, and this vector is updated in advance based on the instruction status in the compressed issue queue in the next cycle. This method, by obtaining the address comparison and checking result based on the address correlation between the first instruction and each second instruction, can flexibly support diverse memory access granularities with a small hardware area overhead while ensuring processor performance (timing). Additionally, by calculating the next state of the comparison and checking result in advance based on the enqueue / dequeue status of the issue queue determined in the current cycle, and updating it directly in the next cycle, it ensures a one-to-one correspondence between the address comparison and checking result and the new instruction position in the issue queue, while also optimizing timing.

A scalar of a display device of an information handling system includes a scalar processor and zero-gray luminance enhancer. The scalar processor generates image data by processing raw image data, including grayscale levels, received from the information handling system. The image data is used by the display device to control pixels of a display screen of the display device in rendering images on the display screen. The zero-gray luminance enhancer generates zero-gray enhancement values, each zero-gray enhancement value uniquely corresponding to one of the grayscale levels. The zero-gray enhancement values control luminance associated with the pixels.

A RISC-V vector memory access processing system and processing method, the processing system includes a scalar-vector dispatch unit that can transmit data to each other, a scalar-vector instruction hysteresis monitoring unit and a scalar-vector memory access unit, and a decoding unit and a system status register connected to the scalar-vector dispatch unit, the decoding unit is also connected to an instruction memory, a vector register and a scalar register; the scalar-vector memory access unit is connected to a data bus and a vector write-back arbitration unit, and the vector write-back arbitration unit is also connected to the vector register and the scalar register. The present invention only adds a small number of hardware function units on the basis of the existing scalar processing system, improves the memory access capability of the scalar processor to vector data, reduces the invalid dispatch-cancellation time of the processor, and greatly improves the processing efficiency of the scalar processor to vector data.

Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

The invention provides an RISC-V superscale processor performance optimization method and system based on a Gem5 platform, and relates to the technical field of processor structure optimization. An instruction set architecture and an RISC-V superscale processor overall architecture are set on the Gem5 platform; according to the pipeline characteristics of the overall architecture of the RISC-V superscalar processor, each pipeline stage is divided into a front-end module, a middle-end module and a rear-end module; setting performance test parameters for the front end, the middle end and the rear end respectively, performing performance test on the front end, the middle end and the rear end based on the performance test parameters, and positioning a performance bottleneck and a bottleneck part of the processor according to a test result; according to the performance bottleneck and the specific bottleneck part, local architecture optimization adjustment is carried out, a progressive multi-level optimization process is set, the performance bottleneck and the bottleneck part of the RISC-V superscale processor are subjected to modular and overall optimization work, and the optimization modeling process of the RISC-V superscale processor is completed.

A scalar of a display device of an information handling system includes a scalar processor and zero-gray luminance enhancer. The scalar processor generates image data by processing raw image data, including grayscale levels, received from the information handling system. The image data is used by the display device to control pixels of a display screen of the display device in rendering images on the display screen. The zero-gray luminance enhancer generates zero-gray enhancement values, each zero-gray enhancement value uniquely corresponding to one of the grayscale levels. The zero-gray enhancement values control luminance associated with the pixels.

Processors, systems and methods are provided for thread level parallel processing. A processor may include a sequencer and a plurality of columns of vector processing units coupled to the sequencer. The sequencer may include a scalar instruction decoder, a vector instruction decoder, and a plurality of scalar processors configured to concurrently execute one or more scalar instructions decoded by the scalar instruction decoder to generate one or more vectors of parameters. The vector instruction decoder may be configured to decode one or more vector instructions to generate a set of configurations with the one or more vectors of parameters embedded as one or more vectors of immediate values and send the configurations to a target column. Each column of vector processing units may be configured to repeatedly execute the vector operations in the configurations using one or more respective elements of one or more vectors of immediate values per repetition.

The application provides a high-performance processing method and an electronic device. The method comprises the following steps: a scalar processor acquires instructions and parameters from a global memory; and the scalar processor calls a vector processor to execute a task based on the parameters after determining that an execution condition is met. According to the method provided by the application, after the scalar processor acquires the instructions and the parameters from the global memory, the scalar processor calls the vector processor to execute the task based on the parameters when it is determined that the execution condition is met, and then multiple heterogeneous cores are coordinately used to meet different computing requirements.

Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.

The invention provides a high-performance processing method and electronic equipment. The method comprises the steps that a scalar processor obtains instructions and parameters from a global memory; after the scalar processor determines that execution conditions are met, the vector processor is called to execute the task based on the parameters. According to the method provided by the invention, after the scalar processor obtains the instruction and the parameter from the global memory, when the execution condition is determined to be met, the vector processor is called to execute the task based on the parameter, so that the plurality of heterogeneous cores are cooperatively used to meet different calculation requirements.

According to the automatic superscale processor design method based on the learning data dependency relationship, the superscale processor supporting instruction-level parallelism is automatically designed by learning data dependency between instructions, and the defect that dynamic dependency cannot be processed in the prior art is overcome. According to the technical scheme, dependency prediction is achieved based on a hardware-friendly machine learning model, and the most reusable state is selected from a high-dimensional processor state space through a state selector and stored in a small buffer area; and the state speculator is used for generating a hardware predictor by utilizing the selected state high-precision prediction dependence data and integrating the hardware predictor into the superscalar processor. The predictor is obtained by training a machine learning model S-BSD and comprises a state selector and a state speculator. According to the scheme, low-delay and high-precision prediction is achieved under the condition that hardware resources are limited, and parallel execution of multiple instructions is supported.

The application provides a scalar processor, a high-performance processor and an electronic device, the scalar processor comprising: a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit; wherein the synchronization unit is configured to synchronize the scalar processor and a vector processor. The scalar processor provided by the application synchronizes the scalar processor and the vector processor through the synchronization unit, thereby efficiently executing instructions.

The present invention discloses a RISC-V vector processing unit implementation method, which is based on the RISC-V processor vector extension set and implemented in a coprocessor mode. The vector processing unit includes four ports, namely, a main processor interaction port, a vector instruction request port, a vector instruction feedback port, and a vector instruction memory write port. The vector processing unit includes a three-level pipeline, supports sequential dispatch, out-of-order execution, and out-of-order writeback, including decoding and dispatching, execution, writeback and delivery, and its instruction fetching and partial decoding are completed in a scalar processor. The decoding and dispatching are used as the first-level pipeline to decode and pipeline conflict judgment of the vector instruction when the vector unit receives the vector instruction of the main processor. If there is no pipeline conflict, it can be dispatched, the execution is used as the second-level pipeline for the execution of the vector instruction, and the writeback is used as the third-level pipeline for the writeback of the vector instruction, including writing back a scalar register and writing back a vector register.

A scalar processor (142) associated with a vector processor (140) reduces the quantization error for blocked data with a relatively small register size by predicting adjustments for shared scalars used in runtime quantization. The scalar processor provides a recommended scale value (210) to the vector processor for scaling a block of data from a wide data type format to a narrow data type format. The scalar processor and the vector processor share a register (206) at which the scalar processor stores the recommended scale value and from which the vector processor accesses the recommended scale value. The vector processor performs an operation to quantize at least a portion of the block of data (412) by applying a scale value that is based on the recommended scale value.

This invention belongs to the field of pipelined interaction chips, and provides a scalar-vector heterogeneous pipelined interaction chip and interaction method. The scalar-vector heterogeneous pipelined interaction chip includes a scalar processor, a vector coprocessor, and a cross-queue module. The scalar processor has a scalar pipeline, and the vector coprocessor has a vector pipeline. The scalar processor decodes the fetched vector instructions and divides them into two data streams. One data stream directly sends the vector instructions to the vector coprocessor for vector pipeline execution. The other data stream sends the vector instruction ID and the decoded scalar register number to the cross-queue module. The cross-queue module allocates an entry for each vector instruction requiring scalar operands, thereby achieving decoupled interaction between the scalar pipeline and the vector pipeline, significantly improving the execution efficiency of scalar threads and the overall system instruction throughput.

The application provides a method and device for processing an image. The method comprises: obtaining image data; calculating filter weight coefficients of the image data by using a first processing unit and a second processing unit, wherein the filter weight coefficients of the image data comprise filter weight coefficients corresponding to first data elements and filter weight coefficients corresponding to second data elements, the filter weight coefficients corresponding to the first data elements and the filter weight coefficients corresponding to the second data elements comprise a first part with the same value and a second part with different values, the first part is calculated by the first processing unit, and the second part is calculated by the second processing unit, wherein the first processing unit is a vector processor, and the second processing unit is a vector processor or a scalar processor. The application can use the first processing unit to perform the calculation of the data with the same value in the filter weight coefficients, so that the part that needs to be repeatedly calculated only needs to be calculated once, the amount of calculation is reduced, and the operation efficiency is improved.

The application provides a method for instruction fusion using a superscalar processor and related equipment. A decoding unit obtains first instruction control signals of multiple instructions to be executed, and sends the first instruction control signals to a fusion decoding unit. The fusion decoding unit determines, for any one of at least one instruction pair, that a first instruction in the any one instruction pair is an I-type instruction, a second instruction in the any one instruction pair is an I-type instruction or an R-type instruction, and judges whether there is an instruction pair matching the any one instruction pair in a plurality of preset instruction pairs. If there is, instruction fusion is performed under the condition that a source operand of the first instruction is equal to a destination operand of the first instruction and the destination operand of the first instruction is equal to at least one source operand of the second instruction, to obtain a fusion instruction. A fusion instruction execution unit executes the fusion instruction according to an operation logic of the fusion instruction.

The present disclosure relates to methods and apparatus for graphics processing. The techniques facilitate improved unbound state processing at a graphics processor. A shader program comprising a preamble and a main instruction portion may be received at the graphics processor. A scalar processor dedicated to processing the preamble may execute instructions in the preamble to implement an unbound mechanism for loading constant data associated with the shader program. The main instruction portion and the constant data may be distributed to stream processors for execution of the shader program.