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Data processor for improving storage instruction execution efficiency

A technology for data processors and stored instructions, which is applied in the direction of concurrent instruction execution, machine execution device, program startup/switching, etc. It can solve the problems of low execution efficiency of stored instructions, long pipeline pauses, and limited processor performance to improve performance. , reduce pipeline pauses, and speed up execution efficiency

Inactive Publication Date: 2012-06-13
C SKY MICROSYST CO LTD
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  • Description
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AI Technical Summary

Problems solved by technology

[0004] In order to overcome the shortcomings of the existing data processors in solving the true correlation of data read after write in the storage data correlation, the pipeline pause is longer, the execution efficiency of storage instructions is low, and the performance of the processor is limited, the present invention proposes a A data processor that effectively reduces the pipeline stalls caused by the true correlation of data read and write, speeds up the execution efficiency of storage instructions, and improves the performance of the processor.

Method used

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  • Data processor for improving storage instruction execution efficiency
  • Data processor for improving storage instruction execution efficiency
  • Data processor for improving storage instruction execution efficiency

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Embodiment Construction

[0025] The present invention will be further described below in conjunction with the accompanying drawings.

[0026] refer to Figure 1 ~ Figure 2 , a data processor for accelerating the execution efficiency of storage instructions, the data processor comprising:

[0027] register file;

[0028] The instruction decoding unit decodes the type information and operand information of the instruction according to the instruction opcode, accesses the register file, and detects the correlation of the instruction operand;

[0029] The instruction scheduling unit receives all instructions from the instruction decoding unit, monitors the exit data of each execution unit, and completes the feed-forward of the storage instruction address operand and the feed-forward of all operands of other instructions according to the correlation information of the instruction operands. The instruction completed by operand feedforward is sent to the corresponding instruction execution unit;

[0030] ...

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Abstract

A data processor for improving the storage instruction execution efficiency comprises a register file, an instruction decoding unit, an instruction scheduling unit, a storage instruction queue and instruction execution units, wherein the instruction scheduling unit is used for completing feedforward of the address operand of a stored instruction and feedforward of all operands of other instructions according to related information of instruction operands, and transmitting the instructions completed by operand feedforward to the corresponding instruction execution unit; the storage instruction queue is used for receiving storage instructions from the instruction decoding unit, storing write-back data and related information of the stored instruction, monitoring outlet data of all the execution units and completing feedforward of the write-back data of the stored instruction according to the related information of the stored instruction data operand; and the instruction execution units are used for receiving instructions transmitted by the instruction scheduling unit and are divided into different execution units according to the instruction types. The data processor provided by the invention effectively reduces breakdown of assembly lines due to genuine correlation of data write after read, improves the execution efficiency of storage instructions and has promoted performance.

Description

technical field [0001] The present invention relates to a data processor. Background technique [0002] In the pipeline technology of processors, pipeline conflicts mainly include: structure conflicts, data conflicts and control conflicts. With the continuous deepening of the pipeline, these types of conflicts cause the pipeline to stall, seriously affecting the performance of the processor. Structural conflicts can be resolved by increasing resources; for control conflicts, various technologies such as branch predictors and branch target buffers are used to reduce the performance loss caused by control conflicts; for data conflicts, especially read-after-write The real correlation, the hardware usually adopts a feed-forward mechanism to alleviate the performance loss caused by it. [0003] For storage instructions, its operands are divided into address operands and data operands, and its operands may come from the execution results of various instructions, including arith...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38G06F9/48
Inventor 葛海通项晓燕杨军陈志坚
Owner C SKY MICROSYST CO LTD
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