51 results about "Memory model" patented technology

The invention discloses a Direct3D memory model compatible method based on adaptive placeholder resources, which comprises the following steps: establishing resource metadata, accessing a scene library, checking an instruction template and double sandboxes when a DXVK is started, describing related resources by the DXVK through the metadata after a D3D application is started, completing resource mapping and metadata dynamic updating, and allocating the resources to the corresponding sandboxes; the DXVK compiles an application shader code, identifies a resource access instruction, matches an access scene and a check template by combining a pipeline stage and binding slot query metadata, instantiates the check instruction and adds the check instruction to the front of a target instruction; according to the unbound resources, adaptive generation of corresponding occupied resources is carried out, the authority and the state are configured, the unbound resources are bound to a Vulkan descriptor set to replace VKNULLHANDLE, and adaptation of the shader interface and the pipeline state parameters is completed to create PSO (Particle Swarm Optimization); and intercepting an application rendering instruction analysis parameter to construct a command buffer area, submitting the command buffer area to a Vulkan queue to trigger a GPU (Graphic Processing Unit) to execute rendering, and finally completing complete conversion and adaptation from the D3D rendering logic to the Vulkan.

The invention discloses a big language model dialogue system for Token-level resident memory and a use method. The big language model dialogue system comprises an inference engine module, a big language model module, an independent memory model module and an external storage module, relates to the technical field of big language model memory enhancement, after a current dialogue Token sequence is received, whether historical dialogue information is needed or not is judged through a big language model module, and if yes, the historical dialogue information is called from an external storage module through an independent memory model module, so that information displayed by finally responding to the Token sequence is more complete, and user experience is improved. The problems that a model cannot completely retain and utilize long-distance historical information, so that questions cannot be answered and information is forgotten are solved; an external storage module is arranged, and model parameters of an independent memory model module and Token-level data of all historical conversations are resided through a memory mapping technology; and zero occupation of the GPU video memory is realized.

The application relates to the chip technical field, in particular to a chip verification system based on a database, which comprises a first file database, a second file database, a verification IP and a first memory model arranged in the verification IP; the first file database is used for storing verification data; the verification IP reads the verification data in the first file database and stores the verification data into the first memory model through a structured query interface; the verification IP comprises a first data conversion interface and a second data conversion interface; the verification IP is also used for acquiring the verification data from the first memory model through the first data conversion interface, processing the verification data, generating result data, and storing the result data into the first memory model through the second data conversion interface; and the verification IP is also used for storing the result data in the first memory model into the second file database through the structured query interface. The application improves the chip verification efficiency.

The invention relates to a multi-core processor memory consistency verification method and device, the method is executed by a memory model in a processor co-simulation verification architecture, and the method comprises the following steps: monitoring a storage instruction of each processor core in an RTL, and maintaining a storage queue for each processor core based on the storage instruction; in response to a data request initiated when the ISS executes the loading instruction, speculating a set of compliance values possibly read by the loading instruction based on the storage queue and the visible relation of the storage instructions between the maintained different processor cores; comparing the actual read data of the loading instruction obtained from the RTL with the set of compliance values; and if the actually read data is in the set of compliance values, determining that the memory consistency verification of the multi-core processor is compliant. Therefore, an RISC-V multi-core processor memory consistency verification scheme which can be integrated in a front simulation environment, supports real-time accurate verification and has high coverage is provided.

The invention discloses a real-time compiling interpreter system capable of running on an MCU (Microprogrammed Control Unit), an FPGA (Field Programmable Gate Array), a GPU (Graphics Processing Unit) or a universal CPU (Central Processing Unit), and belongs to the technical field of embedded systems and computer compiling. According to the system, hardware decoupling is achieved through a modular architecture, and C / C + +, Python and LLVM intermediate codes are supported to be converted into unified intermediate byte codes; a byte code interpreter and an instant compiling module are integrated, both quick starting and efficient execution are considered, and starting can be completed within 1 millisecond; an event driving and periodic scheduling mechanism is provided, and the real-time response requirement is met; a segmented memory model and a security policy are adopted, low-power-consumption edge equipment is adapted, and domestic instruction sets such as RISC-V and LoongArch are compatible. The system solves the problems that a traditional embedded system is poor in flexibility, difficult in cross-platform, insufficient in real-time performance and the like, can achieve unified execution of heterogeneous platform codes, is suitable for the fields of industrial control, Internet of Things edge AI and the like, and has remarkable technical progress and industrial value.

Embodiments of the present application disclose a kind of group adaptive integrated control method, device, electronic equipment and storage medium, involve embodied intelligent technical field, wherein, the method includes: according to target scene characteristic, utilize physical modeling and domain randomization technology to generate diversified environment task set, and pre-processing is carried out to ensure data quality, train reinforcement learning coach based on these tasks, combine decoupling and backtracking policy distillation technology to synthesize training sequence, enhance the generalization and adaptive ability of model, adopt long-time memory model structure design base model, integrate multi-agent observation module to capture time sequence and spatial correlation, dynamic noise injection and asynchronous optimization are carried out in training process, the trained field base model is deployed to target scene, form collaborative network, and set fault-tolerant mechanism to deal with agent offline and other sudden situations, continuously collect actual data to optimize model parameters.The present application effectively solves the problems of high customization, weak migration and high maintenance cost in the prior art.

The invention provides a memory simulation method and device, equipment, a storage medium and a program product. The memory simulation method comprises the following steps: compiling a memory model and a plurality of simulation interfaces of the memory model in the hardware simulation platform; the method comprises the steps of determining a plurality of simulation interface combinations, establishing mapping between the simulation interface combinations and simulation storage positions, and determining a plurality of programming positions of first data according to the first data to be programmed; determining a first sequence based on the programming position and the simulation interface combination mapped by the programming position; second data are written into the first positions in the multiple first positions one by one, and the set data written into the multiple first positions form first data programmed in the memory model. According to the method and the device, the process of writing data into the first position mapped by the simulation interface combination one by one can be displayed.

A compiler comprises a low-level memory management (LLMM) module that locates computed entities within source code. Each computed entity is analyzed, and resource costs associated with each computed entity are calculated. A memory model is selected for each computed entity, based on memory use, computational complexity, and other factors. User-defined memory model assignment is supported. The compiler auto-generates instructions for allocating memory for, computing, and deallocating memory for each computed entity. The instructions generated for each computed entity will vary based on its assigned memory model. A variety of embodiments are disclosed for auto-generating these instructions during compile time at differing phases of compilation. In all of those, with the resultant executable code, memory is allocated and freed at runtime automatically and accurately without the intervention in source code by a programmer.

This disclosure relates to a method and computer device for controlling underwater vehicles. It pertains to the field of underwater navigation and addresses the safety and mission execution difficulties caused by underwater vehicles being detected. The method includes: constructing an underwater environment simulation model; acquiring passive detection data during the simulated operation of the underwater vehicle based on the underwater environment simulation model; training an explicit risk memory model based on the passive detection data from the underwater vehicle's operational history; generating a multi-dimensional observation vector indicating the current probability of detection based on the risk memory features output by the explicit risk memory model and instantaneous operational data; and performing memory fusion based on the multi-dimensional observation vector and the hidden state of the previous time step of the gated loop unit to output a normalized angular velocity control command to control the underwater vehicle. The technical solution provided by this disclosure is applicable to complex underwater navigation scenarios, achieving efficient and accurate autonomous decision-making for detection avoidance.

The invention discloses a tree shrew visual association memory evaluation method based on an 8-shaped maze, and the method comprises the following steps: preparing before an experiment, including animal screening and environment setting; performing rule training, enabling the tree shrew to learn to associate the colors of the prompt board in the selection area with channel arm selection, including familiarity environment, door pushing training, shaping training and free selection test, and opening and closing the corresponding channel arm according to the colors of the prompt board in the shaping training; formal testing is carried out, shaping training is carried out twice every day, then free selection testing is carried out according to a 1-3 random mode, and the error rate is recorded; and performing modeling evaluation, namely evaluating whether a stable memory model is established or not based on an error rate of a formal test, and entering the formal test when the prompt board continuously appears for 1-3 times according to the same color and the conversion rate is 50-65% and the error rate is lower than 20% in the free selection test. According to the tree shrew visual association memory evaluation method provided by the invention, scientificity and statistical efficacy of behavior testing are ensured, and learning deviation caused by a fixed mode in a traditional method is overcome.

The invention relates to the technical field of computers, in particular to a visual programming method and device and a readable storage medium. The method comprises the following steps: constructing a node graph of a double-layer connection system adopting separation of a data flow and a control flow to represent an algorithm logic; generating an abstract syntax tree which is semantically equivalent to the node graph, and establishing a bidirectional mapping relationship between the abstract syntax tree and the node graph; when the algorithm logic is executed, real-time memory state data including a call stack and a heap memory are captured through a tracking probe; and according to the data, dynamically generating a memory model visual view containing call stack and heap memory tracking. According to the method, the problems of unclear logic expression and opaque execution process in the prior art are solved, and the development and debugging efficiency is remarkably improved by intuitively presenting the dynamic execution process of the algorithm.

Embodiments of this disclosure relate to methods, apparatus, electronic devices, and products for determining memory usage. The method includes acquiring a set of memory usage information by initiating a set of parallel training sessions related to a target model, wherein each parallel training session in the set of parallel training sessions is configured using predetermined parallel parameters. The method also includes determining memory modeling parameters for the target model based on the set of memory usage information. Furthermore, the method includes determining multiple memory usage peaks of the target model in different parallel training sessions corresponding to different parallel parameters based on the memory modeling parameters. Thus, this method can model the memory usage of a target model using memory usage information from a set of parallel training sessions without knowing the specific network structure, thereby determining the maximum memory usage of the target model under different parallel configurations. This provides an important basis for automatic tuning of parallel training and avoids training interruptions or failures due to insufficient memory.

The invention discloses a body navigation memory enhancement method and system based on spiking neurons. The method comprises the following steps: (1) constructing random parallel spiking neurons; (2) using a gating linear RNN as a basic structure of a cyclic memory model, and meanwhile, using a random parallel spiking neuron as a discrete gating function of the cyclic memory model; (3) adding the circulating memory model into the body-equipped intelligent agent, and carrying out reinforcement learning based on a long-term memory navigation task; in the actual navigation process of the body agent, the cyclic memory model maximizes the time significance signal-to-noise ratio through a discrete gating function, so that the capacity of filtering information irrelevant to tasks of the body agent is enhanced. According to the invention, the success rate of long-term memory navigation tasks can be improved.

The invention provides a training method, a resistance state adjusting method and an image processing method and device. The training method comprises the following steps: acquiring a simulation data set generated by a micro-magnetic simulation technology and an experiment data set obtained based on an experiment; a mixed data set is constructed according to the simulation data set and the experiment data set, the mixed data set comprises a plurality of sample pairs, and each sample pair comprises at least two mixed training samples; for each sample pair, processing the sample pair by using an initial memory model to obtain a first prediction performance parameter corresponding to each mixed training sample, and calculating a first residual error of at least two first prediction performance parameters; under the condition that the first residual error meets a residual error threshold value, testing the to-be-tested sample pair through an experiment so as to update the initial sample label, and obtaining a new sample label; and under the condition that a training set iteration termination condition is satisfied, training the initial memory model by using the updated mixed data set to obtain a magnetoresistive memory model.

1. Name of the product in this design: Memory Model (3D Stacked NAND). 2. Purpose of this design: For use in 3D stacked NAND memory models. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

The invention discloses a subway robot interaction system based on multi-modal fusion, and the system comprises an information collection module which is used for collecting interaction object information, and constructing an interaction feature data set; the memory modeling module is used for constructing an interactive memory unit and attenuation control parameters; the confidence fusion module is used for constructing an interaction style vector and updating the interaction confidence; the semantic matching module is used for inputting the semantic candidate path set and the semantic state diagram into the improved GMN model to generate a path score list; and the response decision module is used for calculating a semantic confidence value of the preferred semantic path, executing an interactive output strategy in combination with the interactive semantic response scheme, and outputting semantic clarification information or confirmation instruction information or interactive response content. According to the method, the response accuracy and robustness of the subway robot in the man-machine interaction process are improved, and the method has the advantages of being high in response speed, high in fault tolerance and high in semantic matching precision.

The invention relates to a memory model configuration method and device, computer equipment and a storage medium, the method is applied to core grain verification, a core grain comprises a plurality of chip sets, and each chip set has a corresponding verification environment; the method comprises the following steps: acquiring the total access times of each chip set for accessing a memory model in a chip grain verification process; and determining the verification environment corresponding to the chipset with the maximum total access frequency as a target environment for configuring the memory model. The memory model is configured into the verification environment corresponding to the chipset with the maximum total access frequency, so that the cross-thread request of each chipset in the core grain verification process can be reduced, and the simulation efficiency is improved.

The application relates to the technical field of processors, in particular to a verification method and system of an LRSC instruction in an RISCV instruction set, which comprises a single-core signal collector, a multi-core signal collector, an LR instruction queue, an SC instruction queue, a single-core controller, a multi-core controller, a local monitor, a global monitor, a memory model and a comparator; the application supports the LRSC instruction; if the address attribute of the LRSC instruction is cacheable, the related operation of lock grabbing is maintained in the local monitor; each core has an independent local monitor, and the cores perform lock grabbing operation through data consistency operation; if the address attribute of the LRSC instruction is non-cacheable, the related operation of lock grabbing is maintained in the global monitor; the global monitor is only one, monitors the LRSC access of all cores, and returns the access result. Through the verification method, whether the lock grabbing operation of the DUT is accurate can be effectively and accurately judged, and the verification method is suitable for processor verification of all RISCV architectures.

The invention relates to a memory model switching method and device, a medium and a program product. The memory model switching method comprises the following steps: in response to a memory access request from a processor core, obtaining a leaf-level page table entry corresponding to a target virtual address based on the requested target virtual address; determining a memory model applied to a target memory page corresponding to the leaf-level page table item according to the value of the PBMT field in the leaf-level page table item; when it is determined that the memory model applied to the target memory page is a TSO memory model, scheduling the memory access request to a TSO memory access queue; when it is determined that the memory model applied to the target memory page is a WMO memory model, the memory access request is scheduled to a WMO memory access queue, and the WMO memory access queue and the TSO memory access queue are independent of each other.

The application provides a timing calibration method and system for a serial flash memory device, comprising: a central processing unit controlling a flash memory controller to read first data from the serial flash memory device at a current operating frequency of the serial flash memory device according to a first sampling parameter saved by the central processing unit; then controlling the flash memory controller to adjust the current operating frequency of the serial flash memory device to a desired operating frequency input from outside; further controlling the flash memory controller to read second data from the serial flash memory device according to a second sampling parameter, and when the second data is inconsistent with the first data, continuously adjusting the second sampling parameter according to the desired operating frequency to delay the sampling time of the flash memory controller until the second data is consistent with the first data, and then saving the corresponding second sampling parameter. The beneficial effect is that the flash memory controller can support a higher upper limit of the clock frequency of the serial flash memory device, a wider clock frequency range, and more memory models.

The invention discloses a network security automatic guard robot system based on AI driving, and the system comprises a behavior collection module which is used for collecting multi-source behavior data in a network operation environment, and generating a gray region behavior set; the abrupt change sensing module is used for introducing an abnormal abrupt change sensing structure into the improved RWKV model and generating an abrupt change response vector; the memory modeling module is used for introducing a time sequence memory structure and generating risk state representation; the channel judgment module is used for constructing a behavior risk classification result and outputting a channel selection result; the strategy generation module is used for generating a treatment strategy instruction sequence and constructing a treatment record and a behavior response vector; and the feedback injection module is used for introducing a strategy feedback injection structure, updating the risk state representation and completing a network security guarding response process. According to the invention, continuous, intelligent and safe automatic guarding oriented to a complex network environment can be realized.

This application relates to the field of computer technology, providing a non-intrusive Linux memory barrier modification method and system. The method is applied to scenarios where an information system is migrated from a strong memory model chip architecture to a weak memory model chip architecture. Specifically, it includes: in the newly added adaptation layer, determining the target system calls invoked by the component layer, and constructing a rewritten function with the same name for each target system call. The rewritten function sequentially includes a first memory barrier instruction, an instruction to call the original target system call, and a second memory barrier instruction; compiling the rewritten function into a dynamic link library; and when the business process starts, preferentially loading the custom dynamic library by preloading environment variables to hijack system calls, so that the operating system's dynamic linker redirects the component layer's calls to the target system calls to the rewritten function. This application achieves complete decoupling of business logic and adaptation logic by implanting a memory barrier at the system call layer without modifying the business layer and component layer code.

The present application relates to the technical field of processor, and particularly relates to a multi-core memory access instruction verification system and method, which comprises a DUT monitor, an access instruction queue, a storage instruction queue, a memory access instruction controller, a storage buffer, a memory model, an access data comparator, a storage data comparator, an atomic instruction comparator and a secondary cache comparator. The present application supports multi-core multi-cluster memory access instruction verification, and the number of cores and clusters can be configured, which is parameterized and scalable. The present application supports real-time comparison of the correctness of memory access instruction execution of each core in a multi-core system, including comparison of the correctness of access data when the access instruction is submitted, and comparison of the correctness of write data when the storage instruction updates the cache. The present application supports verification of atomic operation instructions in a multi-core system, and supports verification of secondary cache key interfaces in a multi-cluster system, which has a strong market application prospect.

The invention discloses an input and output management method and system for a reserved memory, equipment and a medium, and the method comprises the steps: specifying a physical address range of a reserved memory region; mapping the physical address range to a linear mapping space by using a page table, and establishing a virtual address range accessible to a kernel mode; registering the physical address range into a sparse memory model, and establishing a mapping relationship between the page structure body and the page frame number; configuring the page structure body into the reserved memory area management area, and managing the page structure body based on the mapping relation; and executing input and output operation of the reserved memory area based on the mapping relation. According to the method, seamless integration of the reserved memory area in the kernel memory management framework is realized, the convenience and stability of kernel mode access are improved, the efficiency of user mode data transmission is optimized, the memory copying and processing overhead introduced by a traditional cache mechanism is reduced, and the user experience is improved. And the performance of directly accessing the memory of the hardware equipment in the embedded system and the resource utilization rate are improved.

The invention relates to the technical field of education, and discloses a multi-sensory linkage educational digital oil painting system which comprises a knowledge visualization sketch layer, an intelligent auxiliary terminal layer and a multi-sensory linkage assembly layer. The knowledge visualization sketch layer is used for presenting a digital oil painting sketch fused with educational information, and a color theory mark, a stroke skill prompt and a famous painting background knowledge pop-up window are embedded in the sketch; and the intelligent auxiliary terminal layer comprises a touch operation module, a data processing module and an educational resource library. In the invention, the knowledge visualization sketch layer is embedded with education information such as a color theory and stroke skills through dynamic labeling, audio explanation, tactile feedback and scene smell of the multi-sensory linkage component layer are combined, a hippocampus memory area is activated by relying on a right brain image memory advantage and an alpha wave regulation and control technology, and multi-sensory synchronous input is combined, so that a hippocampus memory area is activated. A knowledge conversion path conforming to the Ebbinghaus multi-channel memory model is constructed, and the memory retention rate is remarkably improved.

The embodiment of the application belongs to the technical field of resource scheduling optimization of artificial intelligence, and relates to a scheduling method and device applied to a directed acyclic graph, computer equipment and a storage medium. The method considers a DAG of a simple memory model. In each iteration process, the next node is selected based on the scheduling scheme of the current state, but the states required for participating in the next iteration are limited to the optimal limited number of states obtained in the current iteration. The application only retains the k states with the most potential to enter the next iteration, which greatly reduces the search space and reduces the time complexity of the algorithm. In the iteration process, the algorithm continuously selects the node with the minimum memory peak value influence to join the execution sequence, ensuring that the scheduling path close to the optimal solution can still be explored under limited computing resources. This strategy not only improves the execution efficiency of the algorithm, but also guarantees the quality of the scheduling scheme, and realizes the optimization balance of memory use and computing time.

This application discloses an adaptive text regeneration method, system, electronic device, and storage medium that combines dynamic user profiles and standard language proficiency levels. The method receives source text and a target language proficiency level identifier; collects user reading interaction data in real time; combines the target level with a memory model based on the forgetting curve to construct a dynamic user profile containing known vocabulary and vocabulary to be reviewed; integrates the source text, target level, and profile generation prompts; inputs the data into a large language model fine-tuned with target domain corpus; generates regenerated text adapted to the target level and embedding vocabulary to be reviewed; and outputs the regenerated text after dual verification of semantic fidelity and teaching effectiveness. This application solves the problems of insufficient personalization, low memory efficiency, and semantic distortion in existing technologies by deeply integrating personalized dynamic profiles, scientific memory principles, and the capabilities of a large language model, achieving high-fidelity, high-efficiency, and personalized adaptive text regeneration.

The present application relates to the technical field of electric power engineering, and in particular to a power load prediction method fusing attention enhancement and dynamic fine-tuning mechanism, which firstly constructs an attention-enhanced Legendre memory model and improves the standardization layer thereof, enhances the processing capability of the model for high-order nonlinear power load data, simultaneously introduces a frequency enhancement channel attention mechanism, adaptively weights the features in the frequency domain dimension, effectively retains valuable information in high-frequency components, and suppresses noise interference; secondly, constructs a lightweight dynamic fine-tuning framework, finely corrects the prediction residual of the main model in a gradient boosting iteration manner, and significantly reduces the prediction deviation of the load trend mutation area; finally, comprehensively uses the trained attention-enhanced Legendre memory model and the fine-tuning framework to perform power load prediction. It has been verified that the present application can effectively improve the accuracy of short-period power load prediction and shows superior performance on both public data sets and real power data.

Disclosed is a memory model building method and a memory circuit simulation method. The memory model building method includes the following steps. A test condition is applied to unselected memory cells in a memory string. A threshold voltage of a selected memory cell in the memory string is programmed to a first threshold voltage value. Tests are performed on the memory cell string by setting the test condition as test values so as to obtain first impedance values corresponding to the test values. The test values and the corresponding first impedance values are analyzed so as to obtain a linear model having a first slope value and a first intercept value. A relationship between the test values and the corresponding first impedance values at the first threshold voltage value satisfies the linear model.