109 results about "Memory model" patented technology

The invention provides a security data penetration test method. The method comprises the steps of pre-establishing a multi-thread application program race condition vulnerability feature library, performing static analysis on source codes of a target application program, identifying potential race condition vulnerability points, and obtaining a preliminary vulnerability candidate set; for monitored suspected race condition events, abstracting event context information into constraint conditions, exploring an input combination of suspected static conditions by using a constraint solver, and determining a minimum input set of stable triggering race conditions; aiming at memory models and synchronous primitives of different programming languages, obtaining a race condition inverse mode, and extracting universal utilization primitives covering various race condition vulnerabilities; in the penetration test process, static analysis, dynamic monitoring and symbolic execution are applied to mine race condition vulnerabilities of a target application system, the availability of the vulnerabilities is verified, and evaluation of system security is assisted to be completed.

The invention discloses a student sentiment analysis method and system based on a multi-modal dynamic memory large model, and belongs to the field of multi-modal sentiment analysis. The method comprises the following steps: firstly, acquiring facial expression images and corresponding real emotional state category labels when different students watch an online education course to form a training data set, training a multi-modal dynamic memory large model based on the data set, and in the training process, performing prompt fine tuning on an image encoder and a text encoder so as to obtain a multi-modal dynamic memory large model; visual aggregation representation generated in the historical training process is stored through a dynamic feature space, and model parameters are optimized through cross entropy loss; and finally, inputting a facial expression image to be classified into the trained multi-modal dynamic memory large model, and outputting an emotional state category prediction result of the facial expression image. The method can be effectively applied to the field of education, and is beneficial for teachers to know the emotional state of students, thereby improving the participation degree and learning effect of the students.

The invention discloses a Direct3D memory model compatible method based on adaptive placeholder resources, which comprises the following steps: establishing resource metadata, accessing a scene library, checking an instruction template and double sandboxes when a DXVK is started, describing related resources by the DXVK through the metadata after a D3D application is started, completing resource mapping and metadata dynamic updating, and allocating the resources to the corresponding sandboxes; the DXVK compiles an application shader code, identifies a resource access instruction, matches an access scene and a check template by combining a pipeline stage and binding slot query metadata, instantiates the check instruction and adds the check instruction to the front of a target instruction; according to the unbound resources, adaptive generation of corresponding occupied resources is carried out, the authority and the state are configured, the unbound resources are bound to a Vulkan descriptor set to replace VKNULLHANDLE, and adaptation of the shader interface and the pipeline state parameters is completed to create PSO (Particle Swarm Optimization); and intercepting an application rendering instruction analysis parameter to construct a command buffer area, submitting the command buffer area to a Vulkan queue to trigger a GPU (Graphic Processing Unit) to execute rendering, and finally completing complete conversion and adaptation from the D3D rendering logic to the Vulkan.

The invention discloses a real-time simulation performance evaluation method based on an ARMv8 architecture multi-core processor, and particularly relates to the technical field of multi-core performance evaluation. Comprising the following steps that a concurrent monitoring module is arranged, and an access instruction sequence and memory barrier instruction information of a processing core are collected; analyzing an address cross relation and time sequence dependence between the access instructions, and generating an instruction rearrangement risk access group; concurrency consistency analysis is carried out on the risk access group, race conditions are identified, and a synchronization mode and memory barrier instruction distribution are recorded; high-intensity concurrent operation is injected into the simulation environment, read-write operation of the shared variables is continuously tracked, and an instruction execution sequence is analyzed; the matching degree under different simulation load conditions is counted, a real-time simulation performance evaluation index for the weak memory model is generated, and the potential consistency problem caused by instruction rearrangement can be accurately recognized.

The invention discloses a large-model context control system and method based on hierarchical memory and an association graph, and the method comprises the steps: constructing a tree graph mixed memory structure and a logic hierarchical memory model for a context control unit between a user and an LLM, and carrying out the self-adaptive processing of a super-long context through a self-adaptive processing engine, a single-theme persistent dialogue control mechanism, and the like. According to the method, the problem that an LLM context window is limited (including introduction of a mechanism similar to an Agent) is solved, just like an operating system helps developers / users to solve the problems that hardware standards hidden behind are not uniform, and complex resource control is caused, a reliable LLM memory (context) control service with multiple details hidden is provided for upper developers, and the method has the advantages of being high in practicability and easy to popularize and use. The final objective of the method is to approximately relieve the limitation of an LLM context window through a set of self-consistent system mechanism, so that a developer does not need to pay too much attention to the details of a bottom layer, and more energy can be focused on the implementation of an application function.

The invention provides a potential risk event intelligent analysis method based on comparative learning, and belongs to the technical field of risk event intelligent analysis. A memory unit is regarded as a prototype of a normal video mode, and on the basis of memorizing video data features, contrast learning is introduced into the memory unit for training. A data enhancement strategy is adopted: different video sections in the same video belong to positive samples; data enhancement is performed on a video, and spatio-temporal information of the video, such as disorder, random rotation of video frames, continuous repetition of single video frames and the like, is destroyed as a negative sample sequence. Reconstruction errors are used as a standard for judging the drowning event, the similarity between an input video stream and a memory unit is used as an auxiliary standard for judging the drowning event, and the specific mixed decision-making method is completed in a weighting mode. According to the method, the general problem of network reconstruction and the problem of a memory model in anomaly detection are solved.

The invention discloses a multi-node MPI set communication performance modeling method and system, and the method comprises the steps: firstly determining model parameters needing to be measured according to the information of a multi-core processor in a node and the hierarchical information of a platform network; then measuring intra-node communication parameters and inter-node communication parameters on different network levels on the platform; analyzing a set communication source code and simulating a communication algorithm behavior to obtain all communication characteristics of each round of communication of the algorithm; and finally, corresponding parameters are selected in combination with communication characteristics, and the communication time of each round is represented by a mathematical formula of the corresponding parameters. Compared with an existing model, supercomputing network hierarchical structure information and a point-to-point communication primitive type used by a communication algorithm bottom layer are introduced, and the application range of the model is expanded from a single-node shared memory model to a hybrid model of a multi-node shared memory and an interconnection network; the model can more accurately predict the communication time of the multi-node set communication operation.

The invention discloses a UVM automatic verification method for loading an external memory function on a chip, and belongs to the technical field of integrated circuit design and verification. According to the method, test excitation is divided into configuration information filled by a user and control information automatically generated through a formula to generate a configuration file, the configuration file is read by means of a memory model, data is configured to a specified register after a chip is powered on, and cross-channel data verification is achieved through an analysis module, a driving module and a data checking module. And randomly selecting one node from broadcast nodes for a register configured by the broadcast, and reading back data for comparison. According to the method, the limitation of single-link verification is broken through, a closed loop of configuration generation-simulation execution-cross-channel verification is formed, end-to-end automatic verification is realized, verification efficiency and reliability are improved, manual configuration errors are reduced, abnormity is accurately positioned in real time, and verification completeness and efficiency are balanced.

The invention discloses a big language model dialogue system for Token-level resident memory and a use method. The big language model dialogue system comprises an inference engine module, a big language model module, an independent memory model module and an external storage module, relates to the technical field of big language model memory enhancement, after a current dialogue Token sequence is received, whether historical dialogue information is needed or not is judged through a big language model module, and if yes, the historical dialogue information is called from an external storage module through an independent memory model module, so that information displayed by finally responding to the Token sequence is more complete, and user experience is improved. The problems that a model cannot completely retain and utilize long-distance historical information, so that questions cannot be answered and information is forgotten are solved; an external storage module is arranged, and model parameters of an independent memory model module and Token-level data of all historical conversations are resided through a memory mapping technology; and zero occupation of the GPU video memory is realized.

The invention discloses a performance optimization method, device and equipment for multimode query of a data vault and a medium. The method comprises the following steps: low-density screening of levels: analyzing data storage, and constructing a low-density index according to data features; the data statistics level is used for calculating and counting data source information; block scanning level: evaluating the data size, configuring block scanning parameters according to the data size, and determining the degree of parallelism of parallel scanning; a condition operator push-down level: identifying a push-down query condition, and pushing down the push-down query condition to the data source scanning operator; a cost model calculation level: planning to generate data sorting for a sorting operator through cost model calculation; a memory model calculation level: allocating a memory model according to the size of the memory; according to the cost of each layer, evaluating the performance improvement proportion or multiple brought by optimization of each layer layer by layer; and planning a data processing mode according to a layer-by-layer evaluation result. According to the method, the multi-layer optimization model is adopted, so that the performance of multi-mode query is improved.

In various examples, a memory model may support multicasting where a single request for a memory access operation may be propagated to multiple physical addresses associated with multiple processing elements (e.g., corresponding to respective local memory). Thus, the request may cause data to be read from and / or written to memory for each of the processing elements. In some examples, a memory model exposes multicasting to processes. This may include providing for separate multicast and unicast instructions or shared instructions with one or more parameters (e.g., indicating a virtual address) being used to indicate multicasting or unicasting. Additionally or alternatively, whether a request(s) is processed using multicasting or unicasting may be opaque to a process and / or application or may otherwise be determined by the system. One or more constraints may be imposed on processing requests using multicasting to maintain a coherent memory interface.

The invention provides an object-oriented hierarchical memory network device. The object-oriented hierarchical memory network device comprises a low-level object sensing module, a space-time memory construction module and a long-term space-time memory modeling module, the low-level object sensing module is used for extracting object features of an input video through a segmentation basic model; the space-time memory construction module is used for extracting object interaction and scene information by analyzing an inter-frame space and time relationship so as to splice object features and input original video frames to generate a space representation of target perception; and the long-term space-time memory modeling module is used for storing historical information through a memory bank, capturing a global dependency relationship of a video level, and splicing a plurality of adjacent video frames output by the space-time memory construction module on a channel dimension to form local multi-frame space-time representation. And the purpose of enhancing the capturing capability of the model on fine-grained space-time dynamic in the long video is achieved.

Embodiments of the present disclosure relate to computer systems, methods, and hardware storage devices for recording replayable traces. Recording a replayable trace of the execution of a multithreaded process includes identifying a trace memory model that defines one or more sortable events that are to be ordered across multiple threads of the multithreaded process. Multiple threads are executed simultaneously across one or more processing units of one or more processors. During the execution of the multiple threads, a separate replayable trace is recorded independently for each thread. The recording includes, for each thread: recording an initial state for the thread; recording at least one memory read performed by at least one processor instruction, where the at least one processor instruction executed by the thread takes the memory as an input; and recording at least one sortable event executed by the thread with a monotonically increasing number that orders the event among other sortable events across the multiple threads.

The application relates to the chip technical field, in particular to a chip verification system based on a database, which comprises a first file database, a second file database, a verification IP and a first memory model arranged in the verification IP; the first file database is used for storing verification data; the verification IP reads the verification data in the first file database and stores the verification data into the first memory model through a structured query interface; the verification IP comprises a first data conversion interface and a second data conversion interface; the verification IP is also used for acquiring the verification data from the first memory model through the first data conversion interface, processing the verification data, generating result data, and storing the result data into the first memory model through the second data conversion interface; and the verification IP is also used for storing the result data in the first memory model into the second file database through the structured query interface. The application improves the chip verification efficiency.

The invention relates to a multi-core processor memory consistency verification method and device, the method is executed by a memory model in a processor co-simulation verification architecture, and the method comprises the following steps: monitoring a storage instruction of each processor core in an RTL, and maintaining a storage queue for each processor core based on the storage instruction; in response to a data request initiated when the ISS executes the loading instruction, speculating a set of compliance values possibly read by the loading instruction based on the storage queue and the visible relation of the storage instructions between the maintained different processor cores; comparing the actual read data of the loading instruction obtained from the RTL with the set of compliance values; and if the actually read data is in the set of compliance values, determining that the memory consistency verification of the multi-core processor is compliant. Therefore, an RISC-V multi-core processor memory consistency verification scheme which can be integrated in a front simulation environment, supports real-time accurate verification and has high coverage is provided.

The invention relates to the technical field of computers, and discloses a method, a device, equipment and a medium for multi-thread undefined behavior detection, and the method comprises the following steps: constructing a control flow diagram and a data flow diagram based on a multi-thread program code, and creating a multi-thread execution path model based on the control flow diagram and the data flow diagram; distributing a thread fragment data set in the multi-thread execution path model to a plurality of computing nodes, and extracting an operation sequence in the distributed thread fragment data set in each computing node; performing iteration and layering processing on the operation sequence, and constructing a causal relationship graph; based on the causal relationship graph, generating an operation dependency track, mapping the operation dependency track to different memory models, performing execution sequence simulation to obtain a plurality of execution paths, and performing behavior analysis based on the execution paths to obtain a behavior analysis result. According to the method, the undefined behaviors in the multi-thread program can be systematically detected, and the stability and the safety of the system can be improved.

The invention discloses a real-time compiling interpreter system capable of running on an MCU (Microprogrammed Control Unit), an FPGA (Field Programmable Gate Array), a GPU (Graphics Processing Unit) or a universal CPU (Central Processing Unit), and belongs to the technical field of embedded systems and computer compiling. According to the system, hardware decoupling is achieved through a modular architecture, and C / C + +, Python and LLVM intermediate codes are supported to be converted into unified intermediate byte codes; a byte code interpreter and an instant compiling module are integrated, both quick starting and efficient execution are considered, and starting can be completed within 1 millisecond; an event driving and periodic scheduling mechanism is provided, and the real-time response requirement is met; a segmented memory model and a security policy are adopted, low-power-consumption edge equipment is adapted, and domestic instruction sets such as RISC-V and LoongArch are compatible. The system solves the problems that a traditional embedded system is poor in flexibility, difficult in cross-platform, insufficient in real-time performance and the like, can achieve unified execution of heterogeneous platform codes, is suitable for the fields of industrial control, Internet of Things edge AI and the like, and has remarkable technical progress and industrial value.

The invention provides a complex declaration fact checking method and system based on multi-hop retrieval and reasoning, and the method comprises the steps: obtaining a to-be-checked declaration statement, and constructing an evidence set corresponding to the declaration statement through a plurality of retrieval rounds; in each retrieval round, the declaration statement and an evidence statement in a current evidence set are combined, retrieval is conducted from a database through a constraint generation type retriever, the retrieved evidence statement is obtained, and the evidence statement is added into the evidence set; combining the declaration statement and each evidence statement in the evidence set into a declaration evidence pair, and inputting the declaration evidence pair into a recursive memory model for intrasentence reasoning to obtain a corresponding declaration evidence pair vector; constructing a multi-hop reasoning sub-graph corresponding to each evidence statement based on the declaration evidence pair vector, and obtaining an inter-sentence reasoning vector based on all the multi-hop reasoning sub-graphs; and inputting the inter-sentence reasoning vector into a preset MLP model to obtain a check result of the declaration statement.

Embodiments of the present application disclose a kind of group adaptive integrated control method, device, electronic equipment and storage medium, involve embodied intelligent technical field, wherein, the method includes: according to target scene characteristic, utilize physical modeling and domain randomization technology to generate diversified environment task set, and pre-processing is carried out to ensure data quality, train reinforcement learning coach based on these tasks, combine decoupling and backtracking policy distillation technology to synthesize training sequence, enhance the generalization and adaptive ability of model, adopt long-time memory model structure design base model, integrate multi-agent observation module to capture time sequence and spatial correlation, dynamic noise injection and asynchronous optimization are carried out in training process, the trained field base model is deployed to target scene, form collaborative network, and set fault-tolerant mechanism to deal with agent offline and other sudden situations, continuously collect actual data to optimize model parameters.The present application effectively solves the problems of high customization, weak migration and high maintenance cost in the prior art.

The invention provides a test project loading result prediction method and device, equipment and a storage medium, file index information used for representing the distribution condition of each sub-file in a test board card memory chip is generated based on configuration parameters of a to-be-loaded test project file, and a memory model is generated based on the file index information and the memory chip. According to the method, project file loading is simulated in an off-line mode, file loading prediction information and a file loading prediction result are obtained, if file simulation loading succeeds, the test project file is sent to the test board card for file loading, whether loading succeeds or not can be judged in advance without actual file loading, and the file loading efficiency is improved. And configuration parameter adjustment is carried out when file simulation loading fails, so that configuration parameter adjustment and secondary file loading after actual loading are avoided, the hardware loss of the test board card is reduced, the file loading efficiency can be improved, and the chip test efficiency is further improved.

The present invention discloses a method and system for determining an industrial process model, relating to the field of model determination technology. The method comprises: obtaining an industrial process text document to be identified; extracting an activity entity set from the industrial process text document to be identified using a BERT model, a bidirectional long-short word memory model, and a conditional random field model; the activity entity set includes multiple activity entities; inputting the activity entity set into an ordered neural network for identification to obtain a hierarchical structure tree; traversing the hierarchical structure tree according to the priority of each node to obtain a target industrial process model; the target industrial process model is used to describe the business process contained in the industrial process text document to be identified. The present invention combines the BERT model, the bidirectional long-short word memory model, and the conditional random field model to accurately identify each activity entity in the industrial process text document to be identified, thereby improving the accuracy of industrial process model determination.

The present application provides a secure data penetration testing method, including: pre-establishing a multi-threaded application race condition vulnerability feature library, performing static analysis on the source code of the target application to identify potential race condition vulnerability points and obtaining a preliminary set of vulnerability candidates; for the monitored suspected race condition events, abstracting the event context information into constraint conditions, using a constraint solver to explore the input combinations of the suspected static conditions, and determining the minimum input set that stably triggers the race condition; for the memory models and synchronization primitives of different programming languages, obtaining race condition anti-patterns and extracting general exploitation primitives covering various race condition vulnerabilities; during the penetration testing process, applying static analysis, dynamic monitoring, and symbolic execution to mine race condition vulnerabilities in the target application system, verifying the exploitability of the vulnerabilities, and assisting in completing the evaluation of the system security.

The invention provides a memory simulation method and device, equipment, a storage medium and a program product. The memory simulation method comprises the following steps: compiling a memory model and a plurality of simulation interfaces of the memory model in the hardware simulation platform; the method comprises the steps of determining a plurality of simulation interface combinations, establishing mapping between the simulation interface combinations and simulation storage positions, and determining a plurality of programming positions of first data according to the first data to be programmed; determining a first sequence based on the programming position and the simulation interface combination mapped by the programming position; second data are written into the first positions in the multiple first positions one by one, and the set data written into the multiple first positions form first data programmed in the memory model. According to the method and the device, the process of writing data into the first position mapped by the simulation interface combination one by one can be displayed.

The invention discloses an artificial intelligence grouping method and system based on power customer complaints, and the method is characterized in that the method comprises the following steps: obtaining power customer complaint information, and extracting complaint features from the power customer complaint information through employing a neural network; respectively inputting the complaint features into a plurality of hierarchical memory models according to information dimensions, and acquiring outputs of the plurality of hierarchical memory models; connecting the outputs of the plurality of hierarchical memory models, and estimating joint distribution of connection results; and judging the event emergency of the power customer complaint information based on the joint distribution, and issuing a power customer complaint work order according to the event emergency. The method is accurate and effective, the priority ranking of the automatic order sending service is realized, the response efficiency of the system is improved, and the effective response to the emergency complaint is ensured.

The present application discloses a Flink task management method, an electronic device, and a computer-readable storage medium, the method comprising: obtaining a configured task and determining the configuration information of the task; wherein the configuration information includes at least configuration items related to memory; based on the configuration items and the task memory model corresponding to the task, determining the memory to be verified of at least part of the memory area in the task memory model; verifying the memory to be verified and generating a verification log, and managing the task based on the verification log; wherein, when the memory to be verified of all the obtained memory areas passes the verification, the task can be submitted for operation. In the above manner, the present application can improve the memory verification feedback efficiency and the stability of task operation.

The invention discloses a piezoelectric sensor dynamic test calibration method based on a short memory grey model. The method comprises the following steps: constructing a piezoelectric sensor dynamic test short memory grey model; converting the short memory grey model into an algebraic model; establishing a model parameter identification algorithm based on the calibration of the piezoelectric sensor; based on the output of the sensor, the input of the piezoelectric sensor is calibrated through a short memory gray model. Modeling is carried out according to the dynamic response characteristic of the piezoelectric sensor, the response characteristic of the pressure input signal in a future period of time is utilized, and in turn, the pressure input signal is calibrated by utilizing the output in the future period of time. The model better conforms to the dynamic response characteristics of the pressure signals, and calibration is more accurate. According to the method, the short memory model is obtained by truncating the response according to the response rapidity of the sensor, so that the calibration precision is ensured, the calculation complexity is reduced, the calculation time is shortened, and the measurement rapidity is not obviously reduced.

A compiler comprises a low-level memory management (LLMM) module that locates computed entities within source code. Each computed entity is analyzed, and resource costs associated with each computed entity are calculated. A memory model is selected for each computed entity, based on memory use, computational complexity, and other factors. User-defined memory model assignment is supported. The compiler auto-generates instructions for allocating memory for, computing, and deallocating memory for each computed entity. The instructions generated for each computed entity will vary based on its assigned memory model. A variety of embodiments are disclosed for auto-generating these instructions during compile time at differing phases of compilation. In all of those, with the resultant executable code, memory is allocated and freed at runtime automatically and accurately without the intervention in source code by a programmer.

This disclosure relates to a method and computer device for controlling underwater vehicles. It pertains to the field of underwater navigation and addresses the safety and mission execution difficulties caused by underwater vehicles being detected. The method includes: constructing an underwater environment simulation model; acquiring passive detection data during the simulated operation of the underwater vehicle based on the underwater environment simulation model; training an explicit risk memory model based on the passive detection data from the underwater vehicle's operational history; generating a multi-dimensional observation vector indicating the current probability of detection based on the risk memory features output by the explicit risk memory model and instantaneous operational data; and performing memory fusion based on the multi-dimensional observation vector and the hidden state of the previous time step of the gated loop unit to output a normalized angular velocity control command to control the underwater vehicle. The technical solution provided by this disclosure is applicable to complex underwater navigation scenarios, achieving efficient and accurate autonomous decision-making for detection avoidance.

The invention discloses a Flink task management method, electronic equipment and a computer readable storage medium, and the method comprises the steps: obtaining a configured task, and determining the configuration information of the task; wherein the configuration information at least comprises configuration items related to the memory; based on the configuration item and a task memory model corresponding to the task, determining a to-be-verified memory of at least part of a memory area in the task memory model; verifying the to-be-verified memory and generating a verification log, and managing the task based on the verification log; wherein after the to-be-verified memories of all the obtained memory areas pass verification, the task can be submitted to run. By means of the mode, the memory verification feedback efficiency and the task operation stability can be improved.