72 results about "Memory model" patented technology

The invention discloses a Direct3D memory model compatible method based on adaptive placeholder resources, which comprises the following steps: establishing resource metadata, accessing a scene library, checking an instruction template and double sandboxes when a DXVK is started, describing related resources by the DXVK through the metadata after a D3D application is started, completing resource mapping and metadata dynamic updating, and allocating the resources to the corresponding sandboxes; the DXVK compiles an application shader code, identifies a resource access instruction, matches an access scene and a check template by combining a pipeline stage and binding slot query metadata, instantiates the check instruction and adds the check instruction to the front of a target instruction; according to the unbound resources, adaptive generation of corresponding occupied resources is carried out, the authority and the state are configured, the unbound resources are bound to a Vulkan descriptor set to replace VKNULLHANDLE, and adaptation of the shader interface and the pipeline state parameters is completed to create PSO (Particle Swarm Optimization); and intercepting an application rendering instruction analysis parameter to construct a command buffer area, submitting the command buffer area to a Vulkan queue to trigger a GPU (Graphic Processing Unit) to execute rendering, and finally completing complete conversion and adaptation from the D3D rendering logic to the Vulkan.

The invention discloses a large-model context control system and method based on hierarchical memory and an association graph, and the method comprises the steps: constructing a tree graph mixed memory structure and a logic hierarchical memory model for a context control unit between a user and an LLM, and carrying out the self-adaptive processing of a super-long context through a self-adaptive processing engine, a single-theme persistent dialogue control mechanism, and the like. According to the method, the problem that an LLM context window is limited (including introduction of a mechanism similar to an Agent) is solved, just like an operating system helps developers / users to solve the problems that hardware standards hidden behind are not uniform, and complex resource control is caused, a reliable LLM memory (context) control service with multiple details hidden is provided for upper developers, and the method has the advantages of being high in practicability and easy to popularize and use. The final objective of the method is to approximately relieve the limitation of an LLM context window through a set of self-consistent system mechanism, so that a developer does not need to pay too much attention to the details of a bottom layer, and more energy can be focused on the implementation of an application function.

The invention discloses a big language model dialogue system for Token-level resident memory and a use method. The big language model dialogue system comprises an inference engine module, a big language model module, an independent memory model module and an external storage module, relates to the technical field of big language model memory enhancement, after a current dialogue Token sequence is received, whether historical dialogue information is needed or not is judged through a big language model module, and if yes, the historical dialogue information is called from an external storage module through an independent memory model module, so that information displayed by finally responding to the Token sequence is more complete, and user experience is improved. The problems that a model cannot completely retain and utilize long-distance historical information, so that questions cannot be answered and information is forgotten are solved; an external storage module is arranged, and model parameters of an independent memory model module and Token-level data of all historical conversations are resided through a memory mapping technology; and zero occupation of the GPU video memory is realized.

The invention provides an object-oriented hierarchical memory network device. The object-oriented hierarchical memory network device comprises a low-level object sensing module, a space-time memory construction module and a long-term space-time memory modeling module, the low-level object sensing module is used for extracting object features of an input video through a segmentation basic model; the space-time memory construction module is used for extracting object interaction and scene information by analyzing an inter-frame space and time relationship so as to splice object features and input original video frames to generate a space representation of target perception; and the long-term space-time memory modeling module is used for storing historical information through a memory bank, capturing a global dependency relationship of a video level, and splicing a plurality of adjacent video frames output by the space-time memory construction module on a channel dimension to form local multi-frame space-time representation. And the purpose of enhancing the capturing capability of the model on fine-grained space-time dynamic in the long video is achieved.

The application relates to the chip technical field, in particular to a chip verification system based on a database, which comprises a first file database, a second file database, a verification IP and a first memory model arranged in the verification IP; the first file database is used for storing verification data; the verification IP reads the verification data in the first file database and stores the verification data into the first memory model through a structured query interface; the verification IP comprises a first data conversion interface and a second data conversion interface; the verification IP is also used for acquiring the verification data from the first memory model through the first data conversion interface, processing the verification data, generating result data, and storing the result data into the first memory model through the second data conversion interface; and the verification IP is also used for storing the result data in the first memory model into the second file database through the structured query interface. The application improves the chip verification efficiency.

The invention relates to a multi-core processor memory consistency verification method and device, the method is executed by a memory model in a processor co-simulation verification architecture, and the method comprises the following steps: monitoring a storage instruction of each processor core in an RTL, and maintaining a storage queue for each processor core based on the storage instruction; in response to a data request initiated when the ISS executes the loading instruction, speculating a set of compliance values possibly read by the loading instruction based on the storage queue and the visible relation of the storage instructions between the maintained different processor cores; comparing the actual read data of the loading instruction obtained from the RTL with the set of compliance values; and if the actually read data is in the set of compliance values, determining that the memory consistency verification of the multi-core processor is compliant. Therefore, an RISC-V multi-core processor memory consistency verification scheme which can be integrated in a front simulation environment, supports real-time accurate verification and has high coverage is provided.

The invention relates to the technical field of computers, and discloses a method, a device, equipment and a medium for multi-thread undefined behavior detection, and the method comprises the following steps: constructing a control flow diagram and a data flow diagram based on a multi-thread program code, and creating a multi-thread execution path model based on the control flow diagram and the data flow diagram; distributing a thread fragment data set in the multi-thread execution path model to a plurality of computing nodes, and extracting an operation sequence in the distributed thread fragment data set in each computing node; performing iteration and layering processing on the operation sequence, and constructing a causal relationship graph; based on the causal relationship graph, generating an operation dependency track, mapping the operation dependency track to different memory models, performing execution sequence simulation to obtain a plurality of execution paths, and performing behavior analysis based on the execution paths to obtain a behavior analysis result. According to the method, the undefined behaviors in the multi-thread program can be systematically detected, and the stability and the safety of the system can be improved.

The invention discloses a real-time compiling interpreter system capable of running on an MCU (Microprogrammed Control Unit), an FPGA (Field Programmable Gate Array), a GPU (Graphics Processing Unit) or a universal CPU (Central Processing Unit), and belongs to the technical field of embedded systems and computer compiling. According to the system, hardware decoupling is achieved through a modular architecture, and C / C + +, Python and LLVM intermediate codes are supported to be converted into unified intermediate byte codes; a byte code interpreter and an instant compiling module are integrated, both quick starting and efficient execution are considered, and starting can be completed within 1 millisecond; an event driving and periodic scheduling mechanism is provided, and the real-time response requirement is met; a segmented memory model and a security policy are adopted, low-power-consumption edge equipment is adapted, and domestic instruction sets such as RISC-V and LoongArch are compatible. The system solves the problems that a traditional embedded system is poor in flexibility, difficult in cross-platform, insufficient in real-time performance and the like, can achieve unified execution of heterogeneous platform codes, is suitable for the fields of industrial control, Internet of Things edge AI and the like, and has remarkable technical progress and industrial value.

Embodiments of the present application disclose a kind of group adaptive integrated control method, device, electronic equipment and storage medium, involve embodied intelligent technical field, wherein, the method includes: according to target scene characteristic, utilize physical modeling and domain randomization technology to generate diversified environment task set, and pre-processing is carried out to ensure data quality, train reinforcement learning coach based on these tasks, combine decoupling and backtracking policy distillation technology to synthesize training sequence, enhance the generalization and adaptive ability of model, adopt long-time memory model structure design base model, integrate multi-agent observation module to capture time sequence and spatial correlation, dynamic noise injection and asynchronous optimization are carried out in training process, the trained field base model is deployed to target scene, form collaborative network, and set fault-tolerant mechanism to deal with agent offline and other sudden situations, continuously collect actual data to optimize model parameters.The present application effectively solves the problems of high customization, weak migration and high maintenance cost in the prior art.

The invention provides a test project loading result prediction method and device, equipment and a storage medium, file index information used for representing the distribution condition of each sub-file in a test board card memory chip is generated based on configuration parameters of a to-be-loaded test project file, and a memory model is generated based on the file index information and the memory chip. According to the method, project file loading is simulated in an off-line mode, file loading prediction information and a file loading prediction result are obtained, if file simulation loading succeeds, the test project file is sent to the test board card for file loading, whether loading succeeds or not can be judged in advance without actual file loading, and the file loading efficiency is improved. And configuration parameter adjustment is carried out when file simulation loading fails, so that configuration parameter adjustment and secondary file loading after actual loading are avoided, the hardware loss of the test board card is reduced, the file loading efficiency can be improved, and the chip test efficiency is further improved.

The present invention discloses a method and system for determining an industrial process model, relating to the field of model determination technology. The method comprises: obtaining an industrial process text document to be identified; extracting an activity entity set from the industrial process text document to be identified using a BERT model, a bidirectional long-short word memory model, and a conditional random field model; the activity entity set includes multiple activity entities; inputting the activity entity set into an ordered neural network for identification to obtain a hierarchical structure tree; traversing the hierarchical structure tree according to the priority of each node to obtain a target industrial process model; the target industrial process model is used to describe the business process contained in the industrial process text document to be identified. The present invention combines the BERT model, the bidirectional long-short word memory model, and the conditional random field model to accurately identify each activity entity in the industrial process text document to be identified, thereby improving the accuracy of industrial process model determination.

The invention provides a memory simulation method and device, equipment, a storage medium and a program product. The memory simulation method comprises the following steps: compiling a memory model and a plurality of simulation interfaces of the memory model in the hardware simulation platform; the method comprises the steps of determining a plurality of simulation interface combinations, establishing mapping between the simulation interface combinations and simulation storage positions, and determining a plurality of programming positions of first data according to the first data to be programmed; determining a first sequence based on the programming position and the simulation interface combination mapped by the programming position; second data are written into the first positions in the multiple first positions one by one, and the set data written into the multiple first positions form first data programmed in the memory model. According to the method and the device, the process of writing data into the first position mapped by the simulation interface combination one by one can be displayed.

A compiler comprises a low-level memory management (LLMM) module that locates computed entities within source code. Each computed entity is analyzed, and resource costs associated with each computed entity are calculated. A memory model is selected for each computed entity, based on memory use, computational complexity, and other factors. User-defined memory model assignment is supported. The compiler auto-generates instructions for allocating memory for, computing, and deallocating memory for each computed entity. The instructions generated for each computed entity will vary based on its assigned memory model. A variety of embodiments are disclosed for auto-generating these instructions during compile time at differing phases of compilation. In all of those, with the resultant executable code, memory is allocated and freed at runtime automatically and accurately without the intervention in source code by a programmer.

This disclosure relates to a method and computer device for controlling underwater vehicles. It pertains to the field of underwater navigation and addresses the safety and mission execution difficulties caused by underwater vehicles being detected. The method includes: constructing an underwater environment simulation model; acquiring passive detection data during the simulated operation of the underwater vehicle based on the underwater environment simulation model; training an explicit risk memory model based on the passive detection data from the underwater vehicle's operational history; generating a multi-dimensional observation vector indicating the current probability of detection based on the risk memory features output by the explicit risk memory model and instantaneous operational data; and performing memory fusion based on the multi-dimensional observation vector and the hidden state of the previous time step of the gated loop unit to output a normalized angular velocity control command to control the underwater vehicle. The technical solution provided by this disclosure is applicable to complex underwater navigation scenarios, achieving efficient and accurate autonomous decision-making for detection avoidance.

The invention relates to a memory data verification method and device, equipment, a storage medium and a program product. The method comprises the steps that under the condition that a reading request sent by a design module is received, an address corresponding to a memory model is indexed according to an address range indicated in the reading request; receiving first data and second data returned by the memory model according to the address sequence of the index; the first data and the second data are the same data. First data are disordered and then returned to a design module, and second data are sent to a scoreboard through a monitor; and comparing the second data with the obtained reference data through the scoreboard to obtain a verification result. Therefore, the preposition of the random read-back verification point is realized, the debugging path is shortened, and the data verification efficiency is improved; and whether the data read back by the design module is consistent with the reference data or not is determined by directly setting the scoreboard, so that the consistency of the reference model and the design module during memory reading is ensured.

The embodiment of the invention provides a program detection method and device and computing equipment, and relates to the technical field of computers. The method comprises the steps of receiving a to-be-detected program, performing code detection on the program, and determining a statement where a global variable in the program is located; according to the library file and the statement where the global variable is located, the program is modified, and the modified program is obtained. According to the embodiment of the invention, the global variable is positioned through code detection, the global variable in a program does not need to be manually positioned, and the positioning efficiency and accuracy of the global variable can be improved. Moreover, the library file provided by the embodiment of the invention can provide a programming interface for realizing variable calculation operation, relation operation, logic operation or bit operation and other operation operations on the weak memory model, a memory barrier instruction does not need to be manually inserted, and the modification difficulty is reduced. Therefore, the program modification efficiency is improved. And through program modification, safe operation of the multi-thread program under the weak memory model is ensured.

The invention discloses a strategy generation method and device based on a collaborative time sequence model, equipment and a medium. The method is applied to a data caching scene, and comprises the following steps: acquiring a target time sequence semantic information set and a preset time period demand corresponding to a target external operation system; performing data prediction on target time sequence semantic information in the target time sequence semantic information set based on a target collaborative time sequence model containing a target moving average model and a target memory model and a preset time period demand to generate a target prediction result; and performing logic judgment on the target prediction result based on preset strategy adjustment logic to generate a logic judgment result, and generating a target caching strategy corresponding to the target time sequence semantic information based on the logic judgment result. Through the technical scheme of the invention, the cache hit rate can be improved and the manual intervention can be reduced through self-adaptive cache strategy adjustment, and the performance and the stability of the system in a high-concurrency scene can be improved.

The invention discloses a tree shrew visual association memory evaluation method based on an 8-shaped maze, and the method comprises the following steps: preparing before an experiment, including animal screening and environment setting; performing rule training, enabling the tree shrew to learn to associate the colors of the prompt board in the selection area with channel arm selection, including familiarity environment, door pushing training, shaping training and free selection test, and opening and closing the corresponding channel arm according to the colors of the prompt board in the shaping training; formal testing is carried out, shaping training is carried out twice every day, then free selection testing is carried out according to a 1-3 random mode, and the error rate is recorded; and performing modeling evaluation, namely evaluating whether a stable memory model is established or not based on an error rate of a formal test, and entering the formal test when the prompt board continuously appears for 1-3 times according to the same color and the conversion rate is 50-65% and the error rate is lower than 20% in the free selection test. According to the tree shrew visual association memory evaluation method provided by the invention, scientificity and statistical efficacy of behavior testing are ensured, and learning deviation caused by a fixed mode in a traditional method is overcome.

The invention relates to the technical field of chip verification, and discloses a to-be-tested design verification method, a verification environment building method, a verification environment and a chip verification device. The verification method comprises the steps that under the condition that a test excitation identifier is received, a target configuration file corresponding to the test excitation identifier is acquired through an excitation generation component; performing parameter analysis on the target configuration file through an analysis component to obtain a target configuration parameter set; and generating a test data packet based on the target configuration parameter set through the excitation generation component, and storing the test data packet to the memory model component, so that the to-be-tested design can use the test data packet to perform verification. Therefore, the target configuration parameter set corresponding to the test excitation is dynamically loaded by utilizing the excitation generation component, and the configuration parameters are stripped from the logic of hard generation excitation codes, so that the verification efficiency of the to-be-tested design is greatly improved.

The invention relates to the technical field of computers, in particular to a visual programming method and device and a readable storage medium. The method comprises the following steps: constructing a node graph of a double-layer connection system adopting separation of a data flow and a control flow to represent an algorithm logic; generating an abstract syntax tree which is semantically equivalent to the node graph, and establishing a bidirectional mapping relationship between the abstract syntax tree and the node graph; when the algorithm logic is executed, real-time memory state data including a call stack and a heap memory are captured through a tracking probe; and according to the data, dynamically generating a memory model visual view containing call stack and heap memory tracking. According to the method, the problems of unclear logic expression and opaque execution process in the prior art are solved, and the development and debugging efficiency is remarkably improved by intuitively presenting the dynamic execution process of the algorithm.

The invention discloses a long-term dialogue memory compression and dialogue model adaptation method, which comprises the following steps: S1, dialogue history compression based on a memory model: the memory model adopts a Transform architecture, so that memory update is carried out in a mode of redistributing attention distribution, and the dialogue history compression is carried out on the basis of the dialogue history compression; determining an attention distribution condition by combining the global self-attention between the memory and the cross attention of the new dialogue information and the memory; s2, memory perception adaptation of the dialogue model: on the premise of not changing original model parameters, accessing a cross attention linear mapping layer, and carrying out adaptation among different semantic spaces; s3, attention output calculation: final attention output is obtained in combination with self-attention and cross attention calculation results after adaptation; according to the method, in a dialogue scene, the dialogue content is compressed into the memory with the fixed size by using the compression model, so that the memory is dynamically updated along with the increase of dialogue rounds, the calculation complexity can be reduced, and the memory overhead is reduced.

The application discloses a kind of UVM automation verification methods of chip loading external memory function, belong to integrated circuit design and verification technical field.The method will test excitation be divided into the configuration information filled in by user and the control information generated automatically by formula to generate configuration file, with the aid of memory model reading configuration file and after powering on on chip, data is configured to specified register, cross-channel data verification is realized through analysis module, drive module and data check module, and data is read back from a node randomly selected in broadcast node for comparison for the register configured by broadcast.The method breaks through the limitation of single link verification, forms a closed loop of "configuration generation-simulation execution-cross-channel verification", realizes end-to-end automation verification, improves verification efficiency and reliability, reduces manual configuration error, accurately locates anomaly in real time, balances verification completeness and efficiency.

Embodiments of this disclosure relate to methods, apparatus, electronic devices, and products for determining memory usage. The method includes acquiring a set of memory usage information by initiating a set of parallel training sessions related to a target model, wherein each parallel training session in the set of parallel training sessions is configured using predetermined parallel parameters. The method also includes determining memory modeling parameters for the target model based on the set of memory usage information. Furthermore, the method includes determining multiple memory usage peaks of the target model in different parallel training sessions corresponding to different parallel parameters based on the memory modeling parameters. Thus, this method can model the memory usage of a target model using memory usage information from a set of parallel training sessions without knowing the specific network structure, thereby determining the maximum memory usage of the target model under different parallel configurations. This provides an important basis for automatic tuning of parallel training and avoids training interruptions or failures due to insufficient memory.

In various examples, a memory model may support multicasting where a single request for a memory access operation may be propagated to multiple physical addresses associated with multiple processing elements (e.g., corresponding to respective local memory). Thus, the request may cause data to be read from and / or written to memory for each of the processing elements. In some examples, a memory model exposes multicasting to processes. This may include providing for separate multicast and unicast instructions or shared instructions with one or more parameters (e.g., indicating a virtual address) being used to indicate multicasting or unicasting. Additionally or alternatively, whether a request(s) is processed using multicasting or unicasting may be opaque to a process and / or application or may otherwise be determined by the system. One or more constraints may be imposed on processing requests using multicasting to maintain a coherent memory interface.

The invention discloses a body navigation memory enhancement method and system based on spiking neurons. The method comprises the following steps: (1) constructing random parallel spiking neurons; (2) using a gating linear RNN as a basic structure of a cyclic memory model, and meanwhile, using a random parallel spiking neuron as a discrete gating function of the cyclic memory model; (3) adding the circulating memory model into the body-equipped intelligent agent, and carrying out reinforcement learning based on a long-term memory navigation task; in the actual navigation process of the body agent, the cyclic memory model maximizes the time significance signal-to-noise ratio through a discrete gating function, so that the capacity of filtering information irrelevant to tasks of the body agent is enhanced. According to the invention, the success rate of long-term memory navigation tasks can be improved.

The invention provides a training method, a resistance state adjusting method and an image processing method and device. The training method comprises the following steps: acquiring a simulation data set generated by a micro-magnetic simulation technology and an experiment data set obtained based on an experiment; a mixed data set is constructed according to the simulation data set and the experiment data set, the mixed data set comprises a plurality of sample pairs, and each sample pair comprises at least two mixed training samples; for each sample pair, processing the sample pair by using an initial memory model to obtain a first prediction performance parameter corresponding to each mixed training sample, and calculating a first residual error of at least two first prediction performance parameters; under the condition that the first residual error meets a residual error threshold value, testing the to-be-tested sample pair through an experiment so as to update the initial sample label, and obtaining a new sample label; and under the condition that a training set iteration termination condition is satisfied, training the initial memory model by using the updated mixed data set to obtain a magnetoresistive memory model.

A memory view generator evaluates a module design file characterizing a memory module to generate a set of port functions that defines operations of ports on a memory module for a memory view file. The memory view generator parses a memory module bitmap characterizing a physical layout of the memory module to determine a physical memory model of address bits, an order of rows, an order of columns, an order of banks and data bits of the memory module for the physical memory view file. A circuit simulator instantiates a memory module and provide simulation results based on a simulation memory model of the memory module, the set of port functions and the physical memory model. The memory view generator analyzes the simulation results to determine operational performance characteristics of the memory module for the memory view file.

1. Name of the product in this design: Memory Model (3D Stacked NAND). 2. Purpose of this design: For use in 3D stacked NAND memory models. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.

The invention discloses a subway robot interaction system based on multi-modal fusion, and the system comprises an information collection module which is used for collecting interaction object information, and constructing an interaction feature data set; the memory modeling module is used for constructing an interactive memory unit and attenuation control parameters; the confidence fusion module is used for constructing an interaction style vector and updating the interaction confidence; the semantic matching module is used for inputting the semantic candidate path set and the semantic state diagram into the improved GMN model to generate a path score list; and the response decision module is used for calculating a semantic confidence value of the preferred semantic path, executing an interactive output strategy in combination with the interactive semantic response scheme, and outputting semantic clarification information or confirmation instruction information or interactive response content. According to the method, the response accuracy and robustness of the subway robot in the man-machine interaction process are improved, and the method has the advantages of being high in response speed, high in fault tolerance and high in semantic matching precision.