Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure

An instruction set architecture, virtual processor technology, applied in the field of image processing, can solve problems such as lack of programming environment

Active Publication Date: 2018-01-02
GOOGLE LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, using custom-designed fixed-function circuits often results in a processor that can only perform a limited set of tasks
Thus, in the second extreme there is a lack of a broadly general programming environment (which is associated with the first extreme)

Method used

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  • Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure
  • Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure
  • Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure

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Experimental program
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Embodiment Construction

[0024] I. Introduction

[0025] The following describes several embodiments of a new image processing technology platform that provides an application software development environment that can be implemented into a hardware architecture using larger data blocks (e.g., line buffers and data slices described further below) to provide Improved power efficiency.

[0026] 1.0 Application software development environment

[0027] a. The application and structure of the kernel

[0028] figure 1 Shows a high-level view of an image processor technology platform that includes a virtual image processing environment 101, actual image processing hardware 103, and object code for translating high-level code written to the virtual processing environment 101 into physical execution on the actual hardware 103 compiler 102 . As detailed below, the virtual processing environment 101 is broadly generic in terms of the applications that can be developed and is tailored for simple visuali...

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Abstract

A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplatefirst and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

Description

technical field [0001] The field of the invention relates generally to image processing, and more particularly to exemplary target hardware for instruction set architecture (ISA) and memory models and having a two-dimensional shift array structure for image processing in virtualization. Background technique [0002] Image processing generally involves manipulating pixel values ​​organized into arrays. Here, the spatially organized two-dimensional array captures the two-dimensional nature of the image (additional dimensions may include time (eg, sequence of two-dimensional images) and data type (eg, color)). In typical scenarios, arrayed pixel values ​​are provided by cameras that generate still images or frame sequences to capture images in motion. Traditional image processors typically fall into one of two extremes. [0003] The first extreme performs image processing tasks as a software program executing on a general-purpose processor or general-purpose processor (eg, a ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T1/20G06T1/60
CPCG06T1/20G06F8/10G06F8/20G06F9/30G06F9/44G06F30/20G06F9/3004G06F9/30101G06T2200/28
Inventor 阿尔伯特·迈克斯纳奥弗尔·莎查姆戴维·帕特森丹尼尔·弗雷德里克·芬舍尔施泰因朱秋玲杰森·鲁珀特·莱德格雷夫
Owner GOOGLE LLC
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