62 results about "Memory load" patented technology

A computer-implemented method includes receiving a neural network model that includes memory load operations and a plurality of computation operations, selecting a memory load operation having an arithmetic intensity factor (AIF) greater than a threshold value from the memory load operations, grouping computation operations associated with data loaded by the selected memory load operation into two or more clusters of computation operations, and incorporating an instance of the selected memory load operation before each cluster of the two or more clusters of computation operations in the neural network model.

The invention provides a distributed rendering task scheduling method based on dynamic load balancing, which relates to the technical field of virtual reality simulation, and comprises the following steps: analyzing and preprocessing input physical simulation data through a multi-source model, and converting the format of the processed data into a manageable virtual set data format; loading the texture data to a video memory as required in a virtual mapping mode; dynamic memory loading and coloring are carried out based on the virtual set, and LOD generation is completed; dynamic task fragmentation and scheduling are carried out on the virtual set rendering task and the heterogeneous multi-source rendering task, real-time monitoring is carried out on GPU / CPU / memory loads of heterogeneous resources, and task scheduling is carried out according to a monitoring result; through a distributed cluster mode, a high-resolution rendering task is divided into a plurality of low-resolution rendering tasks, and the low-resolution rendering tasks are rendered on different nodes. According to the invention, high-fidelity, high-response and high-reliability three-dimensional scene simulation capability is provided for high-complexity scenes such as a hybrid system.

The invention discloses a memory equalization method and system based on edge computing, a medium and a program product, and relates to the field of electrical digital data processing.The method comprises the steps that memory release prediction time points of all edge computing devices are calculated according to the memory change rate; dividing a memory space into a calculation storage area and a temporary cache area; when it is detected that any target edge computing device exists, at least two candidate devices with the optimal communication quality with the target edge computing device are selected according to the network communication quality; sorting the candidate devices to obtain a candidate device queue; respectively migrating the overload data of the target edge computing device to a temporary cache region of each candidate device in the candidate device queue; controlling the target edge computing device to read corresponding overload data from the temporary cache region of the candidate device; and migrating the read overload data to a computing storage area with the memory usage amount lower than a preset threshold value in the plurality of edge computing devices. According to the invention, the memory load balancing efficiency is improved.

The invention relates to the field of unmanned aerial vehicle route analysis, and provides an unmanned aerial vehicle route safety analysis method and system for a Web side. Firstly, cube serialization is carried out on the laser point cloud according to the maximum cutting side length, and an octree index is established; secondly, converting the latitude and longitude of the air route into a self-defined rectangular coordinate system and sampling at equal intervals; screening point cloud sub-blocks intersected with the route buffer bounding box by using a separation axis theorem, executing radius query and nearest neighbor search in the sub-blocks based on KD-Tree, and bidirectionally judging a proximity relationship between route points and obstacle points; and finally, a three-dimensional result with a risk level label is generated and can be rendered in real time at a browser end. According to the method, calculation and memory loads can be greatly reduced, calculation efficiency is improved, centimeter-level real-time safety evaluation can be realized, and the method is suitable for multi-scene unmanned aerial vehicle operation such as power transmission inspection and urban surveying and mapping.

The embodiment of the invention provides a memory optimization method and device, electronic equipment and a storage medium. After a target program runs, memory running information is obtained; according to the memory operation information, a memory load level is obtained, and the memory load level represents the memory load level of the memory demand of the target program; according to the memory load level, a target optimization strategy is executed, the target optimization strategy comprises at least two conditional execution sub-optimization strategies, the sub-optimization strategies are used for releasing cache data of the corresponding type in the memory, and execution conditions of the sub-optimization strategies correspond to the memory load level. By judging the memory load level for the memory demand of the target program and executing the target optimization strategy based on the memory load level, dynamic type memory recovery based on the memory load level is realized, the problems of slow program loading speed, program lagging and the like caused by excessive memory recovery and untimely memory recovery are avoided, and the memory recovery efficiency is improved. And the use experience of the application program is improved.

A data processing system and method provides automated extraction, translation, load (ETL) operations. A server coupled with the processor executes the instructions and extracts data from various sources, such as cloud storage, external APIs and direct uploads. The system may include a stream mode processing unit to process large data files in manageable blocks, thereby improving efficiency and reducing memory load. It performs integrity checks to ensure data accuracy and consistency. The system configures and applies predefined and custom transitions, which is facilitated by user-friendly interface and API integration. Custom conversion logic is integrated into the process, allowing adaptive data operations to be performed. The converted data is then verified and formatted to be loaded into different destination systems. The ETL process is efficient, extensible and user-friendly, and thus suitable for wide data processing applications.

The invention discloses a data synchronization method, a storage medium, electronic equipment and a program product, and relates to the technical field of computers.The method comprises the steps that firstly, a master node can receive a data synchronization request sent by a slave node through an RDMA protocol; then acquiring synchronous data corresponding to the data synchronization request, writing the synchronous data into configured first CXL equipment, and generating a synchronous file corresponding to the synchronous data; and the synchronization file is sent to the slave node through an RDMA protocol, so that the slave node carries out memory loading on the synchronization data in the synchronization file through configured second CXL equipment. Compared with the prior art, the method has the advantages that the master node can send the synchronization file to the slave node through the RDMA protocol, a node kernel does not need to participate in data synchronization, time delay and resource consumption caused by multiple times of copying of the synchronization data in the node are reduced, the transmission speed of the synchronization data is increased, and then the data synchronization efficiency is improved.

An apparatus and method for efficiently processing vector memory accesses on an integrated circuit. In various implementations, a computing system includes a parallel data processing circuit with multiple, replicated compute circuits. Each compute circuit includes a cache that stores temporary data. A control circuit that identifies an instruction of the in-fight wavefronts as a long-latency vector memory access instruction with an indication specifying that a destination targets data storage in the cache, rather than a vector register file. The control circuit assigns a cache line for the vector memory access instruction while foregoing vector register assignment. The control circuit sends a data retrieval request to one or more higher levels of a cache memory subsystem. When the requested data has arrived, the control circuit stores the requested data in the assigned cache line and sends a notification to the corresponding SIMD circuit.

Data processing systems and methods provide for automated Extract, Transform, Load (ETL) operations. A server, coupled with a processor, executes instructions to extract data from various sources such as cloud storage, external APIs, and direct uploads. The system can include a stream mode processing unit for handling large data files in manageable chunks, thereby enhancing efficiency and reducing memory load. It performs integrity checks to ensure data accuracy and consistency. The system configures and applies both predefined and custom transformations, facilitated through a user-friendly interface and API integration. Custom transformation logic is integrated into the process, allowing for adaptable data manipulation. The transformed data is then validated and formatted for loading into diverse destination systems. This ETL process is efficient, scalable, and user-friendly, making it suitable for a wide range of data processing applications.

The application discloses a feature placement method and system for multi-GPU sampling graph neural network training, uniformly models a sampling graph neural network training process, and obtains hardware topology information; in a pre-sampling process, the number of times of accessing node features is counted as node heat, the node features are sorted according to the node heat, the node features are divided into a plurality of feature blocks according to a single-block capacity, and the feature blocks are divided into hot blocks or cold blocks according to block heat; based on the feature block set obtained by the division and the obtained hardware topology information, a mixed integer programming model is constructed, with the minimum bottleneck link time in a feature extraction stage and the memory load imbalance degree as targets, the mixed integer programming model is solved, and the placement position, access path and link flow of the globally jointly optimized hot block are obtained. The application can obtain a high-quality feature placement scheme under a given hardware constraint, minimize the extraction time, and improve the resource utilization rate of a multi-GPU system.

The invention discloses a multi-GPU sampling type graph neural network training-oriented feature placement method and system, and the method comprises the steps: carrying out the unified modeling of a sampling type graph neural network training process, and obtaining hardware topology information; in the pre-sampling process, counting the access times of the node features as node popularity, sorting the node features according to the node popularity, dividing the node features into a plurality of feature blocks according to single block capacity, and dividing the feature blocks into hot blocks or cold blocks according to block popularity; on the basis of the feature block set obtained through division and the obtained hardware topological information, a mixed integer programming model with the purpose of minimizing bottleneck link time and video memory load imbalance in the feature extraction stage is constructed, and the mixed integer programming model is solved; and obtaining the placement position, the access path and the link flow of the hot block subjected to global joint optimization. According to the method, a high-quality feature placement scheme can be obtained under given hardware constraints, so that the extraction time is minimized, and the resource utilization rate of a multi-GPU system is improved.

This invention discloses a method, apparatus, device, and storage medium for adjusting database resource queues. The adjustment method involves predicting the memory usage of resource queues in advance and analyzing business statements. First, historical memory usage information of resource queues over a time period is collected to determine the parameters of the ARIMA model based on the collected information, resulting in the final ARIMA model. This model is then used to predict the memory usage of resource queues over a time period, generating a memory usage prediction table. The memory load value of resource queues over a time period is then updated periodically. Next, the SQL statements in the business logic are parsed to predict the memory capacity required for execution. This, combined with the memory load value, enables automatic adjustment of the resource queues executing SQL statements in the database. This helps avoid resource waiting or timeouts in business applications and effectively improves data resource utilization.

The present invention belongs to the field of GEMM operation acceleration technology, and is a GEMM-based deep neural network acceleration method and system, the method comprising the steps of: firstly judging whether the input matrix multiplication is regular matrix multiplication or irregular matrix multiplication; adopting different slicing methods for different types of matrix multiplication: if it is regular matrix multiplication, traverse the pre-established slicing strategy to select the best strategy; if it is irregular matrix multiplication, first generate the slicing strategy according to the pre-established strategy and then select the strategy; when selecting the slicing strategy, take Kernel Occupancy as the basis; slice the matrix according to the selected slicing strategy; calculate the matrix slices and merge the calculation results. The present invention utilizes two different dynamic slicing methods and Kernel Occupancy through GEMM to improve the adaptability of the slicing size to reduce the number of unnecessary memory loading times while increasing the CU occupancy.

The invention belongs to the technical field of line resistance network analysis, and discloses a fast line resistance network analysis method for a nonvolatile memory array, which comprises the following steps of: establishing electrode KCL equations of all rows and columns in a line resistance network of the nonvolatile memory array; a voltage line and a coefficient matrix in the KCL equation are transformed and decomposed, a fixed point iterative algorithm is introduced, and voltage distribution of nodes at the top and the bottom of the array is iteratively calculated. An original complex large-scale linear equation set problem is converted into two small-scale sub-problems. And solving is carried out through mutual iteration of the two sub-problems, so that the calculation complexity and the calculation memory are reduced. According to the method, the influence of IR-drop on neural network calculation acceleration can be predicted and evaluated in the design stage. The method has the advantages that the accuracy is high, and the influence of IR-drop can be simulated with the accuracy exceeding 95%; the calculation complexity is low, and the calculation complexity is reduced from O ((2mn) 2) to O (mn); the memory load is small, and the use of the memory is minimized while high accuracy is kept.

To provide an integrated circuit device that performs, only once when power supply is connected first, a memory load operation that is performed at switching from a low-power mode to a high-power mode and thereby reduces the current amount used for memory loading.SOLUTION: An integrated circuit device according to the present invention is characterized by including: a memory for storing trim data; a sleep register for inputting trim data to a sleep function block; a normal register for inputting trim data to a normal function block; a memory controller for loading the trim data stored in the memory into the sleep register or the normal register; and a wake controller for loading the trim data stored in the normal register into the sleep register via the memory controller at a first self-wakeup time after power supply is connected, so as to ensure that the memory is loaded only once after power supply is connected.SELECTED DRAWING: Figure 2

The memory management method, device, electronic equipment and readable medium provided by the application belong to the technical field of computers. The method comprises the following steps: acquiring the memory load of a first distributed server running an application program; when the memory load exceeds a load threshold, instructing the first distributed server to stop running the application program, and forwarding traffic data sent to the first distributed server to a second distributed server, wherein the second distributed server is a distributed server in a distributed server cluster whose memory load does not exceed the load threshold; after detecting that the first distributed server stops running the application program, redeploying and starting the application program on the first distributed server, wherein the first distributed server releases the allocated memory in the first distributed server at the same time of stopping running the application program; and re-sending the traffic data of the application program to the first distributed server.

The present invention belongs to the technical field of line resistance network analysis, and discloses a fast line resistance network analysis method for a non-volatile memory array, comprising: establishing KCL equations for electrodes in all rows and columns of the line resistance network of the non-volatile memory array; transforming and decomposing the voltage lines and coefficient matrices in the KCL equations, introducing a fixed-point iteration algorithm, and iteratively calculating the voltage distribution of the top and bottom nodes of the array. The originally complex large-scale linear equations problem is converted into two smaller-scale sub-problems. The two sub-problems are solved by mutual iteration, thereby reducing the computational complexity and computational memory. The method of the present invention can predict and evaluate the impact of IR-drop on the acceleration of neural network calculations during the design phase. Advantages include: high accuracy, capable of simulating the impact of IR-drop with an accuracy of more than 95%; low computational complexity, reducing the computational complexity from O((2mn) 2 ) is reduced to O(mn); the memory load is small, minimizing memory usage while maintaining high accuracy.

The application provides a subgraph matching method and device. In the execution method, first, store the query graph and the data graph processed into a preset format; then, filter the data vertices in the query graph twice to generate a query vertex candidate set; then, connect the candidate vertices in the query vertex candidate set in a preset order to obtain a subgraph with the same structure as the query graph, and the preset order is to connect the core vertices in the candidate vertices in the query vertex candidate set first, and then connect the leaf vertices in the candidate vertices in the query vertex candidate set. The application filters the data vertices in the query graph twice, so that fewer invalid vertices are screened, and in the connection process, the vertices with a degree of one are connected first, and then the vertices with a degree of one are connected, which produces fewer invalid intermediate results, speeds up the subgraph matching speed, avoids occupying too much GPU memory, and further avoids the problem of excessive GPU memory load.

The application discloses a single-register multiplexing circuit and parameter configuration method for parameter configuration, and relates to the technical field of parameter configuration.The circuit comprises a group of configuration registers for storing and providing calibration parameters to an analog IP, wherein the configuration registers are multiplexed in a test mode and a normal working mode; and a multiplexing module coupled to the data input end of the configuration registers, used for selecting one way of data from a plurality of configuration data sources according to a preset priority strategy and writing the data into the configuration registers; wherein the plurality of configuration data sources at least include a default initial value, a nonvolatile memory loaded value and a test interface written value.The application effectively eliminates the problem that parameters cannot be effectively in real time in the traditional double-register architecture due to the separation of test registers and working registers, so that the calibration parameters written through the interface in the test stage can directly act on the analog IP, and it is not necessary to re-verify the power supply after burning the memory, thereby significantly improving the calibration efficiency.

This invention discloses a blockchain state management method and system based on delayed writes and a sliding window state tree. The method includes, in response to the execution of the current block, applying the generated state update to the sliding window state tree in memory and generating a local state commitment stored in the current block header; and, in response to the fulfillment of preset conditions, asynchronously calculating the global state root based on the accumulated state updates in the sliding window state tree and disclosing it in the header of subsequent blocks. This invention introduces a TCP-inspired congestion control strategy, adaptively adjusting the window span vector according to the number of active leaf nodes. By decoupling state root calculation from block verification, reducing disk I / O operations, and dynamically adjusting memory load, it significantly improves the transaction processing throughput, node verification efficiency, and attack resistance of the blockchain system, making it suitable for public blockchains, consortium blockchains, and permissioned blockchain environments.

The application discloses a kind of server low-power memory dynamic energy efficiency control method and system, belong to server storage technical field.The application is by collecting the running state data corresponding to each storage unit of server memory, generates the memory load prediction result in the set time range, simultaneously completes the hierarchical processing of memory storage data, based on load prediction result and hierarchical storage data matching and switches memory power supply operating mode, adjusts the refresh cycle of corresponding memory storage unit, again in combination with memory chip temperature data and the current effective power supply operating mode adjusts heat dissipation system operating parameter, completes the collaborative control of memory power consumption and heat dissipation.The application can realize energy efficiency dynamic optimization while guaranteeing the continuity of memory read-write operation, reduce the invalid energy consumption in the whole operation cycle of memory, avoid the performance decline caused by temperature fluctuation, improve the stability and energy efficiency level of memory operation.

The invention belongs to the technical field of large-scale deep learning model training, and particularly relates to a video memory scheduling system based on dynamic sequence length assembly line parallel training. The system comprises a dynamic recalculation module, a video memory arrangement and prefetching module and a mapping reconstruction module, the system collects the length and load information of each micro-batch before each round of iteration, establishes an optimization model with the goal of minimizing the iteration time, dynamically generates a re-calculation plan, and realizes inter-stage video memory load balancing; by introducing a collating stream and an asynchronous scheduler outside a main computing stream, overlapping execution of video memory collating and computing prefetching is realized, and the influence of fragment collating on training performance is reduced; a dynamic physical block mapping strategy is designed based on a CUDA virtual memory management mechanism, the physical block granularity is adaptively adjusted according to the idle state of the video memory, and the API calling and context switching overhead is reduced. Experimental results show that the video memory utilization rate and the system stability are remarkably improved, and an efficient video memory scheduling scheme is provided for large model training.

Disclosed is providing fast memory discard in a processor-based device. In this regard, an instruction set architecture (ISA) of the processor-based device provides a memory load instruction that indicates a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is executed, the value at the memory address does not need to be maintained). After the memory load instruction is received by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device and is used to perform the final memory load operation. After the final memory load operation is performed using the entry, the value of a discard indicator for the entry is set to indicate that the entry can be reused before its content is written to the system memory.

A transformer-based machine-learned model may use relative positions between token embeddings to more accurately predict outputs. Example outputs may include an object detection, sensor data segmentation, object state prediction, and / or the like. Efficiently computing relative position-aware attention scores of the transformer-based machine-learned model may comprise utilizing fast memory available in specialized hardware according to the memory loading and flushing techniques described herein.

An apparatus includes: latency determination circuitry configured to determine a predicted exposed latency associated with a memory load request targeting an address in memory, the predicted exposed latency corresponding to a stall that would be caused by waiting for the memory load request to complete had the data stored at the address in memory targeted by the memory load request not been prefetched into a cache; and prefetch control circuitry configured to control issuing of prefetch requests to prefetch data from a memory system based on the predicted exposed latency.

This invention discloses a memory tiered management and dynamic migration method and system based on hardware virtualization, relating to the fields of virtualization and hardware management technology. The specific steps of the method are: multi-source data collaborative collection, multi-source data fusion prediction, virtual machine memory tiered configuration, active migration trigger judgment, and tiered migration execution. This invention collects hardware health data and memory load data, uses a multi-source data fusion weight coefficient formula to weight and integrate differentiated data, and uses a memory pressure peak prediction formula and a hardware failure risk level quantification formula to predict memory bottlenecks and hardware failure risks in advance, thereby dynamically adjusting the virtual machine memory tiered configuration. For example, core business data is preferentially stored in the local high-speed cache and configured with the highest migration priority, while cold data layers are compressed to reduce resource consumption. This tiered management strategy improves memory access efficiency, and at the same time, the active migration trigger mechanism avoids service interruptions.

An apparatus having a firmware memory storing firmware, a cache memory loading at least a portion of the firmware for execution by a processor, and a firmware check engine having defined syndrome storage locations and iterating over cache line entries associated with firmware stored in the cache memory to: select a cache line entry; verify that an address mapped in the cache line entry maps to an address in the firmware memory, and when the cache line entry is locked and the address mapped in the cache line entry maps to an address in the firmware memory, compare the contents of the cache line entry to the contents of a corresponding address in the firmware stored in the firmware memory, and generate an integrity result indicating whether the integrity of the apparatus has been compromised. The abstract is not meant to be limiting.

The invention discloses a training deduction decoupling and asynchronous overlapping reinforcement learning method and system for a small language model, which is characterized in that a training deduction decoupling and iteration internal asynchronous scheduling method is adopted, and the parallel execution of reasoning and training is realized without changing the semantics and convergence properties of the original GRPO algorithm, so that the learning efficiency is improved. According to training deduction decoupling, reasoning Worker and training Worker are deployed on different GPU resource groups, and physical separation of Actor reasoning and training in the spatial dimension is achieved; the asynchronous scheduling in iteration realizes time overlapping of reasoning and training; the system is composed of a reasoning execution module, a Reference model calculation module, a reward generation module, a training module and the like and a parameter buffer area located in a CPU, and all the modules are unified and coordinated through a scheduling layer. Compared with the prior art, the method has the advantages that a localized, high-throughput and stable reinforcement learning training process is realized under the limited hardware condition by a user, and the system bottlenecks of communication amplification, resource coupling, computing-memory load imbalance and the like generally existing in a training system after SLM reinforcement learning are effectively solved.

A data operation device is disclosed. The data operation device comprises at least one memory configured to store a first data set represented as a first sparse matrix and a second data set represented as a second matrix, a vector unit configured to perform a row-wise product-based matrix multiplication operation based on the first sparse matrix and the second matrix and output a third data set represented as a third matrix, and a memory load unit configured to load into the vector unit first vector data associated with a row of the first sparse matrix from the first data set, and second vector data associated with a row of the second matrix that corresponds to an order of non-zero vector elements included in the first vector data from the second data set.

This application provides a communication method, system, and apparatus, applied in the field of communication technology. The method includes: acquiring first data and a first bandwidth, wherein the first data includes at least one of a first duration and a second duration, the first duration being the average duration of CPU pipeline pauses during a single execution of a load instruction by a CPU node from issuing a physical memory load request to obtaining a physical memory data response, the second duration being the average duration of CPU pipeline pauses during a single execution of a load instruction by a CPU node from issuing a physical memory load request to obtaining a physical memory data response, and the first bandwidth being the bandwidth of all memory controllers in the CPU node reading physical memory; and determining whether a CE storm fault has occurred in the local memory corresponding to the CPU node based on the first data and the first bandwidth. In the above solution, it is possible to detect whether a CE storm fault has occurred in the local memory corresponding to the CPU node without relying on hardware alarms or hardware interrupt notifications.