28 results about "Memory load" patented technology

The application discloses a feature placement method and system for multi-GPU sampling graph neural network training, uniformly models a sampling graph neural network training process, and obtains hardware topology information; in a pre-sampling process, the number of times of accessing node features is counted as node heat, the node features are sorted according to the node heat, the node features are divided into a plurality of feature blocks according to a single-block capacity, and the feature blocks are divided into hot blocks or cold blocks according to block heat; based on the feature block set obtained by the division and the obtained hardware topology information, a mixed integer programming model is constructed, with the minimum bottleneck link time in a feature extraction stage and the memory load imbalance degree as targets, the mixed integer programming model is solved, and the placement position, access path and link flow of the globally jointly optimized hot block are obtained. The application can obtain a high-quality feature placement scheme under a given hardware constraint, minimize the extraction time, and improve the resource utilization rate of a multi-GPU system.

The invention discloses a multi-GPU sampling type graph neural network training-oriented feature placement method and system, and the method comprises the steps: carrying out the unified modeling of a sampling type graph neural network training process, and obtaining hardware topology information; in the pre-sampling process, counting the access times of the node features as node popularity, sorting the node features according to the node popularity, dividing the node features into a plurality of feature blocks according to single block capacity, and dividing the feature blocks into hot blocks or cold blocks according to block popularity; on the basis of the feature block set obtained through division and the obtained hardware topological information, a mixed integer programming model with the purpose of minimizing bottleneck link time and video memory load imbalance in the feature extraction stage is constructed, and the mixed integer programming model is solved; and obtaining the placement position, the access path and the link flow of the hot block subjected to global joint optimization. According to the method, a high-quality feature placement scheme can be obtained under given hardware constraints, so that the extraction time is minimized, and the resource utilization rate of a multi-GPU system is improved.

This invention discloses a method, apparatus, device, and storage medium for adjusting database resource queues. The adjustment method involves predicting the memory usage of resource queues in advance and analyzing business statements. First, historical memory usage information of resource queues over a time period is collected to determine the parameters of the ARIMA model based on the collected information, resulting in the final ARIMA model. This model is then used to predict the memory usage of resource queues over a time period, generating a memory usage prediction table. The memory load value of resource queues over a time period is then updated periodically. Next, the SQL statements in the business logic are parsed to predict the memory capacity required for execution. This, combined with the memory load value, enables automatic adjustment of the resource queues executing SQL statements in the database. This helps avoid resource waiting or timeouts in business applications and effectively improves data resource utilization.

The memory management method, device, electronic equipment and readable medium provided by the application belong to the technical field of computers. The method comprises the following steps: acquiring the memory load of a first distributed server running an application program; when the memory load exceeds a load threshold, instructing the first distributed server to stop running the application program, and forwarding traffic data sent to the first distributed server to a second distributed server, wherein the second distributed server is a distributed server in a distributed server cluster whose memory load does not exceed the load threshold; after detecting that the first distributed server stops running the application program, redeploying and starting the application program on the first distributed server, wherein the first distributed server releases the allocated memory in the first distributed server at the same time of stopping running the application program; and re-sending the traffic data of the application program to the first distributed server.

The application provides a subgraph matching method and device. In the execution method, first, store the query graph and the data graph processed into a preset format; then, filter the data vertices in the query graph twice to generate a query vertex candidate set; then, connect the candidate vertices in the query vertex candidate set in a preset order to obtain a subgraph with the same structure as the query graph, and the preset order is to connect the core vertices in the candidate vertices in the query vertex candidate set first, and then connect the leaf vertices in the candidate vertices in the query vertex candidate set. The application filters the data vertices in the query graph twice, so that fewer invalid vertices are screened, and in the connection process, the vertices with a degree of one are connected first, and then the vertices with a degree of one are connected, which produces fewer invalid intermediate results, speeds up the subgraph matching speed, avoids occupying too much GPU memory, and further avoids the problem of excessive GPU memory load.

The application discloses a single-register multiplexing circuit and parameter configuration method for parameter configuration, and relates to the technical field of parameter configuration.The circuit comprises a group of configuration registers for storing and providing calibration parameters to an analog IP, wherein the configuration registers are multiplexed in a test mode and a normal working mode; and a multiplexing module coupled to the data input end of the configuration registers, used for selecting one way of data from a plurality of configuration data sources according to a preset priority strategy and writing the data into the configuration registers; wherein the plurality of configuration data sources at least include a default initial value, a nonvolatile memory loaded value and a test interface written value.The application effectively eliminates the problem that parameters cannot be effectively in real time in the traditional double-register architecture due to the separation of test registers and working registers, so that the calibration parameters written through the interface in the test stage can directly act on the analog IP, and it is not necessary to re-verify the power supply after burning the memory, thereby significantly improving the calibration efficiency.

This invention discloses a blockchain state management method and system based on delayed writes and a sliding window state tree. The method includes, in response to the execution of the current block, applying the generated state update to the sliding window state tree in memory and generating a local state commitment stored in the current block header; and, in response to the fulfillment of preset conditions, asynchronously calculating the global state root based on the accumulated state updates in the sliding window state tree and disclosing it in the header of subsequent blocks. This invention introduces a TCP-inspired congestion control strategy, adaptively adjusting the window span vector according to the number of active leaf nodes. By decoupling state root calculation from block verification, reducing disk I / O operations, and dynamically adjusting memory load, it significantly improves the transaction processing throughput, node verification efficiency, and attack resistance of the blockchain system, making it suitable for public blockchains, consortium blockchains, and permissioned blockchain environments.

The application discloses a kind of server low-power memory dynamic energy efficiency control method and system, belong to server storage technical field.The application is by collecting the running state data corresponding to each storage unit of server memory, generates the memory load prediction result in the set time range, simultaneously completes the hierarchical processing of memory storage data, based on load prediction result and hierarchical storage data matching and switches memory power supply operating mode, adjusts the refresh cycle of corresponding memory storage unit, again in combination with memory chip temperature data and the current effective power supply operating mode adjusts heat dissipation system operating parameter, completes the collaborative control of memory power consumption and heat dissipation.The application can realize energy efficiency dynamic optimization while guaranteeing the continuity of memory read-write operation, reduce the invalid energy consumption in the whole operation cycle of memory, avoid the performance decline caused by temperature fluctuation, improve the stability and energy efficiency level of memory operation.

The invention belongs to the technical field of large-scale deep learning model training, and particularly relates to a video memory scheduling system based on dynamic sequence length assembly line parallel training. The system comprises a dynamic recalculation module, a video memory arrangement and prefetching module and a mapping reconstruction module, the system collects the length and load information of each micro-batch before each round of iteration, establishes an optimization model with the goal of minimizing the iteration time, dynamically generates a re-calculation plan, and realizes inter-stage video memory load balancing; by introducing a collating stream and an asynchronous scheduler outside a main computing stream, overlapping execution of video memory collating and computing prefetching is realized, and the influence of fragment collating on training performance is reduced; a dynamic physical block mapping strategy is designed based on a CUDA virtual memory management mechanism, the physical block granularity is adaptively adjusted according to the idle state of the video memory, and the API calling and context switching overhead is reduced. Experimental results show that the video memory utilization rate and the system stability are remarkably improved, and an efficient video memory scheduling scheme is provided for large model training.

A transformer-based machine-learned model may use relative positions between token embeddings to more accurately predict outputs. Example outputs may include an object detection, sensor data segmentation, object state prediction, and / or the like. Efficiently computing relative position-aware attention scores of the transformer-based machine-learned model may comprise utilizing fast memory available in specialized hardware according to the memory loading and flushing techniques described herein.

An apparatus includes: latency determination circuitry configured to determine a predicted exposed latency associated with a memory load request targeting an address in memory, the predicted exposed latency corresponding to a stall that would be caused by waiting for the memory load request to complete had the data stored at the address in memory targeted by the memory load request not been prefetched into a cache; and prefetch control circuitry configured to control issuing of prefetch requests to prefetch data from a memory system based on the predicted exposed latency.

This invention discloses a memory tiered management and dynamic migration method and system based on hardware virtualization, relating to the fields of virtualization and hardware management technology. The specific steps of the method are: multi-source data collaborative collection, multi-source data fusion prediction, virtual machine memory tiered configuration, active migration trigger judgment, and tiered migration execution. This invention collects hardware health data and memory load data, uses a multi-source data fusion weight coefficient formula to weight and integrate differentiated data, and uses a memory pressure peak prediction formula and a hardware failure risk level quantification formula to predict memory bottlenecks and hardware failure risks in advance, thereby dynamically adjusting the virtual machine memory tiered configuration. For example, core business data is preferentially stored in the local high-speed cache and configured with the highest migration priority, while cold data layers are compressed to reduce resource consumption. This tiered management strategy improves memory access efficiency, and at the same time, the active migration trigger mechanism avoids service interruptions.

The invention discloses a training deduction decoupling and asynchronous overlapping reinforcement learning method and system for a small language model, which is characterized in that a training deduction decoupling and iteration internal asynchronous scheduling method is adopted, and the parallel execution of reasoning and training is realized without changing the semantics and convergence properties of the original GRPO algorithm, so that the learning efficiency is improved. According to training deduction decoupling, reasoning Worker and training Worker are deployed on different GPU resource groups, and physical separation of Actor reasoning and training in the spatial dimension is achieved; the asynchronous scheduling in iteration realizes time overlapping of reasoning and training; the system is composed of a reasoning execution module, a Reference model calculation module, a reward generation module, a training module and the like and a parameter buffer area located in a CPU, and all the modules are unified and coordinated through a scheduling layer. Compared with the prior art, the method has the advantages that a localized, high-throughput and stable reinforcement learning training process is realized under the limited hardware condition by a user, and the system bottlenecks of communication amplification, resource coupling, computing-memory load imbalance and the like generally existing in a training system after SLM reinforcement learning are effectively solved.

This application provides a communication method, system, and apparatus, applied in the field of communication technology. The method includes: acquiring first data and a first bandwidth, wherein the first data includes at least one of a first duration and a second duration, the first duration being the average duration of CPU pipeline pauses during a single execution of a load instruction by a CPU node from issuing a physical memory load request to obtaining a physical memory data response, the second duration being the average duration of CPU pipeline pauses during a single execution of a load instruction by a CPU node from issuing a physical memory load request to obtaining a physical memory data response, and the first bandwidth being the bandwidth of all memory controllers in the CPU node reading physical memory; and determining whether a CE storm fault has occurred in the local memory corresponding to the CPU node based on the first data and the first bandwidth. In the above solution, it is possible to detect whether a CE storm fault has occurred in the local memory corresponding to the CPU node without relying on hardware alarms or hardware interrupt notifications.

Provided in the present application are a communication method, system and apparatus, which are applied to the technical field of communications. The method comprises: acquiring first data and a first bandwidth, wherein the first data comprises at least one of a first duration and a second duration, the first duration is an average value of CPU pipeline stall durations in a process from sending a physical memory load request to acquiring a physical memory data response when a CPU node executes a single load instruction, the second duration is an average value of CPU pipeline durations in the process from sending the physical memory load request to acquiring the physical memory data response when the CPU node executes the single load instruction, and the first bandwidth is a bandwidth for reading a physical memory by all memory controllers in the CPU node; and on the basis of the first data and the first bandwidth, determining whether a CE storm fault has occurred in a local memory corresponding to the CPU node. In the solution, whether a CE storm fault has occurred in a local memory corresponding to a CPU node can be sensed without depending on a hardware alarm or a hardware interrupt notification.

To provide a new technique for reducing a load on a memory of a first communication device.SOLUTION: The first communication apparatus includes: a first storage control unit configured to, when variable first communication information for establishing a first wireless connection between the first communication apparatus and a second communication apparatus is acquired and the invariable identification information of the second communication apparatus is received from the second communication apparatus, store the first communication information and the identification information in association with each other in a memory; and a second storage control unit configured to, after the first wireless connection is disconnected, when variable second communication information for establishing a second wireless connection between the first communication apparatus and the second communication apparatus is acquired and the identification information is received from the second communication apparatus, delete the first communication information associated with the identification information from the memory and store the second communication information in association with the identification information in the memory.SELECTED DRAWING: Figure 3

The application relates to the technical field of cloud platform information service, in particular to an internet information service system and method based on a cloud platform, which comprises the following steps: acquiring CPU occupancy, memory occupancy and response time of each server of the cloud platform, and the traffic of the cloud platform accepting requests, and judging the update time point of the server weight in each period; analyzing the correlation between the CPU occupancy, memory occupancy and response time of the server in each period, so as to acquire the load synchronization coefficient of the server in each period; acquiring the memory load coefficient and the CPU load coefficient through the fluctuation and change trend of the memory occupancy and the CPU occupancy; acquiring the comprehensive load coefficient in combination with the load synchronization coefficient, so as to construct the weight adjustment coefficient of each server in each period, and acquire the server weight of each server in the next period of each period. The application can improve the rationality and accuracy of the request distribution of the cloud platform.

The invention discloses an expressway vehicle management system and method based on swarm intelligence, relates to the technical field of vehicle informatization management, and solves the technical problems of single communication data processing dimension, insufficient task allocation rationality, incomplete computing power scheduling mechanism, and weak load balancing and emergency response capability. According to the method, the node state is judged by combining the queue length, the CPU utilization rate and the memory load, the misjudgment rate is reduced, resource waste caused by false busy or idle is avoided, the scheduling response speed of the high-priority task is improved by performing different priority rating on the task, the pre-selected node is screened according to the processing requirement of the to-be-adjusted task, and the scheduling efficiency is improved. A node hardware adaptation degree distribution task is combined, the load fluctuation amplitude of the distributed node is controlled, overload is avoided, the type coefficient and the adaptation coefficient are introduced to dynamically calculate the computing power gap and the residual capacity, the calculation deviation is reduced, and an accurate basis is provided for scheduling.

Apparatuses and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates the relative ordering of memory access instructions in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and / or memory store instructions includes selecting a next memory load or memory store instruction to execute based on a dependency encoded within the block and a store vector to memory data indicating which memory load and memory store instructions in the instruction block have already executed. The store vector can be masked using a store mask. The store mask can be generated at the time the instruction block is decoded or copied from an instruction block header. Based on the encoded dependency and the masked store vector, the next instruction can be issued when its dependency is available.

The application belongs to the technical field of artificial intelligence and law, and specifically provides a legal knowledge question and answer method and device based on a large model memory, equipment and a medium, the method comprising: constructing a memory bank; converting valid legal information input by a user into standardized memory units; storing the standardized memory units in the memory bank; performing intent recognition on the current legal consultation question of the user, and determining whether the current legal consultation question of the user needs to be understood in combination with historical memory; recalling relevant standardized memory units and loading them into a work area to form a structured context; determining a reply generation strategy for the current user input according to the relationship label between the candidate memory units input by the current user and the historical memory loaded into the work area, generating a legal reply result for the current user input, and performing backwriting on the memory bank according to the legal reply result. The method aims to improve the organization ability, retrieval ability and consistency maintenance ability of the legal intelligent question and answer system for historical information.

A game task prompting method, comprising: determining task execution conditions and task completion conditions corresponding to at least one game task received by a target game account; at the start of a game match, displaying a game scene comprising a controlled virtual object corresponding to the target game account; during the game match, if a game environment in which the controlled virtual object is currently located in the game scene satisfies a task execution condition corresponding to a target game task, displaying task prompt information used for prompting the controlled virtual object to execute the target game task; and when the target game task satisfies an information display cancellation condition, cancelling the display of the task prompt information corresponding to the target game task. In this way, players can focus on core game experience during games, and when tasks are executable, the players are prompted immediately, thus reducing the task memory load of the players; moreover, task prompt information will not be displayed on interfaces for a long time, avoiding long-term blocking of the field of view of games.

A packet stream between a transmitter and a receiver in an unreliable and unordered switched packet network can be established as a result of receiving a second packet comprising a second memory operation on a memory address. Transmission of memory store command packets following memory load command packets in the packet stream can be serialized, and a synchronization operation between the transmitter and the receiver can be performed when a packet count at the receiver satisfies a number of data packets in the packet stream.

Some implementations relate to methods, systems, and computer readable media for partitioning large-scale virtual environments across multiple servers. Data representing a virtual environment is received, including multiple virtual regions with associated computational and memory loads. Communication metrics between adjacent virtual regions are determined. Each virtual region is assigned to a respective server based on balancing computational and memory loads and reducing communication metrics between virtual regions assigned to different servers. The assignment of virtual regions is refined iteratively, such that virtual regions with dense interaction are grouped together on a common server to reduce inter-server communication. State data for virtual regions located at boundaries between server assignments is replicated to neighboring servers. A distributed computing infrastructure is provided for the virtual environment, configured to simulate the virtual environment based on the assignment of virtual regions to the servers.

Memory controller circuitry for performing decryption (e.g., and load) operations and / or encryption (e.g., and store) operations utilizing a message authentication code (MAC) tag, as an initialization vector for a counter based stream cipher, that is stored in one or more error correction code (ECC) memory chips of a single memory module is described. In certain examples, a computing system includes a processing element to generate a memory load request for ciphertext; and a memory controller circuit to, in response to the memory load request: read the ciphertext, a message authentication code (MAC) tag, and an error correction code from memory, perform a first error correction operation on the ciphertext based on the error correction code to generate corrected ciphertext, perform a second error correction operation on the MAC tag based on the error correction code to generate a corrected MAC tag, perform a decryption operation on the corrected ciphertext based on the corrected MAC tag to generate a plaintext, generate a second MAC tag based on the plaintext, and provide the plaintext for the memory load request in response to the corrected MAC tag matching the second MAC tag. In certain examples, the error correcting codes may be encrypted to act as an initialization vector (IV) used for data encryption while still being capable of correcting the original plaintext where, in the case of an erroneous IV, trial and error may be used to recover the determine the correct IV.

The present disclosure provides a data loading method, an instruction execution device, a computing chip, an apparatus and a medium. The method comprises: decoding and splitting a segmented loading instruction into a plurality of first-level micro-operations; splitting the first-level micro-operations into at least one memory loading micro-operation and one vector calculation micro-operation; dispatching the memory loading micro-operation and the vector calculation micro-operation to a loading storage unit and a vector execution unit respectively; executing the at least one memory loading micro-operation by the loading storage unit to store original data loaded from a memory in a temporary storage area of a vector register; executing the vector calculation micro-operation by the vector execution unit to convert all original data corresponding to the first-level micro-operations into a shared data cache area; when the data is ready, rearranging the cached data in the shared data cache area in a vector element granularity; and writing back the rearranged data to a target vector register in the original order of the first-level micro-operations in the instruction.

A memory management circuit for performing decryption and load operations utilizing pigeonhole decoding and / or encryption and store operations utilizing pigeonhole encoding for stateless memory access control and replay protection is described. In certain examples, a computing system includes a processing element to generate a memory load request for a cache line of memory; and a memory management circuit to, in response to the memory load request: decrypt the cache line of memory to generate a first plaintext, read a symbol identification value and a locator value from a section of the first plaintext, determine a symbol based on the symbol identification value, insert the symbol into the first plaintext at a location based on the locator value to generate a second plaintext, and cause the second plaintext to be loaded for the memory load request. In certain examples, when multiple redundant symbols exist in a data line, the choice of which symbol is encoded in the data line may be used to make an access control decision where the choice of symbol corresponds to the identifier used to write the data line to memory.

The application provides a memory loading method and device, wherein the method comprises: obtaining memory requirements of a privileged domain when in a driving execution environment stage under a unified extensible firmware interface framework of a Xen system; determining a preset memory region conforming to the memory requirements through a memory mapping of the unified extensible firmware interface framework, and clearing the preset memory region and filling initialization information used by the privileged domain at startup; constructing a descriptor of the preset memory region, wherein the descriptor comprises the initialization information; and transferring the descriptor to a Xen system manager, so that the Xen system manager analyzes the descriptor and directly maps to a memory page of the privileged domain to perform memory preloading on the privileged domain.

This invention relates to the field of data processing technology, specifically to a data processing method, device, and computer medium. The data processing method includes the following steps: parsing memory load distribution patterns and instruction phase offsets; defining a node set to obtain a mapping layer; isolating nodes with sudden load changes to generate resource stability area blocks; labeling data skew and hole nodes to perform sharding and aggregation; removing low-throughput blocks to obtain monitoring results; comparing hash differences to match scheduling labels; and recording underlying attributes to form a classification dataset. In this invention, by tracing load distribution paths to map the underlying physical space, the resource misalignment defect caused by static partitioning is resolved, improving computing power accuracy; isolating nodes with sudden load changes and aggregating skewed and hole maps strengthens the ability to maintain stability in concurrent scenarios; eliminating data skew risks and bridging memory allocation defects; comparing hash distributions to construct a state discrimination mechanism; optimizing distribution logic and enhancing scheduling accuracy; and ensuring efficient, coherent, and stable data flow.