33 results about "Bad memory" patented technology

The application provides a memory fault positioning method and related device, and relates to the technical field of computers. The memory fault positioning method can comprise: when reading data from a memory, determining the position of a fault in the memory for a memory error; the position of the fault in the memory comprises some or all of the following: a faulty memory bank, a faulty memory column, a faulty memory particle, a faulty storage array, a faulty storage unit, a faulty row in a storage array, a faulty column in a storage array, a faulty bit, a faulty input / output channel, a faulty reading unit or a faulty sub-channel. The memory fault positioning method provided by the application can position faults at various granularities and accurately position the position of the fault in the memory, which is conducive to quickly repairing the memory fault.

Embodiments of the present application provide an error repairing method, device and equipment and a storage medium, the method comprising: collecting memory errors existing in a system, configuring a value of a target option in an active management technology (AMT) when it is detected that the memory errors meet preset conditions, calling a target callback function through the value of the target option to execute AMT testing, obtaining a test log corresponding to the AMT testing, storing the test log in a pre-allocated memory space, and determining an error repairing mode corresponding to the memory errors according to the test log. Embodiments of the present application can execute AMT testing under a system, avoid the problem that AMT testing needs to be restarted, selectively execute AMT testing and repair errors for memory errors generated in the system, and do not need to obtain logs through a serial port, thereby reducing dependence on the serial port and enhancing stability of log data acquisition.

Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed.

Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error / alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.

The application relates to a method for performing memory safety dynamic analysis on a program containing specific sentences. The method comprises the following steps: selecting a project directory or a single source code file to be instrumented; preprocessing the source code, replacing macro calls with the content in the macro definition, and commenting out the original macro call; generating a symbol table and an abstract syntax tree of the source code by using a compiler; traversing all nodes in the abstract syntax tree, performing static analysis on the source code, and modifying the source code for sentences that cannot be processed, and then re-instrumenting the source code; traversing all nodes in the abstract syntax tree, performing different instrumentations on the source code according to different node types, compiling the instrumented project directory or file by using a compiler, generating an executable file on a target system, and running the executable file, performing memory error detection on the program containing specific sentences, and reporting the position of the source code corresponding to the error. The method avoids the problems of instrumentation failure and the failure of correctly compiling the program after instrumentation.

A data storage device includes a memory block relinking system. The memory block relinking system identifies memory blocks that have been identified as grown bad blocks. The memory block relinking system analyzes the memory blocks that have been identified as grown bad blocks to determine whether a sub-block of the memory block is salvageable. To determine whether the sub-block is salvageable, the memory block relinking system executes one or more operations on the sub-block. If the operation fails, the sub-block is retired. If the operation is successful, the memory block relinking system identifies the sub-block as a relinking candidate. The memory block relinking system logically links the sub-block that was identified as a relinking candidate with one or more other sub-blocks that were previously identified as relinking candidates to form a metablock.

A memory and an electronic device are provided in the present application. The memory includes a bank. The bank includes two planes. Each of the two planes includes a plurality of memory resources and a plurality of redundant replacement resources. A bad memory resource of one of the two planes is capable of being replaced by the redundant replacement resource of an other of the two planes for performing a normal Read / Write operation. A first priority level of replacing the bad memory resource in the one of the two planes by the redundant replacement resource in a same plane is greater than a second priority level of replacing the bad memory resource by the redundant replacement resource in a different plane of the two planes.

The application relates to the technical field of server testing, and discloses a memory funnel error reporting mechanism test method, a device, equipment and a medium. The method comprises the following steps: based on a to-be-tested memory funnel error reporting mechanism, a funnel reporting period and a funnel quantity threshold value are configured in a basic input / output system; based on the funnel reporting period, the funnel quantity threshold value and a single error injection duration of a memory error injection tool, a memory funnel error test case is generated; using the memory error injection tool, correctable errors are injected into the memory according to the memory funnel error test case, and a system event log in a baseboard management controller is acquired; based on the relationship between memory error records in the log and expected memory error records corresponding to the memory funnel error test case, a test result of the to-be-tested memory funnel error reporting mechanism is determined. Thus, the automatic testing of the memory funnel error reporting mechanism is realized, manual intervention is not required in the middle of the testing process, the testing efficiency is improved, the manual testing cost is reduced, and long-term testing can be realized.

The embodiment of the application relates to the technical field of big data analysis and artificial intelligence, in particular to a memory fault prediction method, an electronic device and a computer readable storage medium. The memory fault prediction method comprises the following steps: obtaining a plurality of log data of a to-be-tested memory; wherein the plurality of log data at least comprises memory error information address data; performing feature engineering construction according to the plurality of log data to obtain a feature data table corresponding to each of the plurality of log data; splicing the feature data table corresponding to each of the plurality of log data to obtain a feature splicing data table; obtaining a fault prediction result of the to-be-tested memory according to the feature splicing data table and a pre-trained fault prediction model; wherein the fault prediction model is obtained by training a pre-collected training data set, and samples in the training data set comprise a plurality of log data of a plurality of memories, so that the accuracy of predicting memory faults can be improved.

The invention discloses a fault information storage method and device, electronic equipment and a storage medium, and belongs to the field of memories. The method comprises the following steps: responding to a target mode register to finish one-time memory error detection and scrubbing ECS result recording, and reading first address information with a memory error or second address information with the memory error recorded in the target mode register, the first address information is the address information corresponding to the memory error with successful error correction, and the second address information is the address information corresponding to the memory error with failed error correction; fault information corresponding to the memory error is stored in a nonvolatile memory, the fault information comprises the first address information or the second address information and identification information, and the identification information is used for identifying whether error correction of the memory error succeeds or not.

This disclosure provides systems, methods, and devices for memory systems that support detecting and tracking a quantity of errors in memory using a counter and indicating the detection and quantity of errors using an interrupt flag. In a first aspect, a method includes, at a hardware of a memory system detecting one or more errors at a memory. The method includes counting a quantity of the one or more errors until the quantity is equal to or greater than a threshold quantity of errors. The method includes recording the quantity of errors and an error type in an error log. The method includes transmitting an indication that the quantity of errors of the memory is equal to or greater than the threshold. Other aspects and features are also claimed and described.

Systems and methods are provided for implementing improved memory defect management. Bad pages, referring to portions of memory affected by memory errors, are identified by an operating system (“OS”) of a computing system. A list of bad pages may be periodically uploaded to a cloud data storage. The OS may also send the list of bad pages to a basic input / output system (“BIOS”) for repair of some of the bad pages. A list of repaired bad pages or corresponding status information may be sent to the OS. In some examples, the list of bad pages is compared with the list of repaired bad pages and may be updated accordingly. The list of bad pages may be compared with a previously uploaded list of bad pages that has been received from the cloud data storage. One list may be updated with, or replaced by, the other list based on the comparison.

This application discloses a data processing method and related apparatus. The method includes: obtaining a first request for requesting a first memory space; configuring a second memory space based on the first request, the second memory space including a first region and a second region, the first region being a simulated memory space of the first memory space, the access permissions of memory addresses in the first region being accessible, and the access permissions of memory addresses in the second region being inaccessible; obtaining a second request for accessing the first region; and determining that the second request has encountered an error if the access permissions of the memory addresses indicated by the second request are inaccessible. In this way, when the program requests memory space, an additional segment of memory space is allocated as a protected area, whose access permissions differ from those of a normally requested memory space, which helps to detect corresponding memory errors when the program accesses memory.

The application provides a binary program-oriented data-oriented vulnerability searching method, and belongs to the technical field of computers, and comprises the following steps: inputting test data into a target binary program in a computer and running the target binary program; saving a memory snapshot when the target binary program runs to a vulnerability function where a memory error vulnerability is located; marking test data data of a buffer zone input into the computer in the memory snapshot as a pollution source; and executing the target binary program with a first instruction of the vulnerability function as a starting point. If any memory copy Gadget that copies data in the memory to other memory positions and any address write Gadget that writes data in the memory are found in the process of executing the target binary program, it is determined that the current memory error vulnerability is sufficient to be upgraded to a data-oriented vulnerability DOP for exploitation. The method can analyze data-oriented vulnerability availability of a binary program.

The application provides a memory error processing method, system, device, storage medium and program product. An operating system kernel comprises a hardware error source driver, a first driver and a second driver. The second driver is used for processing a memory error processing task of an extended memory area. The first driver is used for processing a memory error processing task of a standard memory area. The first driver is used for distributing the memory error processing task of the extended memory area to the second driver. The method comprises the following steps: obtaining a memory error processing task of a target page distributed by the hardware error source driver; the target page has a memory error; if the target page is a memory page of the extended memory area, calling the second driver to perform error processing on the target page. The method improves the reliability of error processing.

The present application belongs to the technical field of memory test, and specifically provides a memory error causing downtime problem processing method, device, equipment and medium, the method comprises the following steps: detecting memory error and distinguishing error type; judging whether the error type is a memory correctable error; if yes, sending fault information to BMC and recording fault log; otherwise, performing degradation processing on the current memory error; judging whether the number of degraded memory errors reaches the corresponding module register threshold; if yes, performing physical isolation processing on the faulty memory; otherwise, sending memory degradation error log to BMC. The combination of fault memory isolation and fault degradation isolates a single fault memory, the main purpose is to make the system not down, and does not affect the normal business operation, but at the same time, the memory log situation can be clearly recorded, which is convenient for operation and maintenance to handle in time.

This invention discloses a memory error recovery method, apparatus, device, and medium based on a repeating page chain, relating to the field of computer system technology. The method includes: responding to a hardware memory error and determining whether the erroneous page is a KSM page; searching for a healthy copy in its repeating page chain; determining the recovery strategy level based on the parameters of the affected process, allocating a new physical page and adding it to the chain, copying data from the healthy copy to form a recovery copy; remapping the page table of the affected process to the recovery copy, updating the load count and sharing count, and isolating the erroneous page. By introducing dynamic thresholds, periodic degradation marking, health-level response, and a memory reservation pool mechanism, the fault tolerance threshold is significantly reduced, the fault tolerance protection scope is expanded, and the chain is given self-maintenance capabilities. This significantly improves the fault tolerance range and system reliability under extreme memory pressure while reducing performance jitter.

This invention provides a memory page isolation method, comprising: obtaining memory error information, including correctable memory errors; determining, based on the memory error information, the probability of an uncorrectable error occurring in the memory page and / or its row where the correctable memory error occurred; determining, based on the memory error information, the probability of an error storm occurring in the row where the memory page is located; determining an isolation strategy based on the probability of an uncorrectable error and the probability of an error storm; and applying the isolation strategy to the memory page and / or its row. This invention also provides a memory monitoring system. By collecting memory error verification information and more accurate CE (Error Detection) counts, this invention analyzes and predicts the probability of future UE (User Error Detection) and a large number of CEs occurring in the pages and rows to which the CEs belong, as well as the correlation between CE row errors and error storms. Based on the total number of isolateable pages and the probability of risk, strategies are flexibly set, ultimately reducing overall system downtime and performance impact.

The invention discloses a terminal resistor measuring method, a memory, a testing device and a storage medium, a terminal resistor is arranged in the memory, and the measuring method comprises the following steps: when the memory is in a wafer stage or a finished product stage, collecting a first voltage output from an output pin of the memory and a first current at an input pin of the memory; wherein the coupling point of the terminal resistor and the output pin is located behind the coupling point of the terminal resistor and the input pin, or the terminal resistor, the output pin and the input pin share the same coupling point; and measuring the resistance value of the terminal resistor by using the first voltage and the first current. Through the above mode, the resistance value of the terminal resistor in the memory can be measured when the memory is in the wafer stage or the finished product stage, and then the memory in the wafer stage or the finished product stage is subjected to quality screening based on the measured resistance value, and bad memories in the memory in the wafer stage and the memory in the finished product stage are eliminated. Therefore, the product yield of the memory is improved.

The present disclosure relates to a cloud service control method and device, a storage medium and an electronic device, to specifically handle memory errors and improve the processing efficiency of memory errors. The method comprises: when a memory error is detected, determining a memory address at which the memory error occurs, and determining an error type of the memory error according to the memory address, the error type being used to identify whether the memory error will cause a virtual machine to crash; determining a total error number of the detected memory error; and according to the error type of the memory error and the total error number, controlling a cloud scheduler to schedule a corresponding scheduling service from a scheduling service library, the scheduling service library storing a first scheduling service and a second scheduling service, the first scheduling service being used to control restarting a virtual machine on an original host to which the virtual machine belongs, and the second scheduling service being used to control migrating the virtual machine from the original host to which the virtual machine belongs to another host.

In one embodiment, a partition is executed in a primary server, with the partition accessing a first memory location at a first memory block address in the primary server. If a corresponding first memory location in a secondary server has an error, where the corresponding first memory location in the secondary server corresponds to the first memory location in the primary server, an object is moved from the first memory location in the primary server to a second memory location in the primary server.

Apparatuses, systems, and techniques to detect memory errors and isolate or migrate partitions on a parallel processing unit using an application programming interface to facilitate parallel computing, such as CUDA. In at least one embodiment, interrupts are intercepted and processed on a graphics processing unit indicating a memory error for one or more partitions, and a policy is applied to isolate that memory error from other partitions.

The invention discloses a memory error detection method and system suitable for an electric energy meter and a use and acquisition terminal, and relates to the technical field of computer software security. According to the method, a memory management function is hijacked, and distributed memory blocks are contained in a unified memory pool for management, wherein each memory block comprises a metadata structure, a prefix and suffix filling area and a element searching pointer; during memory allocation, request validity check is carried out, a memory block structure is initialized, and during memory release, various memory errors are detected by verifying the element searching pointer offset, the metadata magic number, the checksum and the completeness of the filling area. The system correspondingly comprises a memory management function hijacking module, a memory pool management module, a memory allocation processing module and a memory release processing module. According to the method, source codes do not need to be modified or instrumented, the overhead during operation is reduced, meanwhile, the detection capacity for errors such as illegal release, repeated release and out-of-border writing is expanded, and the method is suitable for development and debugging environments with high performance requirements.

A method includes detecting a memory error associated with a memory device of a storage unit of a set of storage units that is storing a set of encoded data slices, the storage unit services encoded data slice access messages from a processing unit, and the detecting occurs while attempting to access one or more of: a read threshold number (R) of encoded data slices, a decode threshold number (D) of encoded data slices needed to reconstruct the data segment, or a write threshold number (W) indicating a number of encoded data slices that must be accurately stored. The method further includes identifying an error descriptor code based on the detected memory error. The method further includes determining to perform an action based on the error descriptor code and executing the action to produce an action result.

The application provides a memory error processing method, device, equipment and program product. The method comprises the following steps: adding a first identifier to a first memory page in the case that a recoverable error occurs in the first memory page, wherein the first identifier is used to indicate that the memory page is unreliable; detecting the type of data stored in the first memory page; in the case that the first memory page stores first type data, migrating the data stored in the first memory page to a second memory page which is not added with the first identifier; wherein the content of the first type data is related to the application execution state of the system runtime. The above method can process the recoverable memory error in time and efficiently, and effectively avoids losing important data when the non-recoverable error occurs due to the frequent occurrence of the recoverable error.

This application discloses a server health prediction method, apparatus, device, and storage medium, relating to the field of server monitoring technology. The server health prediction method of this application first acquires server status indicator data for a target historical period; wherein, the status indicator data includes CPU temperature, CPU voltage, CPU current, memory temperature, memory voltage, memory current, GPU temperature, fan speed, memory ECC error count, and hard disk health parameters; then, based on the server status indicator data for the target historical period, the indicator health level for the target historical period is calculated; subsequently, based on the indicator health level of the target historical period and preset indicator health level weights, the server health level for the target historical period is calculated; finally, based on a prediction model, the server health level for a target future period is predicted according to the server health level of the target historical period. This application can achieve accurate prediction of server health.

The embodiment of the application discloses a memory error processing method, device, terminal and storage medium, and belongs to the memory field, and comprises the following steps: when a memory fault occurs, it is judged whether a read-write action occurs in a CPU execution context; when the CPU execution context is executed, an interrupt context is acquired, and it is judged whether the memory fault is in a write stage by using the interrupt context; when the write stage is executed, a page table entry is acquired, and it is judged whether it is a file mapping according to the page table entry; when the file mapping is executed, a physical page frame corresponding to the memory fault is determined, all page table entries related to the physical page frame are determined through reverse mapping, a physical page frame entry in the page table entry is atomically deleted, and a physical memory page corresponding to the virtual address is deleted from a file page cache; a free physical memory page is allocated, added to the file page cache, and initialized for a read operation; and the virtual memory and the free physical memory page of the file page cache are associated through the page table entry.

This invention discloses a memory fault handling system, method, electronic device, and program product, relating to the field of computer technology. The system includes memory, a management controller, and a central processing unit (CPU). The CPU reads system operation data from the memory via a physical link and determines memory error information. The management controller constructs two isolated processes. During the process of the first process collecting memory error information through an out-of-band interface, it listens for a trigger signal to adjust the collection parameters and adjusts the initial data collection parameters according to the signal type of the trigger signal. The second process receives the memory error information sent by the first process and triggers a fault repair operation when a memory fault is predicted based on the memory error information. This invention can solve the problems of high-frequency data collection operations affecting device performance, increasing energy consumption, and wasting resources in related technologies, enabling low-interference memory fault prediction and repair, and effectively improving memory reliability and availability.

The embodiment of the invention discloses a memory error processing method and device, a terminal and a storage medium, and belongs to the field of memorys.The memory error processing method comprises the steps that when a memory breaks down, whether a read-write action occurs when a CPU executes a context or not is judged, when the context is executed for the CPU, an interrupt context is obtained, and whether the memory breaks down or not is in a writing stage or not is judged through the interrupt context; in the writing stage, obtaining a page table item, and judging whether file mapping is performed or not according to the page table item; when file mapping is carried out, determining a physical page frame corresponding to a memory fault, determining all page table entries related to the physical page frame through reverse mapping, carrying out atomic deletion on the physical page frame entries in the page table entries, and deleting a physical memory page corresponding to the virtual address from a file page cache; distributing an idle physical memory page, adding a file page cache, and initializing a read operation; and associating the virtual memory with an idle physical memory page of the file page cache through a page table item.