56 results about "Bad memory" patented technology

The invention discloses a memory error correction method, a server system, electronic equipment and a storage medium, and relates to the technical field of storage software, and the method comprises the following steps: under the condition that a memory generates a current uncorrectable error, based on an uncorrectable error evolution rule, correcting the current uncorrectable error; a group of target historical correctable errors matched with the memory address of the current uncorrectable error is extracted from a historical error record file, the group of target historical correctable errors are tried to be corrected, and once the group of target historical correctable errors are successfully processed, the current uncorrectable error has an opportunity to be converted into a derivative correctable error, so that the correctable error cannot be corrected. According to the method, the source or mode of the current uncorrectable error is changed, at the moment, the memory error processing mechanism plays a role again, and then the derivative correctable error is corrected, so that the current uncorrectable error is fundamentally solved, and the problem that the multi-bit error cannot be effectively corrected when the uncorrectable error occurs in the memory is solved. And the problems of data loss and server system stability reduction are solved.

Memory with enhanced fail tracking, and associated systems, devices, and methods, are disclosed herein. In one embodiment, a memory device comprises a memory array and fail tracking circuitry. The fail tracking circuitry can include a counter and a plurality of memory slots and can be configured to, for each memory row of a plurality of memory rows in a memory region of the memory array, (a) count errors detected in data read from the memory row to determine an error count, and (b) store the error count and address information for the memory row in a memory slot of the plurality of memory slots. In some embodiments, the fail tracking circuitry can be configured to count the errors and store the error counts during error check and scrub operations of the memory device (e.g., to identify the worst memory rows in the memory region for post-package repair operations).

The invention discloses a method and a system for protecting privacy of source codes in memory error detection, belongs to the technical field of computer software security, and particularly relates to a technology for protecting confidentiality of the source codes in a third-party memory error analysis process of software. According to the method, a debugging information minimization processing system DIREDUCER is constructed, a selective deletion and type minimization technology is utilized, on the premise that complete source codes are not exposed, necessary debugging information used for memory error detection is effectively reserved, and dual guarantee of source code privacy and memory error detection effects is achieved. According to the method, the debugging information in the non-stripping binary file is compressed to be within 10% of the original volume, and the recognition capability of an analysis tool on the problems such as memory leak, buffer overflow and overhanging pointers is not remarkably reduced. Experimental results show that the method has good adaptability and expandability in actual deployment, is suitable for various debugging tools and binary analysis frameworks, and has wide application prospects and practical values.

Systems and methods include an Information Handling System (IHS) that is adapted to provide memory diagnostics for use in identifying replaceable memory modules that are starting to fail. Upon initialization of an IHS that includes replaceable memory modules, a plurality of memory device drivers are loaded for use in accessing the replaceable memory modules. Each memory device driver is adapted to support a diagnostic API (Application Programming Interface). The IHS detects memory errors resulting from attempts throughout the IHS to access the replaceable memory modules. A memory address associated with the detected memory error is determined and the diagnostic API of a memory device driver is used to identify a specific replaceable memory module as the source of the memory error.

The invention provides a memory error processing method, system and device, a storage medium and a program product, an operating system kernel comprises a hardware error source driver, a first driver and a second driver, and the second driver is used for processing a memory error processing task of an extended memory area. The first driver is used for processing a memory error processing task of a standard memory area and distributing a memory error processing task of an extended memory area to a second driver, and the method comprises the following steps: acquiring a memory error processing task of a target page distributed by a hardware error source driver; memory errors exist in the target page; and if the target page is the memory page of the extended memory area, calling the second driver to carry out error processing on the target page. According to the method, the reliability of error processing is improved.

The invention provides a high-efficiency memory repair system and method based on a pooling memory. The method comprises the following steps: a memory test module performs UCE error address detection on a memory bank by taking cache as granularity; the management module is used for converting the memory error address into a memory page address to which the memory error address belongs, and issuing a repair command for the memory page address; the address routing module replaces and adds a memory page address into a routing table by utilizing a routing table look-up algorithm according to the repair command so as to finish address repair, performs corresponding address conversion according to a repair state of an accessed host memory address, and routes the address to a port where the memory bank or the out-of-band storage module is located; and the out-of-band storage module is an out-of-band memory pool independent of the system memory pool and is used for repairing the damaged memory by taking the memory page as the granularity. According to the method, the effects of improving the utilization efficiency and compatibility of the memory and enhancing the RAS system of the memory are achieved through the high-efficiency memory repair system which is provided with the out-of-band memory module and takes the memory page capable of being dynamically configured as the granularity.

The application provides a memory fault positioning method and related device, and relates to the technical field of computers. The memory fault positioning method can comprise: when reading data from a memory, determining the position of a fault in the memory for a memory error; the position of the fault in the memory comprises some or all of the following: a faulty memory bank, a faulty memory column, a faulty memory particle, a faulty storage array, a faulty storage unit, a faulty row in a storage array, a faulty column in a storage array, a faulty bit, a faulty input / output channel, a faulty reading unit or a faulty sub-channel. The memory fault positioning method provided by the application can position faults at various granularities and accurately position the position of the fault in the memory, which is conducive to quickly repairing the memory fault.

Embodiments of the present application provide an error repairing method, device and equipment and a storage medium, the method comprising: collecting memory errors existing in a system, configuring a value of a target option in an active management technology (AMT) when it is detected that the memory errors meet preset conditions, calling a target callback function through the value of the target option to execute AMT testing, obtaining a test log corresponding to the AMT testing, storing the test log in a pre-allocated memory space, and determining an error repairing mode corresponding to the memory errors according to the test log. Embodiments of the present application can execute AMT testing under a system, avoid the problem that AMT testing needs to be restarted, selectively execute AMT testing and repair errors for memory errors generated in the system, and do not need to obtain logs through a serial port, thereby reducing dependence on the serial port and enhancing stability of log data acquisition.

Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed.

When it is determined that a first super memory block among a plurality of super memory blocks satisfies an exchange condition, the storage device may exchange a first memory unit in the first super memory block with a second memory unit included in a second super memory block among the plurality of super memory blocks. In this case, the first memory unit is a bad memory unit and the second memory unit is a normal memory unit.

The application discloses a C / C++ post-release re-reference dynamic detection method based on pointer dereference insertion, and when software testing is performed, a traditional Address Sanitizer cannot detect logical errors of address legality; the application realizes dynamic detection of pointer reuse memory errors through data flow analysis and insertion of GetElementPtr instructions.

The application provides a high-efficiency memory repair system and method based on a pooling memory, which comprises a memory test module for detecting UCE error addresses of a memory bank with cacheline as a granularity; a management module for converting memory error addresses into memory page addresses, and issuing repair commands for the memory page addresses; an address routing module for replacing and adding the memory page addresses into a routing table by using a routing lookup table algorithm to complete address repair, and for performing corresponding address conversion and routing to a port where the memory bank or the out-of-band storage module is located according to a repair state of a host memory address accessed; and an out-of-band storage module for repairing damaged memory with memory page as a granularity. The application achieves the effects of improving memory utilization efficiency and compatibility, and enhancing a memory RAS system by using the out-of-band storage module and the high-efficiency memory repair system with dynamically configurable memory page as a granularity.

Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error / alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.

This application discloses a method, apparatus, storage medium, and electronic device for repairing server memory, relating to the field of artificial intelligence technology. The method includes: determining first resource information corresponding to repair resources in the server, the first resource information indicating the state of resources in the server that can be used to repair memory errors; searching for a target rule in a rule lookup table based on the first resource information and first error information of the server memory, the first error information indicating errors occurring in the server memory within a preset period, the rule lookup table indicating the correspondence between the first resource information, the first error information, and reference rules, the reference rules including the target rule; determining a target threshold based on the target rule and the first error information; and repairing the server memory using repair resources when the first error information and the target threshold meet preset repair conditions. This solves the technical problem of low resource utilization in related server memory repair methods.

The application relates to a method for performing memory safety dynamic analysis on a program containing specific sentences. The method comprises the following steps: selecting a project directory or a single source code file to be instrumented; preprocessing the source code, replacing macro calls with the content in the macro definition, and commenting out the original macro call; generating a symbol table and an abstract syntax tree of the source code by using a compiler; traversing all nodes in the abstract syntax tree, performing static analysis on the source code, and modifying the source code for sentences that cannot be processed, and then re-instrumenting the source code; traversing all nodes in the abstract syntax tree, performing different instrumentations on the source code according to different node types, compiling the instrumented project directory or file by using a compiler, generating an executable file on a target system, and running the executable file, performing memory error detection on the program containing specific sentences, and reporting the position of the source code corresponding to the error. The method avoids the problems of instrumentation failure and the failure of correctly compiling the program after instrumentation.

A data storage device includes a memory block relinking system. The memory block relinking system identifies memory blocks that have been identified as grown bad blocks. The memory block relinking system analyzes the memory blocks that have been identified as grown bad blocks to determine whether a sub-block of the memory block is salvageable. To determine whether the sub-block is salvageable, the memory block relinking system executes one or more operations on the sub-block. If the operation fails, the sub-block is retired. If the operation is successful, the memory block relinking system identifies the sub-block as a relinking candidate. The memory block relinking system logically links the sub-block that was identified as a relinking candidate with one or more other sub-blocks that were previously identified as relinking candidates to form a metablock.

The invention discloses a server memory repairing method and device, a storage medium and electronic equipment, and relates to the technical field of artificial intelligence, and the method comprises the steps that first resource information corresponding to a repairing resource in a server is determined, and the first resource information is used for indicating a resource state capable of being used for repairing a memory error in the server; a target rule is searched in a rule comparison table based on the first resource information and first error information of a server memory, the first error information is used for indicating that an error occurring in a preset period exists in the server, and the rule comparison table is used for indicating a corresponding relation among the first resource information, the first error information and a reference rule; the reference rule comprises a target rule; determining a target threshold according to the target rule and the first error information; and under the condition that the first error information and the target threshold value meet a preset repair condition, repairing the server memory by utilizing a repair resource. The technical problem that the resource utilization rate is low in a server memory repairing method in the related technology is solved.

A memory and an electronic device are provided in the present application. The memory includes a bank. The bank includes two planes. Each of the two planes includes a plurality of memory resources and a plurality of redundant replacement resources. A bad memory resource of one of the two planes is capable of being replaced by the redundant replacement resource of an other of the two planes for performing a normal Read / Write operation. A first priority level of replacing the bad memory resource in the one of the two planes by the redundant replacement resource in a same plane is greater than a second priority level of replacing the bad memory resource by the redundant replacement resource in a different plane of the two planes.

This application discloses a memory fault management system, method, server, and electronic device, relating to the field of computer technology. It includes a hardware memory processing circuit with a hardware layer and a processor, the processor being further divided into a kernel layer, a user layer, and an input / output layer. Through the collaborative work of the hardware layer and various software layers, it achieves hierarchical detection, classification processing, and automatic isolation of memory error data, effectively preventing server downtime caused by memory fault data. Simultaneously, through the linkage mechanism between kernel mode and user mode, combined with visual display, it enhances the monitorability and maintainability of memory errors, facilitating rapid problem location and repair by maintenance personnel and reducing system maintenance costs.

The application relates to the technical field of server testing, and discloses a memory funnel error reporting mechanism test method, a device, equipment and a medium. The method comprises the following steps: based on a to-be-tested memory funnel error reporting mechanism, a funnel reporting period and a funnel quantity threshold value are configured in a basic input / output system; based on the funnel reporting period, the funnel quantity threshold value and a single error injection duration of a memory error injection tool, a memory funnel error test case is generated; using the memory error injection tool, correctable errors are injected into the memory according to the memory funnel error test case, and a system event log in a baseboard management controller is acquired; based on the relationship between memory error records in the log and expected memory error records corresponding to the memory funnel error test case, a test result of the to-be-tested memory funnel error reporting mechanism is determined. Thus, the automatic testing of the memory funnel error reporting mechanism is realized, manual intervention is not required in the middle of the testing process, the testing efficiency is improved, the manual testing cost is reduced, and long-term testing can be realized.

The embodiment of the application relates to the technical field of big data analysis and artificial intelligence, in particular to a memory fault prediction method, an electronic device and a computer readable storage medium. The memory fault prediction method comprises the following steps: obtaining a plurality of log data of a to-be-tested memory; wherein the plurality of log data at least comprises memory error information address data; performing feature engineering construction according to the plurality of log data to obtain a feature data table corresponding to each of the plurality of log data; splicing the feature data table corresponding to each of the plurality of log data to obtain a feature splicing data table; obtaining a fault prediction result of the to-be-tested memory according to the feature splicing data table and a pre-trained fault prediction model; wherein the fault prediction model is obtained by training a pre-collected training data set, and samples in the training data set comprise a plurality of log data of a plurality of memories, so that the accuracy of predicting memory faults can be improved.

The invention discloses a fault information storage method and device, electronic equipment and a storage medium, and belongs to the field of memories. The method comprises the following steps: responding to a target mode register to finish one-time memory error detection and scrubbing ECS result recording, and reading first address information with a memory error or second address information with the memory error recorded in the target mode register, the first address information is the address information corresponding to the memory error with successful error correction, and the second address information is the address information corresponding to the memory error with failed error correction; fault information corresponding to the memory error is stored in a nonvolatile memory, the fault information comprises the first address information or the second address information and identification information, and the identification information is used for identifying whether error correction of the memory error succeeds or not.

This disclosure provides systems, methods, and devices for memory systems that support detecting and tracking a quantity of errors in memory using a counter and indicating the detection and quantity of errors using an interrupt flag. In a first aspect, a method includes, at a hardware of a memory system detecting one or more errors at a memory. The method includes counting a quantity of the one or more errors until the quantity is equal to or greater than a threshold quantity of errors. The method includes recording the quantity of errors and an error type in an error log. The method includes transmitting an indication that the quantity of errors of the memory is equal to or greater than the threshold. Other aspects and features are also claimed and described.

Systems and methods are provided for implementing improved memory defect management. Bad pages, referring to portions of memory affected by memory errors, are identified by an operating system (“OS”) of a computing system. A list of bad pages may be periodically uploaded to a cloud data storage. The OS may also send the list of bad pages to a basic input / output system (“BIOS”) for repair of some of the bad pages. A list of repaired bad pages or corresponding status information may be sent to the OS. In some examples, the list of bad pages is compared with the list of repaired bad pages and may be updated accordingly. The list of bad pages may be compared with a previously uploaded list of bad pages that has been received from the cloud data storage. One list may be updated with, or replaced by, the other list based on the comparison.

This application discloses a data processing method and related apparatus. The method includes: obtaining a first request for requesting a first memory space; configuring a second memory space based on the first request, the second memory space including a first region and a second region, the first region being a simulated memory space of the first memory space, the access permissions of memory addresses in the first region being accessible, and the access permissions of memory addresses in the second region being inaccessible; obtaining a second request for accessing the first region; and determining that the second request has encountered an error if the access permissions of the memory addresses indicated by the second request are inaccessible. In this way, when the program requests memory space, an additional segment of memory space is allocated as a protected area, whose access permissions differ from those of a normally requested memory space, which helps to detect corresponding memory errors when the program accesses memory.

The application provides a binary program-oriented data-oriented vulnerability searching method, and belongs to the technical field of computers, and comprises the following steps: inputting test data into a target binary program in a computer and running the target binary program; saving a memory snapshot when the target binary program runs to a vulnerability function where a memory error vulnerability is located; marking test data data of a buffer zone input into the computer in the memory snapshot as a pollution source; and executing the target binary program with a first instruction of the vulnerability function as a starting point. If any memory copy Gadget that copies data in the memory to other memory positions and any address write Gadget that writes data in the memory are found in the process of executing the target binary program, it is determined that the current memory error vulnerability is sufficient to be upgraded to a data-oriented vulnerability DOP for exploitation. The method can analyze data-oriented vulnerability availability of a binary program.

The application provides a memory error processing method, system, device, storage medium and program product. An operating system kernel comprises a hardware error source driver, a first driver and a second driver. The second driver is used for processing a memory error processing task of an extended memory area. The first driver is used for processing a memory error processing task of a standard memory area. The first driver is used for distributing the memory error processing task of the extended memory area to the second driver. The method comprises the following steps: obtaining a memory error processing task of a target page distributed by the hardware error source driver; the target page has a memory error; if the target page is a memory page of the extended memory area, calling the second driver to perform error processing on the target page. The method improves the reliability of error processing.

The present application belongs to the technical field of memory test, and specifically provides a memory error causing downtime problem processing method, device, equipment and medium, the method comprises the following steps: detecting memory error and distinguishing error type; judging whether the error type is a memory correctable error; if yes, sending fault information to BMC and recording fault log; otherwise, performing degradation processing on the current memory error; judging whether the number of degraded memory errors reaches the corresponding module register threshold; if yes, performing physical isolation processing on the faulty memory; otherwise, sending memory degradation error log to BMC. The combination of fault memory isolation and fault degradation isolates a single fault memory, the main purpose is to make the system not down, and does not affect the normal business operation, but at the same time, the memory log situation can be clearly recorded, which is convenient for operation and maintenance to handle in time.

This application discloses a memory error correction method, server system, electronic device, and storage medium, relating to the field of storage software technology. The method includes: when a memory generates a currently uncorrectable error, based on the evolution law of uncorrectable errors, extracting a set of target historical correctable errors from a historical error record file that match the memory address of the currently uncorrectable error, attempting to correct the set of target historical correctable errors; once the set of target historical correctable errors is successfully processed, the currently uncorrectable error has the opportunity to transform into a derived correctable error, thus changing the root cause or pattern of the currently uncorrectable error. At this time, the memory error handling mechanism can play a role again. Subsequently, the derived correctable errors are corrected, fundamentally resolving the currently uncorrectable error. This solves the problem that when uncorrectable errors occur in memory, multiple errors cannot be effectively corrected, leading to data loss and decreased server system stability.