86 results about "Bad memory" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

The invention relates to memory error correction, in particular to an ECC check single-bit error correction system in a DDR (Double Data Rate), which comprises a DRAM (Dynamic Random Access Memory) scanner, periodically performs address read traversal operation on a DDR particle DRAM, timely finds a single-bit error of data in the DDR particle DRAM by inquiring an ECC check state in a DDR controller DDRC, and performs correction processing on the single-bit error, so that the error correction efficiency is improved. The error is prevented from being evolved into an uncorrectable multi-bit error; the DDR controller DDRC is used for converting the AXI interface signal into a corresponding DFI interface signal, outputting the DFI interface signal to a DDR physical layer DDR PHY, carrying out ECC verification on read-write data, and storing an ECC verification result to a register, so that a DRAM scanner inquires an ECC verification state; according to the technical scheme, the defects that in the prior art, the processing speed is low, data errors are not found in time, and more CPU resources are occupied can be effectively overcome.

The embodiment of the invention discloses a system startup memory detection method and device, equipment and a storage medium, and the method comprises the steps: calculating the maximum value of a Hypervisor early virtual address mapping range according to the initial address of Hypervisor operation before a final page table takes effect; when the dynamic allocation pool is utilized to allocate the memory page, determining a virtual address range of the allocated memory page by utilizing a base address of the allocated memory page, and detecting whether the virtual address range of the allocated memory page exceeds a maximum value of a Hypervisor early virtual address mapping range or not; and when the maximum value of the Hypervisor early virtual address mapping range is exceeded, outputting an error prompt, and returning a memory error. Compared with a traditional estimation mode, the probability that estimation is inaccurate due to the fact that dynamic allocation changes is reduced, the memory errors can be accurately detected in advance before the system crashes, and a developer can conveniently locate the reason of crashes.

The invention discloses a memory error correction method, a server system, electronic equipment and a storage medium, and relates to the technical field of storage software, and the method comprises the following steps: under the condition that a memory generates a current uncorrectable error, based on an uncorrectable error evolution rule, correcting the current uncorrectable error; a group of target historical correctable errors matched with the memory address of the current uncorrectable error is extracted from a historical error record file, the group of target historical correctable errors are tried to be corrected, and once the group of target historical correctable errors are successfully processed, the current uncorrectable error has an opportunity to be converted into a derivative correctable error, so that the correctable error cannot be corrected. According to the method, the source or mode of the current uncorrectable error is changed, at the moment, the memory error processing mechanism plays a role again, and then the derivative correctable error is corrected, so that the current uncorrectable error is fundamentally solved, and the problem that the multi-bit error cannot be effectively corrected when the uncorrectable error occurs in the memory is solved. And the problems of data loss and server system stability reduction are solved.

A host server computer with an uncorrectable memory error can be repaired without a reboot operation. While initially booting a hypervisor, a special software Application Programming Interface (API) can be loaded between a BIOS System Management Mode (SMM) code and the hypervisor. Once the host server computer is booted and a number of virtual machines are executing, a memory error (e.g., uncorrectable error correction code (UECC)) can occur. In response, the hypervisor calls into the special software API identifying the defective memory rows that the BIOS needs to repair. The BIOS starts a soft Post Package Repair (PPR) process on those rows and gives back control to the hypervisor. When the repair is completed, the hypervisor loads a scrubbing virtual machine and validates that the memory is corrected. After the repair is validated, the hypervisor allows the available partition to take a new customer instance.

The invention discloses a memory fault management system and method, a server and electronic equipment, and relates to the technical field of computers, the memory fault management system comprises a processing circuit of a hardware memory, a hardware layer and a processor are arranged on the processing circuit, and the processor is further divided into a kernel layer, a user layer and an input and output layer. Through cooperative work of the hardware layer and each software layer, hierarchical detection, classified processing and automatic isolation of memory error data are realized, and server downtime caused by memory fault error data is effectively prevented. And meanwhile, through a linkage mechanism of a kernel mode and a user mode and in combination with visual display, the monitorability and maintainability of memory errors are enhanced, operation and maintenance personnel can quickly position and repair problems conveniently, and the operation and maintenance cost of the system is reduced.

Memory with enhanced fail tracking, and associated systems, devices, and methods, are disclosed herein. In one embodiment, a memory device comprises a memory array and fail tracking circuitry. The fail tracking circuitry can include a counter and a plurality of memory slots and can be configured to, for each memory row of a plurality of memory rows in a memory region of the memory array, (a) count errors detected in data read from the memory row to determine an error count, and (b) store the error count and address information for the memory row in a memory slot of the plurality of memory slots. In some embodiments, the fail tracking circuitry can be configured to count the errors and store the error counts during error check and scrub operations of the memory device (e.g., to identify the worst memory rows in the memory region for post-package repair operations).

The invention discloses a memory error processing method and system, electronic equipment and a storage medium. The method comprises the steps that in response to restarting of a target operating system, memory error information is collected, and the memory error information is used for recording historical memory errors generated before crash of the target operating system; persistently storing the memory error information to obtain a storage result; and isolating the error memory based on the storage result so as to reject the application program in the target operating system to apply for or access the error memory. According to the method, the technical problems of high system downtime frequency and poor stability of a memory error isolation mode in related technologies are solved.

The embodiment of the invention provides a fault prediction method, a fault processing method and a fault processing system.The fault prediction method comprises the steps that a memory error event of a cloud server is obtained, and the memory error event has corresponding event information; based on the event information, extracting a first distribution feature of the memory error event in a basic storage unit of the cloud server memory; determining a second distribution feature of the memory error event in the instance according to the first distribution feature and an affiliation relationship between the basic storage unit and the instance; and on the basis of the second distribution feature, a fault prediction model is utilized to determine a predicted fault instance, and the fault prediction model is obtained based on sample distribution feature training of the sample memory fault event on the instance. By determining the distribution characteristics of the instance granularity, fault prediction of the instance granularity is realized based on the distribution characteristics of the instance granularity, and the refinement degree of fault prediction is improved.

The invention relates to memory error correction, in particular to an ECC (error correction code) check single-bit error correction system of a DDR (double data rate) controller, which comprises the following steps of: generating a command Cmd1, an address Addr1 and write data Wrdata1, and receiving read data Rddataout, a read address Rdaddrout and a single-bit error enable signal 1bit; the ECC single-bit error corrector is used for receiving a single-bit error signal 1bit, read data Rddataout and a read address Rdaddrout, and generating a command Cmd2, an address Addr2, write data Wrdata2 and a single-bit error enable signal 1bit which are required by ECC single-bit error correction, and the command Cmd2, the address Addr2, the write data Wrdata2 and the single-bit error enable signal 1bit are used for correcting the ECC single-bit error; according to the technical scheme provided by the invention, the defects of relatively low processing speed, relatively high delay and relatively large CPU (Central Processing Unit) resource occupation can be effectively overcome.

The invention provides a memory error simulation method and device based on a satellite-borne intelligent computing system, a medium and a simulator, and relates to the technical field of satellites. The method comprises the following steps: inputting a deep learning neural network engine into a deep learning reasoning program of a satellite-borne intelligent computing system; executing a deep learning reasoning program to read a process page table; based on the DRAM standard file, the DRAM mapping file and the address mapping relation, determining a memory active area of the deep learning neural network engine in the virtual memory model; performing construction processing on the memory active area, constructing an error injection space represented in a bitmap tree form, and determining an error information injection position in the error injection space according to particle flipping error model information and a Monte Carlo random algorithm; and performing reverse translation processing on the physical address in the virtual memory model, and determining a target virtual address of the deep learning reasoning process. And a single-particle upset memory error and a multi-particle upset memory error caused by space radiation can be effectively simulated.

In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.

The invention discloses a method and a system for protecting privacy of source codes in memory error detection, belongs to the technical field of computer software security, and particularly relates to a technology for protecting confidentiality of the source codes in a third-party memory error analysis process of software. According to the method, a debugging information minimization processing system DIREDUCER is constructed, a selective deletion and type minimization technology is utilized, on the premise that complete source codes are not exposed, necessary debugging information used for memory error detection is effectively reserved, and dual guarantee of source code privacy and memory error detection effects is achieved. According to the method, the debugging information in the non-stripping binary file is compressed to be within 10% of the original volume, and the recognition capability of an analysis tool on the problems such as memory leak, buffer overflow and overhanging pointers is not remarkably reduced. Experimental results show that the method has good adaptability and expandability in actual deployment, is suitable for various debugging tools and binary analysis frameworks, and has wide application prospects and practical values.

The invention discloses a memory error processing method and system, electronic equipment, a computer readable storage medium and a computer program product, and relates to the technical field of computers. The method is applied to an operating system kernel of a target computer architecture and comprises the steps that in response to a reading event corresponding to a memory error reading mechanism, memory error information is read from a target register, and the memory error reading mechanism is obtained according to instruction set type configuration corresponding to the target computer architecture; the memory error information is obtained by detecting a hardware module corresponding to the target register in a process of accessing a memory space; the memory error information is analyzed, an analysis result is obtained, and the analysis result is used for representing the memory position corresponding to the hardware module with the memory error in the target computer architecture. According to the method and the device, the technical problem of low collection integrity of memory error information in a firmware priority scheme in the related technology is solved.

Systems and methods include an Information Handling System (IHS) that is adapted to provide memory diagnostics for use in identifying replaceable memory modules that are starting to fail. Upon initialization of an IHS that includes replaceable memory modules, a plurality of memory device drivers are loaded for use in accessing the replaceable memory modules. Each memory device driver is adapted to support a diagnostic API (Application Programming Interface). The IHS detects memory errors resulting from attempts throughout the IHS to access the replaceable memory modules. A memory address associated with the detected memory error is determined and the diagnostic API of a memory device driver is used to identify a specific replaceable memory module as the source of the memory error.

The invention provides a memory error processing method, system and device, a storage medium and a program product, an operating system kernel comprises a hardware error source driver, a first driver and a second driver, and the second driver is used for processing a memory error processing task of an extended memory area. The first driver is used for processing a memory error processing task of a standard memory area and distributing a memory error processing task of an extended memory area to a second driver, and the method comprises the following steps: acquiring a memory error processing task of a target page distributed by a hardware error source driver; memory errors exist in the target page; and if the target page is the memory page of the extended memory area, calling the second driver to carry out error processing on the target page. According to the method, the reliability of error processing is improved.

The invention provides a high-efficiency memory repair system and method based on a pooling memory. The method comprises the following steps: a memory test module performs UCE error address detection on a memory bank by taking cache as granularity; the management module is used for converting the memory error address into a memory page address to which the memory error address belongs, and issuing a repair command for the memory page address; the address routing module replaces and adds a memory page address into a routing table by utilizing a routing table look-up algorithm according to the repair command so as to finish address repair, performs corresponding address conversion according to a repair state of an accessed host memory address, and routes the address to a port where the memory bank or the out-of-band storage module is located; and the out-of-band storage module is an out-of-band memory pool independent of the system memory pool and is used for repairing the damaged memory by taking the memory page as the granularity. According to the method, the effects of improving the utilization efficiency and compatibility of the memory and enhancing the RAS system of the memory are achieved through the high-efficiency memory repair system which is provided with the out-of-band memory module and takes the memory page capable of being dynamically configured as the granularity.

The application provides a memory fault positioning method and related device, and relates to the technical field of computers. The memory fault positioning method can comprise: when reading data from a memory, determining the position of a fault in the memory for a memory error; the position of the fault in the memory comprises some or all of the following: a faulty memory bank, a faulty memory column, a faulty memory particle, a faulty storage array, a faulty storage unit, a faulty row in a storage array, a faulty column in a storage array, a faulty bit, a faulty input / output channel, a faulty reading unit or a faulty sub-channel. The memory fault positioning method provided by the application can position faults at various granularities and accurately position the position of the fault in the memory, which is conducive to quickly repairing the memory fault.

The present disclosure includes apparatuses, methods, and systems for memory maintenance operations. An embodiment includes a memory having a plurality of groups of memory cells, where no data is stored in one of the plurality of groups of memory cells and data is stored in all other of the plurality of groups of memory cells; and a controller coupled to the memory and having circuitry configured to: determine that one of the plurality of groups of memory cells in which data is stored is a bad group of memory cells; recovering the data stored in the group of bad memory cells; programming the recovered data to the one of the plurality of groups of memory cells in which no data is stored; and retreating the group of bad memory cells.

Embodiments of the present application provide an error repairing method, device and equipment and a storage medium, the method comprising: collecting memory errors existing in a system, configuring a value of a target option in an active management technology (AMT) when it is detected that the memory errors meet preset conditions, calling a target callback function through the value of the target option to execute AMT testing, obtaining a test log corresponding to the AMT testing, storing the test log in a pre-allocated memory space, and determining an error repairing mode corresponding to the memory errors according to the test log. Embodiments of the present application can execute AMT testing under a system, avoid the problem that AMT testing needs to be restarted, selectively execute AMT testing and repair errors for memory errors generated in the system, and do not need to obtain logs through a serial port, thereby reducing dependence on the serial port and enhancing stability of log data acquisition.

Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed.

When it is determined that a first super memory block among a plurality of super memory blocks satisfies an exchange condition, the storage device may exchange a first memory unit in the first super memory block with a second memory unit included in a second super memory block among the plurality of super memory blocks. In this case, the first memory unit is a bad memory unit and the second memory unit is a normal memory unit.

The application discloses a C / C++ post-release re-reference dynamic detection method based on pointer dereference insertion, and when software testing is performed, a traditional Address Sanitizer cannot detect logical errors of address legality; the application realizes dynamic detection of pointer reuse memory errors through data flow analysis and insertion of GetElementPtr instructions.

The application provides a high-efficiency memory repair system and method based on a pooling memory, which comprises a memory test module for detecting UCE error addresses of a memory bank with cacheline as a granularity; a management module for converting memory error addresses into memory page addresses, and issuing repair commands for the memory page addresses; an address routing module for replacing and adding the memory page addresses into a routing table by using a routing lookup table algorithm to complete address repair, and for performing corresponding address conversion and routing to a port where the memory bank or the out-of-band storage module is located according to a repair state of a host memory address accessed; and an out-of-band storage module for repairing damaged memory with memory page as a granularity. The application achieves the effects of improving memory utilization efficiency and compatibility, and enhancing a memory RAS system by using the out-of-band storage module and the high-efficiency memory repair system with dynamically configurable memory page as a granularity.

Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error / alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.

This application discloses a method, apparatus, storage medium, and electronic device for repairing server memory, relating to the field of artificial intelligence technology. The method includes: determining first resource information corresponding to repair resources in the server, the first resource information indicating the state of resources in the server that can be used to repair memory errors; searching for a target rule in a rule lookup table based on the first resource information and first error information of the server memory, the first error information indicating errors occurring in the server memory within a preset period, the rule lookup table indicating the correspondence between the first resource information, the first error information, and reference rules, the reference rules including the target rule; determining a target threshold based on the target rule and the first error information; and repairing the server memory using repair resources when the first error information and the target threshold meet preset repair conditions. This solves the technical problem of low resource utilization in related server memory repair methods.

The application relates to a method for performing memory safety dynamic analysis on a program containing specific sentences. The method comprises the following steps: selecting a project directory or a single source code file to be instrumented; preprocessing the source code, replacing macro calls with the content in the macro definition, and commenting out the original macro call; generating a symbol table and an abstract syntax tree of the source code by using a compiler; traversing all nodes in the abstract syntax tree, performing static analysis on the source code, and modifying the source code for sentences that cannot be processed, and then re-instrumenting the source code; traversing all nodes in the abstract syntax tree, performing different instrumentations on the source code according to different node types, compiling the instrumented project directory or file by using a compiler, generating an executable file on a target system, and running the executable file, performing memory error detection on the program containing specific sentences, and reporting the position of the source code corresponding to the error. The method avoids the problems of instrumentation failure and the failure of correctly compiling the program after instrumentation.

Techniques are disclosed relating to improving memory reliability. In some embodiments, an apparatus includes memory circuitry and tracking circuitry that implements multiple tracking circuit entries. Control circuitry may track, using multiple uncorrectable error (UE) tracking circuit entries, detected uncorrectable errors associated with multiple respective memory locations, where the UE tracking circuit entries include a source field that identifies a source of a given UE.

A method for dynamically enhancing the memory error correction ability, the method comprising: obtaining and transmitting memory data to a pool controller; establishing a memory status table according to the memory data; determining a target area in a leaf switch that needs ECC enhancement, and calculating the size of the parity space required for the ECC enhancement; and selecting a target area corresponding to the size of the parity space to store the newly added parity data after the ECC enhancement. The present invention also provides an electronic device, which provides an ECC function for a memory without an ECC function, or dynamically enhances the ECC strength for a memory with insufficient ECC error detection strength.

A data storage device includes a memory block relinking system. The memory block relinking system identifies memory blocks that have been identified as grown bad blocks. The memory block relinking system analyzes the memory blocks that have been identified as grown bad blocks to determine whether a sub-block of the memory block is salvageable. To determine whether the sub-block is salvageable, the memory block relinking system executes one or more operations on the sub-block. If the operation fails, the sub-block is retired. If the operation is successful, the memory block relinking system identifies the sub-block as a relinking candidate. The memory block relinking system logically links the sub-block that was identified as a relinking candidate with one or more other sub-blocks that were previously identified as relinking candidates to form a metablock.