416 results about "Cpu load" patented technology

Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and / or power consumption).

A video codec for real-time encoding / decoding of digitized video data with high compression efficiency, comprising a frame encoder receiving input frame pixels; a codec setting unit for setting and storing coding setting parameters; a CPU load controller for controlling desired frame encoding time and CPU loading; a rate controller for controlling frame size; a coding statistics memory for storing frequency tables for arithmetic coding of bitstream parameters and a reference frame buffer for storing reference frames. The frame encoder comprises a motion estimation unit, a frame head coding unit, a coded frame reconstruction and storage unit and a macroblock encoding unit. The macroblock encoding unit provides calculation of texture prediction and prediction error, transforming texture prediction error and quantization of transform coefficient, calculation of motion vector prediction and prediction error and arithmetic context modeling for motion vectors, header parameters and transform coefficients. The codec also includes a deblocking unit for processing video data to eliminate blocking effect from restored data encoded at high distortion level, which may be a part of encoder or decoder, an internal resize unit, providing matching downscaling of a frame before encoding and upscaling of decoded frame according to the coding setting parameters, and a noise suppression unit.

A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.

Provided is a multicast distribution system which can perform a multicast distribution by selecting a communication path satisfying a communication feature required by a multicast group. A distribution source router (Rs) performs a multicast distribution to routers (R1 to R5) constituting a multicast group based on an application via a mesh virtual network connected to a plurality of routers. When the CPU load ratio and the multicast group communication feature exceed threshold values, the distribution source router updates the number of branches and the depth of the multicast tree which distributes a packet from the router and starts reconfiguration of the multicast tree. When reconfiguring the multicast tree, the distribution source router references a path feature of the mesh virtual network, selects a communication path having a sufficient path feature with a higher priority, and generates a routing table based on the multicast tree.

A biometrics authentication device uses biometrics information to perform individual authentication. Primary and secondary verification of biometrics characteristic data from an image capture device are performed by a control unit and IC card. The biometrics character data is scrambled and transmitted between devices. The second registration data which is more important to authentication is stored within the IC card, and first registration data is registered in the IC card in a scrambled state. Security is improved, and moreover the load on the CPU of the IC chip in the IC card is reduced.