245 results about "Dynamic power dissipation" patented technology

A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.

The invention relates to a gate driving circuit and a display device. The gate driving circuit comprises multiple levels of driving circuit units connected in series. Each level of units comprises an inputting module for providing threshold voltage of a driving module, a driving module for responding to the threshold voltage and for sending a first clock signal to a signal outputting interface, a discharging module for responding to an output signal or a clock signal of an adjacent level and for coupling a control terminal of the driving module to a first voltage source, a clock feedthrough inhibiting module for stablizing the potential of the control terminal of the driving module under the control of the clock signal and the output signal of the adjacent level, and a low level maintaining module for stablizing the output signal at the potential of the first voltage source under the control of the clock signal. The driving circuit unit, gate driving circuit and display device provided by the invention employ single driving tube to realize the fast pull-up and pull-down of the output signal with sequential coordination, reducing the delay time of the rise and fall of the output signal at a low temperature, and employs the clock feedthrough inhibiting module to stablize the gate potential of the driving tube, reducing the corresponding dynamic power consumption.

The invention provides a system power consumption automatic control method, which aims at a server or a group of computers to define a target power consumption value, timely adjusts a frequency control system of a CPU (computer processing unit) to run under the target power consumption value through a power consumption control management module, and achieves the purpose of controlling the power consumption. The power consumption control management module comprises an IPMI management control module, a power management module provided with a PMBUS communication bus, a dynamic power consumption node management module, a power management module, a management control platform, a BMC management module and a power consumption management module for BIOS and an operating system. The method of the invention is based on the flexible extension properties of the modular components, and each module as a modular component in the system can carry out flexible configuration, thereby reducing the complexity of the system management; moreover, the method covers the shortage that a traditional network server which takes computer resources as the core can't automatically adjust a power value set in advance, and enables the servers to be more applicable to the complex high performance commercial application fields which save more energy at present, thereby having broad development prospect.

An integrated circuit may have separate power control for a number of different functional units. Ancillary to some of the functional units may be an activity detector and power control unit which monitors input to its functional unit to determine when the functional unit will be inactive. When an activity detector and power control unit determines that a particular functional unit is or will be inactive, it may disable power to its functional unit while the functional unit is inactive. When activity detector and power control unit determines that activity will resume for its functional unit, it enables power to its functional unit. Thus, the activity detector and power control unit for each such functional unit functions to control power to its respective functional unit so that during periods of inactivity, inactive functional units are powered down to reduce the overall static and/or dynamic power consumption for the integrated device.

Various embodiments of methods and systems for dynamically adjusting a peak dynamic power threshold are disclosed. Advantageously, embodiments of the solution for peak dynamic power management optimize a peak dynamic power threshold based on estimations of real-time leakage current levels and/or actual power supply levels to a power domain of a system on a chip (“SoC”). In this way, embodiments of the solution ensure that a maximum amount of available power supply is allocated to dynamic power consumption for processing workloads at an optimum performance or quality of service (“QoS”) level without risking that the total power consumption (leakage power consumption+dynamic power consumption) for the power domain exceeds the power supply capacity.

The invention relates to a dynamic voltage frequency adjustment method in the power management technology, which comprises steps: collecting different hardware signals; writing a hardware dynamic voltage frequency adjustment controller and a corresponding register of a CPU loading log; reading CPU loading log information via an operating system/software drive, and inputting the information into an interface module of the operating system/software drive after analyzing; and reading dynamic processing temperature compensation, the hardware dynamic voltage frequency adjustment controller, the information processed by the interface module of the operating system/software drive; outputting to a corresponding frequency adjustment and voltage adjustment unit via related algorithm analysis, so as to complete adjusting system real time dynamic voltage frequency. The invention adjusts working frequency according to system performance demands, and correspondingly reduces system working voltage and reduces dynamic power dissipation. The invention greatly improves shortcomings of short service life of the battery, bad system stability and reliability brought in by the traditional simple power management technology. The invention can use various embedded system devices such as the portable multimedia recording and playing device, and smart phone.

A low-power-consumption source driver for a liquid crystal display is provided. Morethan one middle voltage level for the level shifter and the output buffer is provided, in addition to the power supply voltage level VDD and the ground level GND, to provide different voltage levels for image data of different polarities. Hence, amplitude of the operational voltage of the level shifters and the analog circuits with different polarities can be reduced. It also can reduce the amplitude of the operational voltage of the level shifter and can reduce significantly the dynamic power consumption of the level shifter and the DAC. Because the voltage amplitude of the circuit is reduced and a low-voltage tolerated device can be used, so that the present invention can further reduce the cost of the circuit.

The invention relates to a design method of a dynamic multi-clock AHB bus with low power consumption used for SOC. The method adopts a multi-clock gating register to realize the control of clock signals of each module; when a certain module is needed to work, a corresponding grating signal is opened so as to lead the module to work normally; otherwise, the grating signal is closed, the clock does not work and then the dynamic turning of a logic gate can be reduced so as to achieve the purpose of reducing the system dynamic power consumption; moreover, an AHB-AHB bridge is adopted and a plurality of AHB buses can be adopted and then the high-speed and low-speed devices all can be connected with the different AHB buses; the AHB buses are mutually connected through the AHB-AHB bridge; and the clock frequency of certain modules can be reduced so as to achieve the purpose of reducing the dynamic power consumption.

An apparatus measures a dynamic power consumption in each of component devices at a time intervals and subtracts the sum of the dynamic power consumptions from a predetermined maximum value to obtain a dynamic margin. When a request for connecting an emergency device to a power supply is issued, the apparatus compares the rated power consumption in the emergency device with the dynamic margin. If the rated power consumption in the emergency device exceeds the dynamic margin, the apparatus selects, as a disconnectable device, a component device having an individual margin calculated by subtracting the dynamic power consumption from the rated power consumption is greater than an excess of power amount over the dynamic margin of the rated power consumption in the emergency device and the lowest priority. The apparatus issues an instruction to power the emergency device if the rated power consumption in the emergency device is less than or equal to the dynamic margin, issues an instruction to power off the disconnectable device if the rated power consumption in the emergency device exceeds the dynamic margin, and issues an instruction to power on the emergency device after the power-off of the disconnectable device is confirmed.

The invention discloses a method for testing dynamic power consumption of servers, and belongs to the field of tests for power consumption of servers. The method includes particular steps of 1, constructing SPECpower test platforms and preparing test environments; 2, running SUT (system under test) ends and CCS (central control station) ends; 3, carrying out SPECpower tests on the SUT ends and the CCS ends and running scripts for reading data of power consumption of various components; 4, collecting test results after the tests are completed and processing and analyzing the test results. The method has the advantages that the shortcoming that data of dynamic power consumption of different components of integral machines under different load conditions cannot be acquired by PTU (parallel transmission unit), memtest, IOmeter test tools and the like can be overcome, the accuracy and the validity of the test data can be improved, and the conversion efficiency of power sources further can be evaluated when different types of power are outputted by the power sources; the method for testing the dynamic power consumption of the servers is simple in operation and high in automation degree and practicality, labor can be saved, the accuracy of the data of the dynamic power consumption of the various components of the servers can be effectively guaranteed, and the method is an extremely effective method for testing the dynamic power consumption of the various components of the servers.

The invention discloses a method and a device for designing a standard cell library. The method comprises a step of designing a common standard cell, and also comprises a step of designing a double-edge flip-flop cell, and the step of designing the double-edge flip-flop cell comprises: when determining the type of the standard cell, adding the double-edge flip-flop cell to the standard cell type; designing a schematic diagram of the double-edge flip-flop cell; and designing a diagram of the double-edge flip-flop cell. A mold of the double-edge flip-flop cell is established, and the method for establishing the mold comprises the following steps of: establishing a rising edge comprehensive library and a falling edge comprehensive library for the double-edge flip-flop; and establishing a double-edge flip-flop simulated library for the double-edge flip-flop. The invention also discloses a method and a device for designing an integrated circuit. Due to the method and the device, the rising edge and the falling edge for each jump of the clock signal can serve the logical function of a chip, so that the jumping frequency of the clock, needed to complete the same logical function, is reduced, and the dynamic energy consumption of the circuit is also lowered.

The invention relates to an energy consumption optimization method for a fixed priority periodic task of a hybrid critical system, the method comprising the following steps: establishing a hybrid critical periodic task model comprising a plurality of hybrid critical periodic tasks; determining priority of hybrid critical periodic tasks by using the critical hierarchy partitioning method; calculating the lowest feasible speed S of hybrid critical period task scheduling; calculating an idle time ST generated by a task of a high critical level in a low mode, and determining an execution speed Siof the processor by using the idle time, wherein the low level critical tasks and high level critical tasks are always executed at speed Si in low mode, and the high critical level tasks are executedat maximum processor speed with extra load in high mode; using dynamic power management technology to reduce processor power consumption. The method of the invention effectively reduces the system energy consumption by utilizing the idle time generated by the high-critical-level tasks and the dynamic power consumption management technology.

The invention discloses a digital type electric energy meter power consumption measuring device and method. An optical fiber data communication interface is adopted to communicate with a measured digital type electric energy meter in real time, in a 'measuring mode' and a 'standby mode' of the digital type electric energy meter, voltage and current signals of a power supply loop of the measured digital type electric energy meter can be acquired in real time, the real-time power consumption value of the measured digital type electric energy meter in the 'measuring mode' and the 'standby mode' can be accurately analyzed by using a rapid Fourier frequency domain conversion technique, and whether the power consumption meets relevant technical requirements can be judged. Compared with a method that only the static power consumption of the electric energy meter is measured by using an ordinary multimeter, the method is relatively high in accuracy, complex wiring and electric shock hazard are avoided, the measuring process is full-automatic, the static power consumption and the dynamic power consumption can be measured in real time, the electric energy quality of an alternative-current power supply of the measured digital type electric energy meter is effectively evaluated, and the energy conservation and the reliable operation of intelligent substation equipment are ensured.

The invention relates to a charge pump circuit with low power consumption. The charge pump circuit comprises a multiphase clock generation circuit, a charge transmission transistor, a substrate adjustment circuit of the charge transmission transistor and a capacitor element, wherein one end of the capacitor element is connected to a serial connection joint of the charge transmission transistor, and the other end is connected to clock signals generated by the multiphase clock circuit; the plurality of clock signals output by the multiphase clock generation circuit have different phases, and each clock signal is connected to the corresponding capacitor element so that the charge pump only charges one capacitor when working at different moments. The invention can effectively avoid larger transient current and transient power consumption caused by charging the plurality of capacitors in the traditional charge pump circuit at the same time, and thereby the dynamic power consumption and power peak current are reduced when the charge pump works.

The invention provides a storage unit circuit with an adaptive leakage current cutoff mechanism, which is a dual-port read-writing sub-threshold storage unit circuit. The circuit comprises a first inverter and a second inverter which are connected in a cross coupling way; the two inverters are connected between complementary bit lines through an equalizer pipe; and the grid end of the equalizer pipe is connected with an enhanced word line. The invention overcomes the defects of the prior art and provides the sub-threshold storage unit circuit with low power consumption and high robustness; and the sub-threshold storage unit circuit can reduce leakage power consumptions in dynamic operation and static operation while the leakage power at the same time on the premise of not increasing dynamic power consumption or reducing performance, and can balance each index of a storage unit so as to optimize system performance.

A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption.

The invention discloses a novel 12-tube SRAM (Static Random Access memory) unit circuit capable of simultaneously increasing read noise tolerance and writing margin, and the novel 12-tube SRAM unit circuit can eliminate a partial-select problem and solve a read partial-select problem and a writing partial-select problem, a stability problem cannot be caused, and additionally, no additional power is consumed. Experiments measure that compared with a traditional 6T unit, the read dynamic power consumption and the writing dynamic power consumption of an array with the total number of 128 are respectively reduced by 81.3% and 88.2% when a column decoding unit (CMUX) is 4; additionally, according to the circuit, the read noise tolerance is greatly increased, so that the read noise tolerance is similar to the noise tolerance in a hold mode and reaches 2.3 times of that of the traditional 6T unit; in addition, according to the circuit, a feedback structure of a phase inverter is interrupted, so that the writing margin is increased and reaches 1.41 times of that of a traditional 6T SRAM unit.

A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

The invention discloses a router power model on the basis of a network-on-chip, which simplifies router operations into four power dissipation links namely write-cache, read-cache, a bestride switch and a bestride link according to the power dissipation specific weight and attributes dynamic power dissipation to bit flipping activities which are triggered when a present data film arrives, and numbers the power dissipation by the bit flipping activities to obtain the router power model. Considering that the implementation complexity which is required by the network-on-chip requirements to the power model is as low as possible, the invention can adopt the statistical average in stead of the instantaneous sampled value to obtain a power dissipation simplified model. Hardware implementation methods of two power dissipation models are given out aiming at a five-channel rooter structure, the simplified model is introduced to a self-adaptive routing algorithm, which realizes the power dissipation distribution optimization of the network-on-chip. The router power model which is proposed by the invention has low algorithm complexity and simple realization, is suitable for network-on-chip, and can be used in research and application in the aspects of power dissipation performance statistics, the power dissipation distribution optimization, thermal protection and the like.

The invention discloses a design method of a high speed register with low power consumption and high capacity. On the one hand, the invention prevents the invalid visiting to the high speed register by beforehand obtaining the information whether the high speed register is hitting and reduce the dynamic power consumption; on the other hand, the invention divides the storing district in to a number of physical blocks and only visit 1/n of the total size under the hitting status of the high speed working-storage section, the dynamic power consumption is 1/n of the original situation. The invention saves the switching time of the dummy address to the physical address, reduces the extra hardware spending brought by the address switching and reduces the whole power consumption of the system byadopting the dummy address to search the high speed register. The invention can greatly reduce the power consumption of the high speed register and greatly elevate the whole capacity of the highly embedding type processor being utilized, which has the advantages of low hardware cost and simple design realization.

An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shifter circuits. For some embodiments, existing multiplexing circuit architectures provided within logic resources of various logic blocks of the configurable IC device may be used as level shifter circuits to increase the voltage swing of signals received into the blocks from the interconnect signal lines, and modified multiplexing circuit architectures provided within the logic resources may be used to reduce the voltage swing of signals output from the logic blocks onto the interconnect signal lines.