149 results about "Dynamic power dissipation" patented technology

The invention discloses a domestic heterogeneous chip dynamic power consumption cooperative scheduling method oriented to a vehicle-mounted environment, and aims to solve the problem of system energy efficiency optimization caused by strict limitation of power supply and heat dissipation resources, dynamic mixing of calculation tasks and unique power consumption characteristics of domestic chips in the vehicle-mounted environment. The method is based on a vehicle-mounted heterogeneous computing platform comprising a domestic central processing unit, a field programmable gate array and a memory, and is realized through a closed-loop scheduling process executed by the central processing unit. According to the method, global, dynamic and collaborative power consumption management of domestic heterogeneous chip resources is realized, and the overall energy efficiency and the operation reliability of the system are remarkably improved on the premise of ensuring the real-time performance and the performance of a vehicle-mounted task.

The invention provides a low-power-consumption scheduling method and system for an edge heterogeneous computing unit, and the method comprises the steps: constructing a resource sensing model of heterogeneous hardware, and collecting the performance parameters of a processing unit in real time; establishing a task priority evaluation model, and calculating a task priority by adopting an analytic hierarchy process based on the resource perception model and the task priority evaluation model; designing a collaborative optimization model; based on the collaborative optimization model and by adopting an improved particle swarm optimization algorithm, solving an optimal allocation scheme of tasks in the heterogeneous hardware, and dynamically adjusting the working frequency of the heterogeneous hardware; monitoring states of task execution and heterogeneous hardware in real time, judging whether resource overload or task timeout risks occur in the states or not, and if yes, triggering scheduling scheme updating. According to the method, local optimum is effectively avoided, the solution efficiency and the solution quality are remarkably improved, and the frequency-to-voltage linkage dynamic power consumption regulation and control closed loop is realized by triggering scheduling scheme updating.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

The invention relates to the technical field of electronic timers, in particular to an environment self-adaption low-power-consumption management system and method for an electronic timer, and the system comprises an environment sensing array, a physical state evaluator, a dynamic power consumption strategy generator, a closed loop execution and calibration unit and a self-adaption compensator. According to the method, multi-dimensional environment parameters are dynamically collected, a coupling model representing the relation between frequency deviation and compensation power consumption is constructed, combined regulation and control parameters are generated through multi-target optimization by combining the residual electric quantity of equipment and a timing error accumulated value, hardware execution is driven, operation deviation is monitored in real time, and strategy self-adaptive iterative optimization is achieved through a feedback closed loop. According to the invention, the pain point that the precision and the power consumption of a traditional electronic timer are mutually restricted is effectively solved, and the equipment environment adaptive capability, the endurance time and the full life cycle operation stability are greatly improved.

The invention provides a dual-conversion gain reading circuit, a reading method and an image sensor, and the circuit comprises a comparison module which carries out the pre-comparison of a high-gain photosensitive signal and a ramp signal, so as to obtain a pre-comparison result, comparing the low-gain reset signal, the high-gain reset signal, the high-gain photosensitive signal and the low-gain photosensitive signal with a ramp signal to output corresponding comparison signals; and the counting module selects a counting mode according to the pre-comparison result to count the comparison signals so as to output data signals. A comparison module is used for pre-comparing a high-gain photosensitive signal with a ramp signal, and a counting module is used for selecting a corresponding counting mode for counting quantization according to a pre-comparison result, so that the corresponding counting mode can be adaptively selected according to a voltage difference value between a high-gain reset signal and the high-gain photosensitive signal; therefore, the dynamic power consumption of the counting module is effectively reduced, the overall power consumption of the reading circuit is reduced, and the problem that an existing dual-conversion gain reading circuit is large in dynamic power consumption is solved.

The invention relates to the technical field of wearable equipment and chip power consumption management, and discloses a storage chip low power consumption management method and system for AI glasses, and the method comprises the steps: obtaining multi-application concurrent operation access request data and an instantaneous current change value; according to the access request data, carrying out access request time interval calculation to obtain concurrent access density distribution feature data; according to the instantaneous current change value and the concurrent access density distribution characteristic data, carrying out association binding to obtain access request characteristic data; and performing conflict request identification and risk assessment according to the access request feature data, and performing dynamic power consumption parameter adjustment in combination with real-time power consumption data to obtain a storage chip power consumption distribution scheme. The method can solve the technical problem of low power consumption management efficiency.

The invention discloses a random question number generator and method suitable for a question and answer mode watchdog, and belongs to the technical field of integrated circuit safety. Comprising an on-chip high-frequency oscillation source, an enabling controller, a low-power-consumption controller, a pseudo-random number generator and a random code hopping device. According to the method, an external dog feeding signal is used for triggering, a non-reproducible hopping code value is generated by using different sources of clock sources and physical deviation of signal transmission, a pseudo-random number generator is controlled to operate within a random duration, and a low-power-consumption state is entered after a final random problem number is output and latched. Through hardware-level entropy source enhancement and dynamic power consumption management, the predictable potential safety hazard of the traditional pseudo-random number sequence is fundamentally solved, and the balance of high randomness, high attack resistance and low power consumption is realized at low cost.

The invention discloses a livestock intelligent ear tag and management system, which comprises a Bluetooth AOA positioning module, a UHF RFID module, a sensor module and a dynamic power consumption management unit, and is characterized in that the Bluetooth AOA positioning module realizes centimeter-level dynamic positioning through a base station array, and the dynamic power consumption management unit adjusts the data reporting frequency according to the livestock motion state. The Bluetooth AOA positioning module and the UHF RFID module are dynamically switched and multiplexed in a time division mode, and the limitation of a traditional ear tag on precision, endurance and reliability is broken through through three core technologies of double-frequency cooperation, dynamic power consumption and a glue-pouring-free technology.

A bit line charge sharing precharge circuit is provided that precharges a bit line pair during a charge sharing period in which the bit line pair is isolated from a memory power supply voltage. Prior to the charge sharing period, one of the bit lines in the bit line pair was charged to the memory power supply voltage whereas a remaining one was either fully or partially discharged. Charge thus flows from the charged bit line to the discharge bit line during the charge sharing period to precharge the bit lines for a current read or write operation.

The invention discloses an automatic testing method and device for a water meter module, a medium and a product. In the method, a manipulator is controlled to grab a to-be-tested water meter module and place the to-be-tested water meter module at a test station, and start power consumption characteristic data, sleep power consumption characteristic data and valve control response characteristic data of the to-be-tested water meter module are collected; processing the starting power consumption characteristic data, the dormancy power consumption characteristic data and the valve control response characteristic data to construct an electrical reference portrait; writing a module identity into a nonvolatile memory of the water meter module to be tested; performing function verification on the to-be-tested water meter module to obtain a dynamic function data set; obtaining dynamic power consumption characteristic data, and verifying the dynamic function data set and the dynamic power consumption characteristic data to obtain a consistency verification result; and generating a quality judgment conclusion, and moving the to-be-detected water meter module to a preset area according to the quality judgment conclusion. By implementing the technical scheme provided by the invention, the limitation that a traditional quality inspection method only depends on independent parameter threshold judgment is effectively overcome.

The invention belongs to the technical field of wearable equipment, and discloses a self-powered multi-parameter wearable health monitoring system and a working method thereof, and the system comprises a dual-mode self-powered module which is used for generating and outputting electric energy to a DC-DC voltage stabilization chip; the multi-modal sensor array is used for collecting predetermined various vital sign index information and environmental data; the edge AI processing unit is used for performing AI reasoning according to the various vital sign index information and the environmental data, and generating and outputting a health risk assessment result; the dynamic power consumption management module is used for collecting the input power of the DC-DC voltage stabilization chip and the current power consumption of the system, and generating and sending a power consumption scheduling instruction to the multi-mode sensor array and the edge AI processing unit according to the input power of the DC-DC voltage stabilization chip and the current power consumption of the system; according to the invention, the power consumption management and endurance strategy precision is improved, the phenomenon of insufficient energy supply or waste is avoided, and all-weather, continuous and high-precision health monitoring can be realized.

This invention belongs to the field of integrated circuit testing and semiconductor manufacturing quality control technology, and discloses an integrated circuit final testing method and system based on dynamic power consumption compensation. The method includes the following steps: acquiring power consumption prediction data for each test vector in the test program; querying a lookup table to obtain the expected voltage drop value corresponding to each test vector; performing feedforward pre-compensation on the supply voltage based on the expected voltage drop value before testing; monitoring the actual voltage at the power supply pin in real time during testing; comparing the actual voltage with the target voltage to generate an error signal; performing feedback fine-tuning compensation on the supply voltage based on the error signal; and collecting the actual voltage drop value under each test vector after testing, iteratively updating the expected voltage drop value of the corresponding test vector in the lookup table based on the deviation between the actual voltage drop value and the corresponding expected voltage drop value. This invention can solve the problems of test misjudgment, low yield, and insufficient test coverage caused by IR drop in traditional testing methods.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

The application discloses an AI cluster perception-based dynamic power distribution system of a heterogeneous computing platform, which comprises a data acquisition module, a performance quantization module, a power consumption analysis module and a power distribution module.The data acquisition module acquires the real-time power consumption and utilization rate of each computing unit in the cluster, and forms a heterogeneous unit data set after preprocessing.The performance quantization module obtains the single-resource bottleneck coefficient of each resource type based on the heterogeneous unit data set, and calculates the comprehensive bottleneck coefficient of each unit by constructing an AI-based bottleneck perception space-time network.The power consumption analysis module identifies the critical path unit and the idle unit based on the comprehensive bottleneck coefficient by using a weighted power consumption redistribution algorithm based on critical path perception, and calculates the releasable power consumption factor of the critical path unit and the idle unit to perform optimized distribution in combination with the comprehensive bottleneck coefficient, so that the best target power consumption range of the computing platform is obtained.The power distribution module performs setting operation by calling the underlying hardware power consumption management interface based on the power consumption upper limit value set of different units, so that dynamic power distribution is realized.

The present application discloses a dynamic power consumption management system, comprising: an equalization algorithm circuit, a carrier recovery algorithm circuit, and an IQ imbalance algorithm circuit; an equalization algorithm coefficient update circuit connected to an output end of the carrier recovery algorithm circuit and configured to provide equalization algorithm update coefficients to the equalization algorithm circuit; a carrier recovery frequency offset and phase noise calculation circuit connected to an output end of the equalization algorithm circuit and configured to provide carrier recovery frequency offset and phase noise coefficients to the carrier recovery algorithm circuit; an IQ imbalance algorithm coefficient update circuit connected to an output end of the IQ imbalance algorithm circuit and configured to provide IQ imbalance algorithm coefficients to the IQ imbalance algorithm circuit; a signal-to-noise ratio reporting circuit connected to an output end of the IQ imbalance algorithm circuit and configured to acquire a signal-to-noise ratio of the entire system; and a management circuit configured to determine the equalization algorithm update coefficients, the carrier recovery frequency offset and phase noise coefficients, and the IQ imbalance algorithm coefficients based on the signal-to-noise ratio. The present application can reduce the power consumption of chips.

The invention provides a dynamic power consumption management method and system for portable brain-computer interface equipment and a storage medium, and the method at least comprises the following steps: S1, after the system is electrified and initialized, controlling a main control chip, an electroencephalogram acquisition chip, a first wireless communication module and a second wireless communication module to enter a deep sleep mode; s2, in response to occurrence of at least one preset awakening event, awakening the main control chip; s3, the main control chip generates at least one task to be executed according to the type of the wake-up event and adds the task to be executed into a task queue; s4, the main control chip schedules and executes the tasks in the task queue; and S5, after all tasks in the task queue are executed, the main control chip returns to the deep sleep mode. The system comprises a main control chip, an electroencephalogram acquisition chip, a first wireless communication module and a second wireless communication module. The method has the advantages of obviously reducing the average power consumption of the system, intelligently selecting a wireless transmission path, improving the response efficiency of the system and the like.

The invention relates to the technical field of intelligent power driving in analog integrated circuits, in particular to a novel intelligent power driving chip high-side continuous power supply circuit which comprises a novel charge pump bootstrap power supply circuit and a charge pump capacitor Ccharge. According to the novel charge pump bootstrap power supply circuit, an oscillator is integrated at the control end of a voltage withstanding switch S2A, a clock signal CLK is generated through the oscillator to control on and off of the voltage withstanding switch S2A, meanwhile, the dV / dt state of a floating ground end HS of a charge pump circuit is detected, a dV / dt detection adaptive circuit is matched to generate a control signal of a voltage withstanding switch S1A, and the voltage withstanding switch S2A is controlled to be switched on and off. A high-side continuous power supply circuit is formed by combining charge pump diodes D1 and D2 and a charge pump capacitor Ccharge and continuously supplies power to a bootstrap capacitor Cboot; according to the novel charge pump bootstrap power supply circuit, a high-side integrated level shift circuit in the novel charge pump bootstrap power supply circuit is effectively prevented from working in a high-frequency state, and the dynamic power consumption of the circuit is remarkably reduced while the relatively high power supply efficiency is maintained.

The application provides a space heterogeneous computing resource scheduling method and device based on dynamic power consumption budget, a terminal, a medium and a product. The method is applied to a task initiation device, and the method comprises the following steps: acquiring a current space computing task to be executed, and determining a current dynamic space heterogeneous computing group; acquiring current power consumption budget scores and device capability information of each computing device in the computing group; according to the space computing task, based on the acquired current power consumption budget scores and device capability information of each computing device, one or more optimal computing devices are selected from each computing device by using a multi-objective optimization scheduling algorithm, so that the one or more optimal computing devices execute the space computing task. Through the power consumption budget score and the multi-objective optimization scheduling algorithm, the application effectively avoids that a low power or energy shortage device undertakes a high energy consumption task, thereby significantly reducing energy consumption, prolonging the effective use time of the computing device, and improving stability.

The application relates to the technical field of semiconductor simulation, in particular to a semiconductor device power consumption simulation data analysis method and system, which comprises the following steps: setting a plurality of working scenes and design parameters of a semiconductor device, simulating the semiconductor device under each working scene and each design parameter, obtaining a temperature sensitivity coefficient based on the difference between the junction temperature data and the environmental temperature data of the semiconductor device under any working scene and in combination with the dynamic proportion under the working scene, adjusting the static power consumption data change condition of the semiconductor device under different design parameters, and respectively performing weighted processing on the dynamic proportion adjustment result under the working scene and the change condition of the dynamic power consumption data, so that the difference between the weighted static power consumption change amount and the weighted dynamic power consumption change amount is used to iteratively optimize the design parameters of the semiconductor device. The application effectively reduces the overall power consumption of the semiconductor device and enhances the thermal stability.

The application relates to the technical field of integrated circuits, and discloses a digital auxiliary adaptive zero-crossing detection circuit. The circuit comprises a digital auxiliary comparator module, a digital logic module, a detection discrimination module and a counter module. The digital auxiliary comparator module compares a switch node voltage signal with a power ground signal to generate a first output signal; the digital logic module processes the first output signal to generate a zero-crossing detection signal and control the turn-off of a power tube; the detection discrimination module receives a second output signal of the digital logic module and the zero-crossing detection signal to generate a digital tuning signal; and the counter module receives the digital tuning signal to generate a six-digit digital signal, dynamically adjusts a resistance array in the digital auxiliary comparator module, adaptively adjusts the flip offset of the comparator by changing the resistance value of the resistance array, and thus changes the turn-off timing of the power tube. The application can accurately control the turn-off timing of a synchronous rectification power tube, reduce the reverse current and reduce the dynamic power consumption.

The application relates to the field of data calculation, and relates to a neural network operation method and device, a chip, electronic equipment and a storage medium. The neural network operation method comprises the following steps: acquiring input data and Wk*Hk sub-convolution kernel groups of neural network operation, and entering an operation step; N Wk*Hk*C convolution kernels of the neural network operation are split to obtain N*Wk*Hk 1*1*C sub-convolution kernels, and the N*Wk*Hk 1*1*C sub-convolution kernels are divided into Wk*Hk sub-convolution kernel groups; the operation step comprises the following steps: rearranging the input data according to a data rearrangement mode corresponding to each sub-convolution kernel group to obtain rearranged input data corresponding to each sub-convolution kernel group; the sub-convolution kernel groups and the rearranged input data corresponding to the sub-convolution kernel groups are convolved to obtain convolution results of the sub-convolution kernel groups; the convolution results of the sub-convolution kernel groups are accumulated to obtain an accumulated result, and data located at an effective position in the accumulated result is taken as an output result of the neural network operation. The hardware design overhead, the increase of data memory access and the increase of dynamic power consumption caused by img2col are eliminated.

The invention discloses a low-power-consumption Bluetooth near-field identity recognition device, a dynamic power consumption management method, a hierarchical encryption storage method and a cross-layer collaborative management method, and relates to the field of near-field recognizing.An MCU and a BLE module integrating 4MB Flash form a core, and data communication is achieved through a UART interface; the dynamic power consumption control unit adjusts a power supply strategy according to the working state of the equipment, and controls the broadcast interval of the BLE module and the power mode of the MCU; the hierarchical storage architecture based on 4MB Flash realizes sensitive data isolation through a hardware encryption engine, and supports dynamic partition access permission switching during operation; a near-field identification trigger interface, a configuration parameter read-write interface and a function expansion interface are provided, distance threshold adjustment and power consumption mode switching are supported, breakthrough between low cost and long endurance is achieved through collaborative design of hardware architecture optimization and dynamic power consumption control, and the method is suitable for large-scale deployment scenes and has wide application prospects. And the full life cycle cost of the terminal equipment is obviously reduced.

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-precision low-overhead runtime on-chip digital power meter. The power meter comprises a bit-level agent flipping detection module, a lifting binary tree prediction module, a weight score read-write module, a weight score accumulation module and an average power consumption calculation module. By detecting the activity of the proxy net in the deployed target design, the method adopts binarized input characteristics and a lightweight nonlinear prediction model, and can avoid high-precision redundant calculation while keeping high-precision prediction of dynamic power consumption, thereby accelerating the calculation period and reducing the area overhead. The method has the characteristics of high precision and low overhead, and can monitor the on-chip real-time dynamic power consumption by using efficient hardware resources.

Embodiments of the present description provide an instruction fetching method, a processor, a system-on-chip, and a computing device. The instruction fetching method is applied to an instruction fetch unit of a processor, and the processor further comprises a cache unit, a tightly-coupled memory unit, and a program counter. The instruction fetching method comprises: receiving branch prediction information for a current jump instruction; on the basis of the branch prediction information, determining, from the cache unit and the tightly-coupled memory unit, a current storage unit where the current jump instruction is located; and on the basis of an offset of a current program counter value recorded by the program counter, fetching the current jump instruction from the current storage unit. The timing pressure is reduced, the clock rate of the processor is increased, and the additional dynamic power consumption caused by fetching jump instructions from two branches simultaneously are effectively avoided, thereby improving the performance of the processor when processing non-sequential instructions and the product battery life, and implementing more efficient and energy-saving instruction fetching without sacrificing the processing speed; the present invention is applicable to application scenarios having high requirements for real-time performance and product battery life.

The application discloses a chip bottom layer topology control method and system based on discrete space-time dual mapping, and belongs to the technical field of integrated circuit bottom layer intelligent control. In view of the bottom layer defects of traditional chip hardware and information being split, relying on external driving, architecture being solidified, scheduling being redundant, and lacking self-adaptive evolution capability, the application is based on the original TPS-CCC discrete space-time information-physical dual theory, constructs a three-dimensional topological dual mapping system, establishes hardware native topological evolution driving logic, and realizes chip computing power autonomous scheduling, hardware self-adaptive reconstruction, error self-healing correction and dynamic power consumption optimization. The application overturns the software passive control paradigm of the traditional chip, creates the next-generation chip bottom layer general paradigm of hardware-level autonomous intelligent control, has extremely high bottom layer theoretical barriers and full-coverage protection range, can be adapted to all types of high-end semiconductor chips, and has extremely strong industry monopoly and industrialization value.

The invention provides a non-destructive data reading method for a ferroelectric memory, and relates to the technical field of semiconductor memories, and the method comprises the steps: S1, applying a subthreshold reading voltage; s2, detecting a polarization response signal; s3, comparing and judging a logic state; the method has thorough non-destructiveness, the polarization direction of the ferroelectric capacitor cannot be overturned in the whole read operation process, and original storage data can be completely reserved. The write-back operation necessary for the traditional method is fundamentally eliminated. Delay and power consumption can be reduced, energy consumed by write-back operation is avoided, and dynamic power consumption is remarkably reduced; the read-write service life of the ferroelectric memory is greatly prolonged; and the design flexibility and robustness are improved.

This invention discloses a low-scan-power scanning unit and scanning chain, belonging to the field of integrated circuit design-for-test (DTBT). The invention uses a low-scan-power scanning unit, adding an OR gate to control the switching activity of two tri-state gates in the secondary latch unit during the scanning phase, and using a high-threshold PMOS as a power supply gating to control the power supply VDD of the two inverters inside the secondary latch unit, thus reducing the dynamic power consumption of the secondary latch and unnecessary dynamic power consumption of the combinational logic during the scanning phase. Additionally, a test vector output port P is added, whose signal originates from the output of the primary latch unit inside the scanning unit, reducing the transmission path delay during the scanning phase. This invention is applicable to the DTBT stage of digital circuits; by simply adding an OR gate and a high-threshold PMOS, without affecting the original logic circuit function, it achieves the goal of reducing dynamic power consumption during the shift phase.

The present application relates to the technical field of electronic timer, and especially to an environment adaptive low power consumption management system and method for electronic timer, the system comprising an environment perception array, a physical state evaluator, a dynamic power consumption strategy generator, a closed loop execution and calibration unit and an adaptive compensator; the present application dynamically collects multi-dimensional environment parameters, constructs a coupling model representing the relationship between frequency offset and compensation power consumption, combines the residual power of the device and the cumulative value of timing error, generates joint control parameters through multi-objective optimization, drives hardware execution and real-time monitors operation deviation, and realizes adaptive iterative optimization of strategy through feedback closed loop. The present application effectively solves the pain point of mutual restriction between precision and power consumption of traditional electronic timer, greatly improves the environment adaptive ability, endurance time and whole life cycle operation stability of the device.

The invention relates to the technical field of semiconductors, and particularly discloses an MOSFET device with low grid charge and a preparation method of the MOSFET device. A LOCOS isolation layer; a P-type electric field regulation and control layer is shallowly buried under the channel; a transverse doping gradient channel; a gate dielectric layer; a main gate; a shield grid structure; the source side doping concentration of the asymmetric LDD region is 1 * 10 < 18 > cm <-3 >, the width is 0.1 mu m, and the depth is 50nm; the doping concentration of the drain side is 5 * 10 < 17 > cm <-3 >, the width is 0.15 mu m, and the depth is 50nm; a drain region is provided with a two-stage stepped groove; a source-drain heavily doped region; and the metal electrode comprises a source electrode, a main grid electrode, a shielding grid and a drain electrode. Through the synergistic effect of the shallow-buried P-type electric field regulation and control layer under the channel, the shield gate, the drain region two-stage stepped groove and the composite gate dielectric, the gate-drain coupling capacitance and the gate capacitance are reduced in principle, the Miller effect is inhibited, the ultra-thin gate and the NiSi silicide are combined to reduce the gate driving loss, meanwhile, sub-threshold electric leakage is inhibited, static and dynamic power consumption is doubly reduced, and the reliability of the device is improved. And the sensor endurance is prolonged.

The invention discloses a dynamic power consumption adjusting method, device and equipment based on load prediction and hierarchical dormancy and a storage medium, and relates to the technical field of dynamic environment monitoring systems, and the method comprises the steps: obtaining processor occupation information, sensor connection quantity information, data collection frequency information, communication state information and to-be-processed data quantity information; inputting a predefined load prediction model based on the processor occupation information, the sensor connection quantity information, the data acquisition frequency information, the communication state information and the to-be-processed data quantity information to predict a load change trend in predefined time, and determining a load change trend prediction result, generating corresponding dormancy control strategy information and power consumption adjustment strategy information based on the load change trend prediction result; and controlling the system to operate normally based on the sleep control strategy information and the power consumption adjustment strategy information. The power consumption of the system is dynamically adjusted through load prediction and hierarchical dormancy, and the energy efficiency and endurance are remarkably improved.