242 results about "Dynamic power dissipation" patented technology

The invention discloses a load prediction-based solid state disk power consumption optimization method and system, and particularly relates to the technical field of solid state disks, and the method comprises the following steps: S1, data acquisition; s2, constructing and training a load prediction model; s3, load prediction; s4, power consumption optimization: optimizing the power consumption of the solid state disk by adopting a multi-objective optimized dynamic power consumption adjustment algorithm according to a load prediction result; and S5, feedback adjustment: monitoring actual power consumption and performance parameters of the solid state disk after optimization in real time, and adjusting the load prediction model and the dynamic power consumption adjustment algorithm in combination with a reinforcement learning algorithm. According to the solid state disk power consumption optimization method and system based on load prediction, a set of complete and efficient solid state disk power consumption optimization scheme is formed from load prediction model construction, dynamic power consumption adjustment algorithm design and feedback adjustment mechanism optimization; and a new technical thought and a new practice direction are expected to be provided for reducing energy consumption and improving performance of the solid state disk.

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The invention discloses a single-chip microcomputer hierarchical dormancy control method based on dynamic power consumption prediction, and relates to the technical field of single-chip microcomputer low power consumption control, and the method specifically comprises the steps: building a mapping relation between a load current and a clock frequency; setting a dynamic dormancy threshold value; constructing a dynamic power consumption prediction model; a dormancy strategy is designed, module-level power consumption management and single-chip microcomputer function-based power consumption management are adopted, the callable frequency or the maximum operation duration of each function is distributed according to task priorities and battery residual energy consumption, and single-chip microcomputer peripherals are triggered through events and are independently awakened; and executing the sleep strategy, automatically awakening the single chip microcomputer according to a preset awakening condition, and realizing abnormity positioning and processing based on threshold comparison and power consumption monitoring in the process of executing the sleep strategy. According to the invention, module-level power consumption management and single-chip microcomputer function-based power consumption management are realized, the limitation of traditional global dormancy is broken, the need of overall reset during wakeup is avoided, and the response speed is improved while the energy consumption is reduced.

The invention discloses an agricultural heterogeneous multi-core SoC (System on Chip) architecture and equipment integrating vision and environmental perception. According to the architecture, a heterogeneous multi-core design is adopted, a universal CPU and an AI acceleration and preprocessing module are integrated on an on-chip system, an efficient task scheduling mechanism is combined, real-time management and control of multi-source heterogeneous tasks such as image processing, radar resolving and path planning are achieved, and the system response speed and the task execution efficiency are improved. In the aspects of communication and storage, NoC and AXI buses are adopted to cooperatively construct a high-speed data path, DDR4 and Flash mixed storage is supported, and the transmission stability of large-bandwidth data is guaranteed. The power supply and clock management module realizes modularized start and stop and energy consumption optimization through a multi-voltage domain and dynamic power consumption control technology, and is suitable for outdoor long-time operation. The IO and peripheral interface module provides abundant interfaces, and system expansibility and deployment flexibility are improved. The overall framework integrates the advantages of high integration level, high adaptability and low power consumption, and a solid calculation basis is provided for agricultural intelligent equipment.

The invention relates to the technical field of data center thermal management, and discloses a data center liquid cooling precise temperature control method and system, and the method comprises the following steps: pre-analyzing a calculation task to generate a power consumption prediction sequence; combining the power consumption prediction sequence with the real-time state information of the liquid cooling system, calculating the heat cost of the task at each candidate calculation node through a digital twin model, and selecting a target execution node according to the heat cost; inputting the power consumption prediction sequence and real-time state information into a reinforcement learning controller, and generating a composite coordination action containing a flow regulation instruction and a dynamic power consumption upper limit instruction; and cooperatively controlling the micro-fluidic execution array and the chip power consumption management unit on the target execution node according to the composite coordination action. Through prospective power consumption prediction and two-way cooperative control from the heating end and the heat dissipation end, intelligent distribution and accurate temperature control of thermal loads are achieved, temperature overshoot is effectively restrained, and the overall operation energy consumption of the data center is reduced while the system reliability is guaranteed.

The invention provides a chip power supply network compensation method and device, equipment, a storage medium and a program, relates to the technical field of integrated circuits, in particular to a chip and circuit design technology, can be applied to an application scene of chip test optimization, and the method comprises the following steps: determining a dynamic power consumption violation area of a current power supply network of a target chip; performing compensation priority classification on the dynamic power consumption violation area according to the voltage drop violation distribution information of the dynamic power consumption violation area to obtain a violation priority classification area; and determining a local power supply network compensation strategy of each violation priority classification area according to the compensation priority of the violation priority classification area. According to the embodiment of the invention, the efficiency and precision of chip power supply network compensation can be improved.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

The invention relates to the technical field of Bluetooth earphones, and discloses a Bluetooth earphone dynamic power consumption and transmission delay balance control system, which comprises a state acquisition module, a strategy generation module, a factor analysis module, a quantitative evaluation module, a parameter adjustment module and an execution control module. The state acquisition module obtains working current, data packet state and the like to construct an evaluation model; the strategy generation module generates an initial association strategy table; the factor analysis module analyzes historical data to identify interference factors; the quantitative evaluation module calculates a stability deviation index; the parameter adjusting module updates the strategy table according to the index; and the execution control module triggers rate switching. The system is further provided with a data packet comparison unit, a timestamp marking unit and the like to process data transmission conflicts, and the transmission quality is optimized through a three-dimensional transmission quality field model, a genetic algorithm and a three-level response mechanism. The system realizes dynamic balance of power consumption and transmission delay, and is suitable for the field of power consumption and transmission control of the Bluetooth headset.

The invention discloses a domestic heterogeneous chip dynamic power consumption cooperative scheduling method oriented to a vehicle-mounted environment, and aims to solve the problem of system energy efficiency optimization caused by strict limitation of power supply and heat dissipation resources, dynamic mixing of calculation tasks and unique power consumption characteristics of domestic chips in the vehicle-mounted environment. The method is based on a vehicle-mounted heterogeneous computing platform comprising a domestic central processing unit, a field programmable gate array and a memory, and is realized through a closed-loop scheduling process executed by the central processing unit. According to the method, global, dynamic and collaborative power consumption management of domestic heterogeneous chip resources is realized, and the overall energy efficiency and the operation reliability of the system are remarkably improved on the premise of ensuring the real-time performance and the performance of a vehicle-mounted task.

The invention provides a low-power-consumption scheduling method and system for an edge heterogeneous computing unit, and the method comprises the steps: constructing a resource sensing model of heterogeneous hardware, and collecting the performance parameters of a processing unit in real time; establishing a task priority evaluation model, and calculating a task priority by adopting an analytic hierarchy process based on the resource perception model and the task priority evaluation model; designing a collaborative optimization model; based on the collaborative optimization model and by adopting an improved particle swarm optimization algorithm, solving an optimal allocation scheme of tasks in the heterogeneous hardware, and dynamically adjusting the working frequency of the heterogeneous hardware; monitoring states of task execution and heterogeneous hardware in real time, judging whether resource overload or task timeout risks occur in the states or not, and if yes, triggering scheduling scheme updating. According to the method, local optimum is effectively avoided, the solution efficiency and the solution quality are remarkably improved, and the frequency-to-voltage linkage dynamic power consumption regulation and control closed loop is realized by triggering scheduling scheme updating.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

The invention provides a spatial heterogeneous computing resource scheduling method and device based on dynamic power consumption budget, a terminal, a medium and a product. The method is applied to task initiating equipment, and comprises the following steps: acquiring a current to-be-executed spatial computing task, and determining a current dynamic spatial heterogeneous computing group; obtaining the current power consumption budget score and equipment capability information of each computing equipment in the computing group; and selecting one or more optimal computing devices from the computing devices by utilizing a multi-objective optimization scheduling algorithm according to the spatial computing task and based on the obtained current power consumption budget score and the device capability information of the computing devices, so that the one or more optimal computing devices execute the spatial computing task. Through power consumption budget scoring and a multi-objective optimization scheduling algorithm, the method effectively prevents a low-power or energy-shortage device from undertaking a high-energy-consumption task, thereby remarkably reducing energy consumption, prolonging the effective service time of the computing device, and improving the stability.

The invention relates to the technical field of electronic timers, in particular to an environment self-adaption low-power-consumption management system and method for an electronic timer, and the system comprises an environment sensing array, a physical state evaluator, a dynamic power consumption strategy generator, a closed loop execution and calibration unit and a self-adaption compensator. According to the method, multi-dimensional environment parameters are dynamically collected, a coupling model representing the relation between frequency deviation and compensation power consumption is constructed, combined regulation and control parameters are generated through multi-target optimization by combining the residual electric quantity of equipment and a timing error accumulated value, hardware execution is driven, operation deviation is monitored in real time, and strategy self-adaptive iterative optimization is achieved through a feedback closed loop. According to the invention, the pain point that the precision and the power consumption of a traditional electronic timer are mutually restricted is effectively solved, and the equipment environment adaptive capability, the endurance time and the full life cycle operation stability are greatly improved.

The invention provides a dual-conversion gain reading circuit, a reading method and an image sensor, and the circuit comprises a comparison module which carries out the pre-comparison of a high-gain photosensitive signal and a ramp signal, so as to obtain a pre-comparison result, comparing the low-gain reset signal, the high-gain reset signal, the high-gain photosensitive signal and the low-gain photosensitive signal with a ramp signal to output corresponding comparison signals; and the counting module selects a counting mode according to the pre-comparison result to count the comparison signals so as to output data signals. A comparison module is used for pre-comparing a high-gain photosensitive signal with a ramp signal, and a counting module is used for selecting a corresponding counting mode for counting quantization according to a pre-comparison result, so that the corresponding counting mode can be adaptively selected according to a voltage difference value between a high-gain reset signal and the high-gain photosensitive signal; therefore, the dynamic power consumption of the counting module is effectively reduced, the overall power consumption of the reading circuit is reduced, and the problem that an existing dual-conversion gain reading circuit is large in dynamic power consumption is solved.

The invention relates to the technical field of LED lighting control, and discloses an intelligent LED lamp strip power supply control system with an automatic voltage jump function, which comprises an intelligent control power supply, a series topology LED lamp strip and a plurality of cascaded constant current voltage division control chips, and further comprises a topology discovery and automatic addressing module for detecting the total node number and allocating addresses; the cascade voltage division and dynamic power consumption balancing module is used for calculating a target voltage division value according to the total node number; the power and data cooperative transmission module broadcasts a target partial voltage value on a power supply bus and realizes two-way communication; the node localization constant-current driving module is used for the chip to receive the target voltage division value, adjust the actual voltage division value and drive the LED in a constant-current mode; and the intelligent fault diagnosis and controllable bypass module is used for monitoring a fault of the chip, reporting a fault containing an address and responding to an instruction to activate a bypass. According to the invention, the cascade voltage division and dynamic power consumption equalization module is adopted, so that the technical effects of consistent power and highly uniform brightness obtained by all LED nodes in an ultra-long distance are achieved.

The invention provides an intelligent temperature control system and method based on chip heat energy guiding. The method comprises the steps of obtaining running state information of a target chip set; the working mode of the loop heat pipe is determined according to the operation state information of the target chip set, and stepped energy recovery is conducted on conduction heat of the loop heat pipe through the recovery heat pump; thermal state information of the target chipset and energy recovery information of the recovery heat pump in different historical time windows are obtained, correlation verification analysis is carried out according to the thermal state information and the energy recovery information, and an intermittent boiling threshold value of the loop heat pipe is determined; acquiring operation instruction stream data of the chip, and performing dynamic power consumption prediction according to the operation instruction stream data to obtain a dynamic power consumption prediction value; when the dynamic power consumption predicted value is higher than the intermittent boiling threshold value, the liquid return rate of the loop heat pipe is adjusted based on the dynamic power consumption predicted value, the liquid return rate in the heat transfer process can be controlled according to dynamic power consumption prediction, and the heat energy guiding and recycling efficiency is improved.

The invention relates to the technical field of wearable equipment and chip power consumption management, and discloses a storage chip low power consumption management method and system for AI glasses, and the method comprises the steps: obtaining multi-application concurrent operation access request data and an instantaneous current change value; according to the access request data, carrying out access request time interval calculation to obtain concurrent access density distribution feature data; according to the instantaneous current change value and the concurrent access density distribution characteristic data, carrying out association binding to obtain access request characteristic data; and performing conflict request identification and risk assessment according to the access request feature data, and performing dynamic power consumption parameter adjustment in combination with real-time power consumption data to obtain a storage chip power consumption distribution scheme. The method can solve the technical problem of low power consumption management efficiency.

The invention discloses a random question number generator and method suitable for a question and answer mode watchdog, and belongs to the technical field of integrated circuit safety. Comprising an on-chip high-frequency oscillation source, an enabling controller, a low-power-consumption controller, a pseudo-random number generator and a random code hopping device. According to the method, an external dog feeding signal is used for triggering, a non-reproducible hopping code value is generated by using different sources of clock sources and physical deviation of signal transmission, a pseudo-random number generator is controlled to operate within a random duration, and a low-power-consumption state is entered after a final random problem number is output and latched. Through hardware-level entropy source enhancement and dynamic power consumption management, the predictable potential safety hazard of the traditional pseudo-random number sequence is fundamentally solved, and the balance of high randomness, high attack resistance and low power consumption is realized at low cost.

The invention discloses a three-frequency-band satellite terminal multi-parameter dynamic power consumption optimization method, system and device and a storage medium, and the method comprises the steps: obtaining multi-dimensional parameter data of a three-frequency-band communication system, carrying out the preprocessing of the multi-dimensional parameter data, carrying out the feature extraction of the preprocessed multi-dimensional parameter data, carrying out the integration of the extracted features, and carrying out the optimization of the multi-parameter dynamic power consumption of a three-frequency-band communication system; obtaining a multi-dimensional feature vector; processing the multi-dimensional feature vector by using a prediction model to obtain a prediction result; adjusting dynamic power consumption optimization according to the prediction result; based on dynamic power consumption optimization adjustment, the actual performance parameters of the adjusted three-frequency-band communication system are monitored, the difference between the actual performance parameters and a prediction result is utilized, a prediction model is updated, optimization of multi-parameter dynamic power consumption of the three-frequency satellite terminal is achieved, and the system can still keep high communication quality in a complex frequency band interference environment.

The invention discloses a livestock intelligent ear tag and management system, which comprises a Bluetooth AOA positioning module, a UHF RFID module, a sensor module and a dynamic power consumption management unit, and is characterized in that the Bluetooth AOA positioning module realizes centimeter-level dynamic positioning through a base station array, and the dynamic power consumption management unit adjusts the data reporting frequency according to the livestock motion state. The Bluetooth AOA positioning module and the UHF RFID module are dynamically switched and multiplexed in a time division mode, and the limitation of a traditional ear tag on precision, endurance and reliability is broken through through three core technologies of double-frequency cooperation, dynamic power consumption and a glue-pouring-free technology.

A bit line charge sharing precharge circuit is provided that precharges a bit line pair during a charge sharing period in which the bit line pair is isolated from a memory power supply voltage. Prior to the charge sharing period, one of the bit lines in the bit line pair was charged to the memory power supply voltage whereas a remaining one was either fully or partially discharged. Charge thus flows from the charged bit line to the discharge bit line during the charge sharing period to precharge the bit lines for a current read or write operation.

The invention provides a gated clock circuit, a chip and electronic equipment. The gated clock circuit comprises a signal control module and a clock tree module, the signal control module generates a clock tree signal according to a source clock signal and input signals and output signals of all the single-bit D triggers; the clock tree module generates a plurality of sub-clock signals according to the clock tree signal; when the input signals and the output signals of all the single-bit D triggers are the same, the generated clock tree signal prevents the propagation of the source clock signal; when the input signal and the output signal of any single-bit D trigger are different, the generated clock tree signal enables the clock tree module to generate a plurality of sub-clock signals. The working state of the clock tree module is controlled through the signal control module, so that when the single-bit D flip-flop does not work, the clock tree module stops clock propagation, dynamic power consumption generated by clock flip-flop is saved, and the problem of how to reduce the dynamic power consumption generated by the single-bit D flip-flop in a chip is solved.

The invention discloses an automatic testing method and device for a water meter module, a medium and a product. In the method, a manipulator is controlled to grab a to-be-tested water meter module and place the to-be-tested water meter module at a test station, and start power consumption characteristic data, sleep power consumption characteristic data and valve control response characteristic data of the to-be-tested water meter module are collected; processing the starting power consumption characteristic data, the dormancy power consumption characteristic data and the valve control response characteristic data to construct an electrical reference portrait; writing a module identity into a nonvolatile memory of the water meter module to be tested; performing function verification on the to-be-tested water meter module to obtain a dynamic function data set; obtaining dynamic power consumption characteristic data, and verifying the dynamic function data set and the dynamic power consumption characteristic data to obtain a consistency verification result; and generating a quality judgment conclusion, and moving the to-be-detected water meter module to a preset area according to the quality judgment conclusion. By implementing the technical scheme provided by the invention, the limitation that a traditional quality inspection method only depends on independent parameter threshold judgment is effectively overcome.

The invention belongs to the technical field of wearable equipment, and discloses a self-powered multi-parameter wearable health monitoring system and a working method thereof, and the system comprises a dual-mode self-powered module which is used for generating and outputting electric energy to a DC-DC voltage stabilization chip; the multi-modal sensor array is used for collecting predetermined various vital sign index information and environmental data; the edge AI processing unit is used for performing AI reasoning according to the various vital sign index information and the environmental data, and generating and outputting a health risk assessment result; the dynamic power consumption management module is used for collecting the input power of the DC-DC voltage stabilization chip and the current power consumption of the system, and generating and sending a power consumption scheduling instruction to the multi-mode sensor array and the edge AI processing unit according to the input power of the DC-DC voltage stabilization chip and the current power consumption of the system; according to the invention, the power consumption management and endurance strategy precision is improved, the phenomenon of insufficient energy supply or waste is avoided, and all-weather, continuous and high-precision health monitoring can be realized.

The invention discloses an active intelligent lock system and a control method thereof, and belongs to Internet of Things safety equipment. The active intelligent lock system is provided with an environment energy collection module, a dual-channel power management module, a dynamic power consumption controller, a multi-mode authentication module, an authorization authentication module, a communication module and a master control MCU (Microprogrammed Control Unit), the environment energy collection module and the dual-channel power management module can improve the power supply endurance of the active intelligent lock system and the safety emergency processing of power supply faults, and the dynamic power consumption controller can provide three different power consumption modes to optimize the dynamic energy consumption in multiple use scenes, so that the utilization rate of electric energy is improved; the multi-mode authentication module and the authorization authentication module provide a multi-person combined unlocking mechanism, the industrial-grade centralized supervision requirement and intelligent management are met, and the use safety and operation convenience of the active intelligent lock system are effectively improved.

This invention belongs to the field of integrated circuit testing and semiconductor manufacturing quality control technology, and discloses an integrated circuit final testing method and system based on dynamic power consumption compensation. The method includes the following steps: acquiring power consumption prediction data for each test vector in the test program; querying a lookup table to obtain the expected voltage drop value corresponding to each test vector; performing feedforward pre-compensation on the supply voltage based on the expected voltage drop value before testing; monitoring the actual voltage at the power supply pin in real time during testing; comparing the actual voltage with the target voltage to generate an error signal; performing feedback fine-tuning compensation on the supply voltage based on the error signal; and collecting the actual voltage drop value under each test vector after testing, iteratively updating the expected voltage drop value of the corresponding test vector in the lookup table based on the deviation between the actual voltage drop value and the corresponding expected voltage drop value. This invention can solve the problems of test misjudgment, low yield, and insufficient test coverage caused by IR drop in traditional testing methods.

The invention discloses an SSD dynamic power consumption management method and device, computer equipment and a storage medium, and relates to the technical field of SSD power consumption management. Determining a total number of tokens of the token bucket based on the power consumption gear; initializing a token bucket based on the total number of tokens; if the host command is received, determining the number of target tokens required by the host command; judging whether the number of the remaining tokens in the token bucket is greater than or equal to the number of the target tokens; if yes, distributing tokens of a target token number to the host command, and executing the host command; and if not, adding the host command to a preset command waiting queue. According to the SSD dynamic power consumption management method, the power consumption upper limit reference is established through power consumption gear setting, and it is ensured that the instantaneous power consumption of the SSD never exceeds the limit. Therefore, limitation of a protocol layer is broken through, a host manufacturer can configure a power consumption threshold according to needs, redundant design and compatibility risks of a power supply module are eliminated, and power consumption self-adaption capability is given to terminal equipment.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

The invention relates to the technical field of integrated circuit design and Internet of Things, in particular to a high-integration-level low-power-consumption system-level industry 5G AIoT chip which comprises a multi-core heterogeneous computing module, a high-integration-level radio frequency front-end module, a low-power-consumption storage and data management module and a power management and dynamic power consumption optimization module. The multi-core heterogeneous computing module comprises a reduced instruction set-V (RISC-V) core which is used as a main control core, adopts a 64-bit architecture and is used for task scheduling and system management; a dedicated AI acceleration core is based on in-memory computing (CIM) technology. According to the high-integration-level low-power-consumption system-level industry 5G AIoT chip, miniaturization, low power consumption and function diversification of industry terminal equipment are achieved by integrating a multi-core calculation module, a high-integration radio frequency module, a low-power-consumption storage module and an intelligent power management module, and the high-integration-level low-power-consumption system-level industry 5G AIoT chip is particularly suitable for 5G Internet of Things terminals of industry scenes such as industrial monitoring, intelligent power grids and intelligent cities; and the integrated functions of communication, calculation, storage and power management can be realized.

The application discloses an AI cluster perception-based dynamic power distribution system of a heterogeneous computing platform, which comprises a data acquisition module, a performance quantization module, a power consumption analysis module and a power distribution module.The data acquisition module acquires the real-time power consumption and utilization rate of each computing unit in the cluster, and forms a heterogeneous unit data set after preprocessing.The performance quantization module obtains the single-resource bottleneck coefficient of each resource type based on the heterogeneous unit data set, and calculates the comprehensive bottleneck coefficient of each unit by constructing an AI-based bottleneck perception space-time network.The power consumption analysis module identifies the critical path unit and the idle unit based on the comprehensive bottleneck coefficient by using a weighted power consumption redistribution algorithm based on critical path perception, and calculates the releasable power consumption factor of the critical path unit and the idle unit to perform optimized distribution in combination with the comprehensive bottleneck coefficient, so that the best target power consumption range of the computing platform is obtained.The power distribution module performs setting operation by calling the underlying hardware power consumption management interface based on the power consumption upper limit value set of different units, so that dynamic power distribution is realized.