356 results about "Dynamic power dissipation" patented technology

The invention discloses a load prediction-based solid state disk power consumption optimization method and system, and particularly relates to the technical field of solid state disks, and the method comprises the following steps: S1, data acquisition; s2, constructing and training a load prediction model; s3, load prediction; s4, power consumption optimization: optimizing the power consumption of the solid state disk by adopting a multi-objective optimized dynamic power consumption adjustment algorithm according to a load prediction result; and S5, feedback adjustment: monitoring actual power consumption and performance parameters of the solid state disk after optimization in real time, and adjusting the load prediction model and the dynamic power consumption adjustment algorithm in combination with a reinforcement learning algorithm. According to the solid state disk power consumption optimization method and system based on load prediction, a set of complete and efficient solid state disk power consumption optimization scheme is formed from load prediction model construction, dynamic power consumption adjustment algorithm design and feedback adjustment mechanism optimization; and a new technical thought and a new practice direction are expected to be provided for reducing energy consumption and improving performance of the solid state disk.

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The invention discloses a quantum dot enhanced dynamic power consumption management method, a quantum dot enhanced dynamic power consumption management system and related equipment. Aiming at the problem of insufficient optimization caused by difficulty in comprehensively, accurately and dynamically sensing the internal energy distribution and conversion process of a chip by a traditional method, the method comprises the following steps of: acquiring the quantum state of the chip in real time by utilizing a quantum dot sensing array, and constructing an adaptive power consumption prediction model by combining multi-source data fusion and feature extraction; and an optimal management strategy is generated based on a multi-objective optimization framework, an execution feedback and self-learning mechanism is introduced, and finally a complete closed-loop control system is formed. The method can be widely applied to various processor chips in the fields of high-performance calculation, the Internet of Things, artificial intelligence and the like, dynamic power consumption management of the chips is achieved through the quantum dot enhancement technology, the performance is guaranteed, meanwhile, energy consumption is minimized, the battery endurance time is prolonged, the heat dissipation cost is reduced, and the energy efficiency of the chips can be remarkably improved.

The invention provides a design method and system for a high-integration-level low-power-consumption radio frequency front-end chip, and relates to the technical field of chips, the design method comprises the steps that a radio frequency transceiver, a power amplifier, a low-noise amplifier and a switch module are integrated on a single silicon substrate, and a self-adaptive bias control system is realized in the monolithic integrated radio frequency front-end chip; comprising the steps that a plurality of temperature sensors, a plurality of voltage sensors and a plurality of current sensors are arranged, a digital signal processor calculates optimal bias parameters of all modules according to a preset power consumption optimization algorithm, and bias control signals are sent to the corresponding modules through a digital-to-analog converter; based on the self-adaptive bias control system, dynamic power consumption management of the radio frequency front-end chip is achieved, when it is detected that radio frequency signal transmission is finished, the digital signal processor controls all the modules to enter a low-power-consumption standby state, and the overall power consumption of the chip is further reduced.

The invention discloses a single-chip microcomputer hierarchical dormancy control method based on dynamic power consumption prediction, and relates to the technical field of single-chip microcomputer low power consumption control, and the method specifically comprises the steps: building a mapping relation between a load current and a clock frequency; setting a dynamic dormancy threshold value; constructing a dynamic power consumption prediction model; a dormancy strategy is designed, module-level power consumption management and single-chip microcomputer function-based power consumption management are adopted, the callable frequency or the maximum operation duration of each function is distributed according to task priorities and battery residual energy consumption, and single-chip microcomputer peripherals are triggered through events and are independently awakened; and executing the sleep strategy, automatically awakening the single chip microcomputer according to a preset awakening condition, and realizing abnormity positioning and processing based on threshold comparison and power consumption monitoring in the process of executing the sleep strategy. According to the invention, module-level power consumption management and single-chip microcomputer function-based power consumption management are realized, the limitation of traditional global dormancy is broken, the need of overall reset during wakeup is avoided, and the response speed is improved while the energy consumption is reduced.

The invention belongs to the technical field of electronic design automation, and provides a dynamic power consumption optimization method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design, and determining a starting point of a specific type in the circuit design; performing backward traversal on the circuit design along a signal propagation direction from the starting point to determine circuit branch structure information and a specific type of termination point in the circuit design; starting from the termination point, establishing an ODC expression, performing forward traversal on the circuit design in an inverse signal propagation direction, and in the forward traversal process, based on the circuit branch structure information, propagating the ODC expression in the circuit design until ODC distribution of the circuit design is determined; based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. According to the method, the ODC expression can be quickly and efficiently propagated in the whole circuit design, so that a designer can conveniently optimize the dynamic power consumption through ODC distribution.

The invention discloses a gamepad energy-saving control method and system based on intelligent analysis, and the method comprises the steps: obtaining the operation monitoring information of a gamepad, and carrying out the preprocessing of the operation monitoring information of the gamepad, and obtaining the multi-mode fusion features of a target gamepad; constructing a user operation analysis model, and analyzing the operation behavior of the target user using the gamepad to obtain user operation analysis information; constructing an operation state transition matrix based on the multi-modal fusion features of the target gamepad, and predicting the operation intention of the target user; constructing an energy-saving control strategy database, acquiring energy-saving control parameters matched with the current operation scene from the energy-saving control strategy database, and establishing a dynamic regulation and control mechanism to dynamically regulate and control the energy-saving control parameters; and if the matched energy-saving control parameter combination does not exist in the energy-saving control strategy database, making an energy-saving control strategy. Intelligent energy-saving control of dynamic power consumption regulation and control is realized, so that the energy efficiency performance of the gamepad and the user experience are improved.

The invention relates to a dynamic power consumption management method and related equipment for a storage and calculation integrated chip, and the method comprises the following steps: carrying out the temperature data collection of a target chip, and obtaining a temperature distribution diagram of the target chip; performing power consumption-temperature correlation analysis on the target chip based on the target chip power consumption distribution diagram and the target chip temperature distribution diagram to obtain a power consumption-temperature correlation matrix; performing power consumption management planning on the target chip based on the power consumption-temperature incidence matrix to obtain a dynamic power consumption management strategy; performing voltage frequency adjustment on the target chip based on the dynamic power consumption management strategy to obtain a voltage frequency control parameter; and performing power consumption management on the target chip based on the voltage frequency control parameter to obtain a chip power consumption management scheme, thereby solving the technical problem that a traditional optimization strategy based on a single parameter is difficult to meet the requirements of high efficiency and energy conservation due to a complex nonlinear relationship between power consumption and temperature.

The invention discloses an agricultural heterogeneous multi-core SoC (System on Chip) architecture and equipment integrating vision and environmental perception. According to the architecture, a heterogeneous multi-core design is adopted, a universal CPU and an AI acceleration and preprocessing module are integrated on an on-chip system, an efficient task scheduling mechanism is combined, real-time management and control of multi-source heterogeneous tasks such as image processing, radar resolving and path planning are achieved, and the system response speed and the task execution efficiency are improved. In the aspects of communication and storage, NoC and AXI buses are adopted to cooperatively construct a high-speed data path, DDR4 and Flash mixed storage is supported, and the transmission stability of large-bandwidth data is guaranteed. The power supply and clock management module realizes modularized start and stop and energy consumption optimization through a multi-voltage domain and dynamic power consumption control technology, and is suitable for outdoor long-time operation. The IO and peripheral interface module provides abundant interfaces, and system expansibility and deployment flexibility are improved. The overall framework integrates the advantages of high integration level, high adaptability and low power consumption, and a solid calculation basis is provided for agricultural intelligent equipment.

The invention relates to the technical field of data center thermal management, and discloses a data center liquid cooling precise temperature control method and system, and the method comprises the following steps: pre-analyzing a calculation task to generate a power consumption prediction sequence; combining the power consumption prediction sequence with the real-time state information of the liquid cooling system, calculating the heat cost of the task at each candidate calculation node through a digital twin model, and selecting a target execution node according to the heat cost; inputting the power consumption prediction sequence and real-time state information into a reinforcement learning controller, and generating a composite coordination action containing a flow regulation instruction and a dynamic power consumption upper limit instruction; and cooperatively controlling the micro-fluidic execution array and the chip power consumption management unit on the target execution node according to the composite coordination action. Through prospective power consumption prediction and two-way cooperative control from the heating end and the heat dissipation end, intelligent distribution and accurate temperature control of thermal loads are achieved, temperature overshoot is effectively restrained, and the overall operation energy consumption of the data center is reduced while the system reliability is guaranteed.

The invention relates to the technical field of integrated circuit design verification, and provides a chip power consumption analysis optimization method and system, and the method comprises the steps: obtaining circuit structure information of a chip, carrying out the analysis of the circuit structure information, generating and analyzing a module topological graph and a function logic graph of a circuit, and obtaining static power consumption data and dynamic power consumption data; after a preset analysis model is input and working mode parameters are obtained, a key path in the circuit structure information is reconstructed, based on the reconstructed circuit structure information, dynamic behavior simulation is carried out on the function logic diagram again, simulation power consumption data are generated, the simulation power consumption data and the dynamic power consumption data are subjected to comparative analysis, and the simulation power consumption data are obtained. And generating a power consumption optimization scheme based on the comparison result. By acquiring and analyzing the circuit structure information of the chip, a power consumption optimization scheme is generated, the energy efficiency ratio of the chip is improved, and the problem that an optimization path is difficult to quickly generate for a complex circuit structure during positioning of a power consumption hot spot and circuit optimization reconstruction is solved.

The invention relates to the technical field of remote controller awakening, and discloses a remote controller awakening method, device and equipment and a storage medium, and the method comprises the steps: carrying out the multi-cascade coding processing of a key signal of a remote controller, obtaining the multi-cascade coding data, and generating a session key; performing adaptive carrier modulation to obtain a dynamic modulation signal; performing multi-band emission control processing and adaptive power control to obtain an emission control signal; performing low power consumption management on the remote controller system, creating a multi-stage dormancy strategy and a dynamic power consumption control scheme, and controlling the signal processor to receive the multiband optical signal; performing parallel processing and adaptive decoding on the multi-band optical signal to obtain decoded multi-cascade coded data; and based on the session key, performing multi-factor identity verification processing on the decoded multi-cascade coded data to obtain a secure wake-up instruction, thereby improving the reliability and security of wake-up, optimizing the power consumption management strategy, and enhancing the signal processing capability.

The invention provides a chip power supply network compensation method and device, equipment, a storage medium and a program, relates to the technical field of integrated circuits, in particular to a chip and circuit design technology, can be applied to an application scene of chip test optimization, and the method comprises the following steps: determining a dynamic power consumption violation area of a current power supply network of a target chip; performing compensation priority classification on the dynamic power consumption violation area according to the voltage drop violation distribution information of the dynamic power consumption violation area to obtain a violation priority classification area; and determining a local power supply network compensation strategy of each violation priority classification area according to the compensation priority of the violation priority classification area. According to the embodiment of the invention, the efficiency and precision of chip power supply network compensation can be improved.

The invention discloses an ultra-low power consumption pyroelectric infrared human body detector and a networking control method thereof. The detector comprises a detection module, a control module, a power supply module, a communication module, an interaction module and a dynamic power consumption management module, human body infrared radiation is detected based on the pyroelectric effect, and ultra-low power consumption operation is achieved by dynamically switching working modes. The networking control method is based on a BLE Mesh protocol, a self-adaptive topology management algorithm is used for optimizing routing, and efficient networking with intelligent equipment is achieved. The system solves the problems of high power consumption, large networking delay, high false alarm rate and the like of a traditional detector, and is suitable for the fields of smart home, intelligent security and protection and the like.

The embodiment of the invention provides a novel integrated charge pump driving circuit and a power integrated circuit, and relates to the technical field of driving circuits, the circuit comprises a front signal processing circuit and a main charge pump and driving circuit; the front signal processing circuit receives a driving logic signal input by the system, preprocesses the driving logic signal and outputs a low-voltage control signal, a first high-voltage control signal and a second high-voltage control signal; and the main charge pump and drive circuit is connected with the output end of the front signal processing circuit, receives the low-voltage control signal, the first high-voltage control signal and the second high-voltage control signal, and processes and outputs a gate drive signal. The circuit provided by the invention can continuously output high-quality gate driving signals, hundred percent duty ratio driving is realized, only dynamic power consumption of the charge pump exists in the whole driving scheme, and the efficiency is higher.

The invention relates to a high-voltage level shift circuit and a layout structure thereof, and the high-voltage level shift circuit comprises a pulse generation module which is used for receiving an input signal and generating a double-path low-voltage domain narrow pulse signal; the level shift module is used for receiving the low-voltage domain narrow pulse signal and converting the low-voltage domain narrow pulse signal into a corresponding double-path high-voltage domain narrow pulse signal; the voltage transient noise detection module is used for detecting voltage transient noise and generating a transient noise intensity signal; the voltage transient noise filtering module is used for filtering voltage transient noise based on the received transient noise intensity signal to generate a double-path high-voltage domain filtering signal; and the RS trigger is used for converting the received high-voltage domain filtering signal into a high-side power device driving signal. The common-mode noise filtering capability and the VS negative bias resisting capability of the voltage transient noise filtering module can be enhanced, the transmission delay of a chip is effectively reduced, and the width of a narrow pulse signal is free of loss in the transmission process, so that the dynamic power consumption is reduced.

The invention belongs to the technical field of chip design, and particularly relates to a method for estimating interconnection line parasitic capacitance based on integrated learning in a pre-layout stage, which can improve the accuracy of dynamic power consumption calculation in the early stage of physical design. Comprising the following steps: S1, extracting original data of a circuit and calculating physical characteristics of an interconnection line; s2, establishing a feature-capacitance label supervision training data set of the interconnection line; s3, training an interconnection line parasitic capacitance prediction model; and S4, after the training stage is ended, entering a prediction stage, and taking the physical characteristics of the interconnection line in the current design pre-layout stage as the input of an interconnection line stray capacitance prediction model to obtain predicted stray capacitance. The method is simple and easy to use, the pre-layout information and the final design result have high consistency, the accuracy of circuit power consumption calculation in the early stage of physical design can be improved, and the design period is shortened.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

The invention provides an intelligent clock gating NoC system based on AXI interconnection and a dynamic power consumption management method, and belongs to the technical field of integrated circuit design, the system is characterized in that an AXI interconnection matrix module is provided with a crossbar switch, a master port and a slave port, and the master port and the slave port are connected with the crossbar switch through an AXI bus; each router node in the 2D Mesh network module is provided with a local port and a peripheral port, and each router node is connected with an adjacent router node through the peripheral port; the intelligent clock gating module monitors the channel flow of the AXI interconnection matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls a clock signal; and the dynamic power management module adjusts the power consumption state according to the global power optimization signal and the local optimization signal. The overall power consumption of the system-on-chip is reduced, and the stability and efficiency of data transmission are enhanced.

The invention discloses a universal verification system, device and method suitable for the functional performance of an FPGA device, and relates to the technical field of FPGA device testing, the universal verification system comprises verification hardware, verification software, a verification auxiliary instrument and environment equipment, and the specific verification steps are as follows: step 1, on-chip logic function verification; step 2, common interface function verification; 3, software and hardware adaptability function verification; 4, comprehensive performance function verification; 5, dynamic power consumption testing; step 6, common IP function verification; 7, testing associated parameters; step 8, system adaptability; and step 9, environment adaptability. The universal verification system is suitable for verification of a serial interface function, a multi-path IO compatibility test function, development software platform adaptability, simulator adaptability, a configuration mode, configuration starting time, a signal processing function, official IP supportability and the like, and has functions of a high-speed interface protocol, an Aurora protocol, a DDR protocol, an IIC protocol, an SPI protocol and the like.

The invention relates to the technical field of Bluetooth earphones, and discloses a Bluetooth earphone dynamic power consumption and transmission delay balance control system, which comprises a state acquisition module, a strategy generation module, a factor analysis module, a quantitative evaluation module, a parameter adjustment module and an execution control module. The state acquisition module obtains working current, data packet state and the like to construct an evaluation model; the strategy generation module generates an initial association strategy table; the factor analysis module analyzes historical data to identify interference factors; the quantitative evaluation module calculates a stability deviation index; the parameter adjusting module updates the strategy table according to the index; and the execution control module triggers rate switching. The system is further provided with a data packet comparison unit, a timestamp marking unit and the like to process data transmission conflicts, and the transmission quality is optimized through a three-dimensional transmission quality field model, a genetic algorithm and a three-level response mechanism. The system realizes dynamic balance of power consumption and transmission delay, and is suitable for the field of power consumption and transmission control of the Bluetooth headset.

The invention relates to the field of integrated circuit design, and particularly discloses a high power supply rejection ratio and low swing driving frequency-locked loop circuit and a control method thereof, a low dropout regulator is adopted to provide independent power supply lower than a main power supply voltage for a voltage-controlled oscillator, and double optimization effects are achieved. The clean power supply provided by the low dropout linear regulator effectively isolates the interference of the main power supply noise to the voltage-controlled oscillator, so that the power supply noise suppression capability of the circuit is remarkably enhanced, and the jitter of an output clock signal is greatly reduced; and on the other hand, the working voltage of the voltage-controlled oscillator is allowed and dynamically regulated and controlled to be optimized in a low range meeting the performance according to the real-time load of the voltage-controlled oscillator, so that on-demand power supply is realized, the dynamic power consumption of the voltage-controlled oscillator is reduced to the maximum extent while the output quality is not reduced, and the energy efficiency of the whole circuit under different load conditions is improved.

The invention relates to a memory device and a manufacturing method thereof. The memory device includes: a substrate; the source line is arranged on the substrate and is connected with the substrate; the gate lines are arranged on the sides, away from the substrate, of the source lines, and the gate lines are arranged at intervals in the first direction perpendicular to the substrate; the channel structure penetrates through the multiple gate lines in the first direction, and the bottom of the channel structure is connected with the source line; the channel structure comprises a gate insulating layer, a charge capturing layer, a tunneling layer, a channel layer and a core column which are sequentially arranged in the direction from the gate line to the center of the channel structure, and the core column comprises a first isolating layer, a conductive layer and a second isolating layer which are sequentially arranged in the direction away from the source line; and the bit line is arranged on one side, far away from the source line, of the channel structure. The charging and discharging time of the reading operation on the storage unit can be reduced, and the dynamic power consumption generated by the reading operation is reduced. The reading speed of the memory unit is improved, and the service life of the memory device is prolonged.

The invention discloses a flash memory chip test method. The method comprises the following steps: providing a plurality of flash memory chips; performing dynamic power consumption test on the plurality of flash memory chips during erasing operation to obtain power consumption values corresponding to the flash memory chips; performing outlier statistics according to the power consumption values of the plurality of flash memory chips, and determining outlier flash memory chips; and removing the outlier flash memory chips. According to the scheme, the flash memory chips with some process defects can be removed in the yield testing stage, and the quality of the flash memory chips flowing into a terminal user is guaranteed.

The invention discloses a wireless audio data real-time transmission method based on hardware synchronization, and the method comprises the steps: hardware synchronous clock generation and management: a high-precision synchronous clock generator is integrated in a wireless audio module, and a high-precision synchronous clock signal is generated and used for controlling the sending and receiving time sequence of audio data; the synchronous clock generator adopts a clock chip with low power consumption and high stability. Through a high-precision synchronous clock and timestamp embedding mechanism, the real-time performance of audio data can be ensured, delay in the data transmission process is reduced, audio transmission can be synchronous and stable, a dynamic power consumption management mechanism intelligently adjusts power consumption according to audio flow and a network state, the energy consumption of battery power supply equipment is reduced, and the power consumption is reduced. The self-adaptive network transmission method improves the cruising ability of equipment, is particularly suitable for portable equipment, can detect the network condition in real time and adjust the transmission strategy according to the network change through the self-adaptive network transmission strategy, and effectively solves the problems of network delay, packet loss and the like.

The invention discloses a domestic heterogeneous chip dynamic power consumption cooperative scheduling method oriented to a vehicle-mounted environment, and aims to solve the problem of system energy efficiency optimization caused by strict limitation of power supply and heat dissipation resources, dynamic mixing of calculation tasks and unique power consumption characteristics of domestic chips in the vehicle-mounted environment. The method is based on a vehicle-mounted heterogeneous computing platform comprising a domestic central processing unit, a field programmable gate array and a memory, and is realized through a closed-loop scheduling process executed by the central processing unit. According to the method, global, dynamic and collaborative power consumption management of domestic heterogeneous chip resources is realized, and the overall energy efficiency and the operation reliability of the system are remarkably improved on the premise of ensuring the real-time performance and the performance of a vehicle-mounted task.

The invention provides a multi-environment automobile battery management method and system, and relates to the technical field of battery management, and the method comprises the steps: obtaining environment information and automobile real-time operation parameters, and carrying out the multi-scale decomposition processing, so as to extract the local influence data of all environment information; then, based on a mutual information maximization criterion, calculating a nonlinear dependency relationship between each piece of environmental information and battery consumption, and determining key environmental influence factors from the nonlinear dependency relationship; and processing the influence factors and the automobile operation parameters by using a sparse Bayesian regression model, constructing a dynamic power consumption prediction model, and performing real-time dynamic power consumption optimization. And continuously updating a power consumption distribution strategy through a depth deterministic strategy gradient algorithm to realize self-adaptive battery management. According to the invention, the operation efficiency of the battery is improved, the adaptive capacity in a changeable environment is enhanced, the power consumption distribution strategy of the automobile can be optimized in real time, and the optimal performance of the automobile under various conditions is ensured.

The invention provides a low-power-consumption scheduling method and system for an edge heterogeneous computing unit, and the method comprises the steps: constructing a resource sensing model of heterogeneous hardware, and collecting the performance parameters of a processing unit in real time; establishing a task priority evaluation model, and calculating a task priority by adopting an analytic hierarchy process based on the resource perception model and the task priority evaluation model; designing a collaborative optimization model; based on the collaborative optimization model and by adopting an improved particle swarm optimization algorithm, solving an optimal allocation scheme of tasks in the heterogeneous hardware, and dynamically adjusting the working frequency of the heterogeneous hardware; monitoring states of task execution and heterogeneous hardware in real time, judging whether resource overload or task timeout risks occur in the states or not, and if yes, triggering scheduling scheme updating. According to the method, local optimum is effectively avoided, the solution efficiency and the solution quality are remarkably improved, and the frequency-to-voltage linkage dynamic power consumption regulation and control closed loop is realized by triggering scheduling scheme updating.

The invention discloses a dynamic power consumption optimization control method based on a bidirectional DC-DC power management chip, relates to the technical field of power consumption control, and solves the problem that power consumption cannot be fully optimized and controlled due to the fact that the power consumption is easily influenced by temperature. The dynamic power consumption optimization of the bidirectional DC-DC power supply under all working conditions is realized through closed-loop control of'precise modeling-dynamic optimization-adaptive regulation and control-gradient convergence ', and the defects of a traditional control method in the aspects of loss balance, parameter drift, dynamic response and the like are effectively overcome; an efficient and reliable power supply management technical scheme is provided for the fields of new energy automobiles, energy storage systems and the like, and when temperature rise and device parameter drift are caused by long-time operation of the circuit, a duty ratio iteration adjustment mechanism is triggered. Experimental data show that the mechanism can control the loss amplification in a high-temperature environment to be within 5%, which is reduced by 15%-20% compared with a traditional scheme.

The invention relates to the technical field of chip control, and discloses a dynamic power consumption adjusting method and device for a multi-mode SOC main control chip, and the method comprises the steps: obtaining the chip load characteristics of the SOC main control chip, analyzing the load characteristics according to a preset power consumption adjusting scheme, determining a corresponding power consumption mode, and carrying out the power consumption mode adjustment. The chip load characteristics are transmitted to a cloud computing platform through a network, the cloud platform analyzes a chip user portrait based on the load characteristics, analyzes an expected behavior of the current load characteristics according to the user portrait, predicts a load demand of the SOC main control chip, matches the expected load characteristics based on a cloud strategy library, obtains an optimal adjustment strategy and adjusts a power consumption mode; the power consumption mode can be dynamically adjusted according to the actual load characteristics, the energy efficiency is improved, accurate adjustment of different use scenes is achieved through user portrait analysis, timely updating and accurate execution of strategies are ensured through the cloud platform, and the problem that in the prior art, the power consumption adjustment mode cannot achieve the optimal effect is solved.