312 results about "Dynamic power dissipation" patented technology

The invention discloses a load prediction-based solid state disk power consumption optimization method and system, and particularly relates to the technical field of solid state disks, and the method comprises the following steps: S1, data acquisition; s2, constructing and training a load prediction model; s3, load prediction; s4, power consumption optimization: optimizing the power consumption of the solid state disk by adopting a multi-objective optimized dynamic power consumption adjustment algorithm according to a load prediction result; and S5, feedback adjustment: monitoring actual power consumption and performance parameters of the solid state disk after optimization in real time, and adjusting the load prediction model and the dynamic power consumption adjustment algorithm in combination with a reinforcement learning algorithm. According to the solid state disk power consumption optimization method and system based on load prediction, a set of complete and efficient solid state disk power consumption optimization scheme is formed from load prediction model construction, dynamic power consumption adjustment algorithm design and feedback adjustment mechanism optimization; and a new technical thought and a new practice direction are expected to be provided for reducing energy consumption and improving performance of the solid state disk.

The invention relates to the technical field of chip development, and discloses a chip post-simulation verification acceleration method, system and device and a storage medium, and the method comprises the steps: collecting multi-dimensional data of a large-scale chip; collecting all module names of a given chip; establishing a mapping relation between a redundant module RTL and a corresponding gate-level netlist, ensuring that interfaces before and after replacement are completely consistent, and designing an automatic script identification and processing parameterization module; establishing a post-simulation verification environment, verifying the consistency of output responses before and after replacement, analyzing the time delay change of a key path, calculating the dynamic power consumption and static power consumption of each functional module before and after replacement, and generating a simulation verification result. According to the method, the hybrid simulation model is constructed, and part of the gate-level netlist irrelevant to the current simulation function is replaced with the RTL, so that the actual simulation scale of a chip is reduced, the problem of overlong simulation time after a large-scale integrated circuit is remarkably solved, and the simulation efficiency is effectively improved.

The invention discloses a single-chip microcomputer hierarchical dormancy control method based on dynamic power consumption prediction, and relates to the technical field of single-chip microcomputer low power consumption control, and the method specifically comprises the steps: building a mapping relation between a load current and a clock frequency; setting a dynamic dormancy threshold value; constructing a dynamic power consumption prediction model; a dormancy strategy is designed, module-level power consumption management and single-chip microcomputer function-based power consumption management are adopted, the callable frequency or the maximum operation duration of each function is distributed according to task priorities and battery residual energy consumption, and single-chip microcomputer peripherals are triggered through events and are independently awakened; and executing the sleep strategy, automatically awakening the single chip microcomputer according to a preset awakening condition, and realizing abnormity positioning and processing based on threshold comparison and power consumption monitoring in the process of executing the sleep strategy. According to the invention, module-level power consumption management and single-chip microcomputer function-based power consumption management are realized, the limitation of traditional global dormancy is broken, the need of overall reset during wakeup is avoided, and the response speed is improved while the energy consumption is reduced.

The invention belongs to the technical field of electronic design automation, and provides a dynamic power consumption optimization method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design, and determining a starting point of a specific type in the circuit design; performing backward traversal on the circuit design along a signal propagation direction from the starting point to determine circuit branch structure information and a specific type of termination point in the circuit design; starting from the termination point, establishing an ODC expression, performing forward traversal on the circuit design in an inverse signal propagation direction, and in the forward traversal process, based on the circuit branch structure information, propagating the ODC expression in the circuit design until ODC distribution of the circuit design is determined; based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. According to the method, the ODC expression can be quickly and efficiently propagated in the whole circuit design, so that a designer can conveniently optimize the dynamic power consumption through ODC distribution.

The invention discloses a gamepad energy-saving control method and system based on intelligent analysis, and the method comprises the steps: obtaining the operation monitoring information of a gamepad, and carrying out the preprocessing of the operation monitoring information of the gamepad, and obtaining the multi-mode fusion features of a target gamepad; constructing a user operation analysis model, and analyzing the operation behavior of the target user using the gamepad to obtain user operation analysis information; constructing an operation state transition matrix based on the multi-modal fusion features of the target gamepad, and predicting the operation intention of the target user; constructing an energy-saving control strategy database, acquiring energy-saving control parameters matched with the current operation scene from the energy-saving control strategy database, and establishing a dynamic regulation and control mechanism to dynamically regulate and control the energy-saving control parameters; and if the matched energy-saving control parameter combination does not exist in the energy-saving control strategy database, making an energy-saving control strategy. Intelligent energy-saving control of dynamic power consumption regulation and control is realized, so that the energy efficiency performance of the gamepad and the user experience are improved.

The invention discloses an agricultural heterogeneous multi-core SoC (System on Chip) architecture and equipment integrating vision and environmental perception. According to the architecture, a heterogeneous multi-core design is adopted, a universal CPU and an AI acceleration and preprocessing module are integrated on an on-chip system, an efficient task scheduling mechanism is combined, real-time management and control of multi-source heterogeneous tasks such as image processing, radar resolving and path planning are achieved, and the system response speed and the task execution efficiency are improved. In the aspects of communication and storage, NoC and AXI buses are adopted to cooperatively construct a high-speed data path, DDR4 and Flash mixed storage is supported, and the transmission stability of large-bandwidth data is guaranteed. The power supply and clock management module realizes modularized start and stop and energy consumption optimization through a multi-voltage domain and dynamic power consumption control technology, and is suitable for outdoor long-time operation. The IO and peripheral interface module provides abundant interfaces, and system expansibility and deployment flexibility are improved. The overall framework integrates the advantages of high integration level, high adaptability and low power consumption, and a solid calculation basis is provided for agricultural intelligent equipment.

The invention relates to the technical field of data center thermal management, and discloses a data center liquid cooling precise temperature control method and system, and the method comprises the following steps: pre-analyzing a calculation task to generate a power consumption prediction sequence; combining the power consumption prediction sequence with the real-time state information of the liquid cooling system, calculating the heat cost of the task at each candidate calculation node through a digital twin model, and selecting a target execution node according to the heat cost; inputting the power consumption prediction sequence and real-time state information into a reinforcement learning controller, and generating a composite coordination action containing a flow regulation instruction and a dynamic power consumption upper limit instruction; and cooperatively controlling the micro-fluidic execution array and the chip power consumption management unit on the target execution node according to the composite coordination action. Through prospective power consumption prediction and two-way cooperative control from the heating end and the heat dissipation end, intelligent distribution and accurate temperature control of thermal loads are achieved, temperature overshoot is effectively restrained, and the overall operation energy consumption of the data center is reduced while the system reliability is guaranteed.

The invention relates to the technical field of integrated circuit design verification, and provides a chip power consumption analysis optimization method and system, and the method comprises the steps: obtaining circuit structure information of a chip, carrying out the analysis of the circuit structure information, generating and analyzing a module topological graph and a function logic graph of a circuit, and obtaining static power consumption data and dynamic power consumption data; after a preset analysis model is input and working mode parameters are obtained, a key path in the circuit structure information is reconstructed, based on the reconstructed circuit structure information, dynamic behavior simulation is carried out on the function logic diagram again, simulation power consumption data are generated, the simulation power consumption data and the dynamic power consumption data are subjected to comparative analysis, and the simulation power consumption data are obtained. And generating a power consumption optimization scheme based on the comparison result. By acquiring and analyzing the circuit structure information of the chip, a power consumption optimization scheme is generated, the energy efficiency ratio of the chip is improved, and the problem that an optimization path is difficult to quickly generate for a complex circuit structure during positioning of a power consumption hot spot and circuit optimization reconstruction is solved.

The invention provides a chip power supply network compensation method and device, equipment, a storage medium and a program, relates to the technical field of integrated circuits, in particular to a chip and circuit design technology, can be applied to an application scene of chip test optimization, and the method comprises the following steps: determining a dynamic power consumption violation area of a current power supply network of a target chip; performing compensation priority classification on the dynamic power consumption violation area according to the voltage drop violation distribution information of the dynamic power consumption violation area to obtain a violation priority classification area; and determining a local power supply network compensation strategy of each violation priority classification area according to the compensation priority of the violation priority classification area. According to the embodiment of the invention, the efficiency and precision of chip power supply network compensation can be improved.

The invention discloses an ultra-low power consumption pyroelectric infrared human body detector and a networking control method thereof. The detector comprises a detection module, a control module, a power supply module, a communication module, an interaction module and a dynamic power consumption management module, human body infrared radiation is detected based on the pyroelectric effect, and ultra-low power consumption operation is achieved by dynamically switching working modes. The networking control method is based on a BLE Mesh protocol, a self-adaptive topology management algorithm is used for optimizing routing, and efficient networking with intelligent equipment is achieved. The system solves the problems of high power consumption, large networking delay, high false alarm rate and the like of a traditional detector, and is suitable for the fields of smart home, intelligent security and protection and the like.

The invention belongs to the technical field of chip design, and particularly relates to a method for estimating interconnection line parasitic capacitance based on integrated learning in a pre-layout stage, which can improve the accuracy of dynamic power consumption calculation in the early stage of physical design. Comprising the following steps: S1, extracting original data of a circuit and calculating physical characteristics of an interconnection line; s2, establishing a feature-capacitance label supervision training data set of the interconnection line; s3, training an interconnection line parasitic capacitance prediction model; and S4, after the training stage is ended, entering a prediction stage, and taking the physical characteristics of the interconnection line in the current design pre-layout stage as the input of an interconnection line stray capacitance prediction model to obtain predicted stray capacitance. The method is simple and easy to use, the pre-layout information and the final design result have high consistency, the accuracy of circuit power consumption calculation in the early stage of physical design can be improved, and the design period is shortened.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

The invention provides an intelligent clock gating NoC system based on AXI interconnection and a dynamic power consumption management method, and belongs to the technical field of integrated circuit design, the system is characterized in that an AXI interconnection matrix module is provided with a crossbar switch, a master port and a slave port, and the master port and the slave port are connected with the crossbar switch through an AXI bus; each router node in the 2D Mesh network module is provided with a local port and a peripheral port, and each router node is connected with an adjacent router node through the peripheral port; the intelligent clock gating module monitors the channel flow of the AXI interconnection matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls a clock signal; and the dynamic power management module adjusts the power consumption state according to the global power optimization signal and the local optimization signal. The overall power consumption of the system-on-chip is reduced, and the stability and efficiency of data transmission are enhanced.

The invention relates to the technical field of Bluetooth earphones, and discloses a Bluetooth earphone dynamic power consumption and transmission delay balance control system, which comprises a state acquisition module, a strategy generation module, a factor analysis module, a quantitative evaluation module, a parameter adjustment module and an execution control module. The state acquisition module obtains working current, data packet state and the like to construct an evaluation model; the strategy generation module generates an initial association strategy table; the factor analysis module analyzes historical data to identify interference factors; the quantitative evaluation module calculates a stability deviation index; the parameter adjusting module updates the strategy table according to the index; and the execution control module triggers rate switching. The system is further provided with a data packet comparison unit, a timestamp marking unit and the like to process data transmission conflicts, and the transmission quality is optimized through a three-dimensional transmission quality field model, a genetic algorithm and a three-level response mechanism. The system realizes dynamic balance of power consumption and transmission delay, and is suitable for the field of power consumption and transmission control of the Bluetooth headset.

The invention relates to the field of integrated circuit design, and particularly discloses a high power supply rejection ratio and low swing driving frequency-locked loop circuit and a control method thereof, a low dropout regulator is adopted to provide independent power supply lower than a main power supply voltage for a voltage-controlled oscillator, and double optimization effects are achieved. The clean power supply provided by the low dropout linear regulator effectively isolates the interference of the main power supply noise to the voltage-controlled oscillator, so that the power supply noise suppression capability of the circuit is remarkably enhanced, and the jitter of an output clock signal is greatly reduced; and on the other hand, the working voltage of the voltage-controlled oscillator is allowed and dynamically regulated and controlled to be optimized in a low range meeting the performance according to the real-time load of the voltage-controlled oscillator, so that on-demand power supply is realized, the dynamic power consumption of the voltage-controlled oscillator is reduced to the maximum extent while the output quality is not reduced, and the energy efficiency of the whole circuit under different load conditions is improved.

The invention discloses a flash memory chip test method. The method comprises the following steps: providing a plurality of flash memory chips; performing dynamic power consumption test on the plurality of flash memory chips during erasing operation to obtain power consumption values corresponding to the flash memory chips; performing outlier statistics according to the power consumption values of the plurality of flash memory chips, and determining outlier flash memory chips; and removing the outlier flash memory chips. According to the scheme, the flash memory chips with some process defects can be removed in the yield testing stage, and the quality of the flash memory chips flowing into a terminal user is guaranteed.

The invention discloses a wireless audio data real-time transmission method based on hardware synchronization, and the method comprises the steps: hardware synchronous clock generation and management: a high-precision synchronous clock generator is integrated in a wireless audio module, and a high-precision synchronous clock signal is generated and used for controlling the sending and receiving time sequence of audio data; the synchronous clock generator adopts a clock chip with low power consumption and high stability. Through a high-precision synchronous clock and timestamp embedding mechanism, the real-time performance of audio data can be ensured, delay in the data transmission process is reduced, audio transmission can be synchronous and stable, a dynamic power consumption management mechanism intelligently adjusts power consumption according to audio flow and a network state, the energy consumption of battery power supply equipment is reduced, and the power consumption is reduced. The self-adaptive network transmission method improves the cruising ability of equipment, is particularly suitable for portable equipment, can detect the network condition in real time and adjust the transmission strategy according to the network change through the self-adaptive network transmission strategy, and effectively solves the problems of network delay, packet loss and the like.

The invention discloses a domestic heterogeneous chip dynamic power consumption cooperative scheduling method oriented to a vehicle-mounted environment, and aims to solve the problem of system energy efficiency optimization caused by strict limitation of power supply and heat dissipation resources, dynamic mixing of calculation tasks and unique power consumption characteristics of domestic chips in the vehicle-mounted environment. The method is based on a vehicle-mounted heterogeneous computing platform comprising a domestic central processing unit, a field programmable gate array and a memory, and is realized through a closed-loop scheduling process executed by the central processing unit. According to the method, global, dynamic and collaborative power consumption management of domestic heterogeneous chip resources is realized, and the overall energy efficiency and the operation reliability of the system are remarkably improved on the premise of ensuring the real-time performance and the performance of a vehicle-mounted task.

The invention provides a low-power-consumption scheduling method and system for an edge heterogeneous computing unit, and the method comprises the steps: constructing a resource sensing model of heterogeneous hardware, and collecting the performance parameters of a processing unit in real time; establishing a task priority evaluation model, and calculating a task priority by adopting an analytic hierarchy process based on the resource perception model and the task priority evaluation model; designing a collaborative optimization model; based on the collaborative optimization model and by adopting an improved particle swarm optimization algorithm, solving an optimal allocation scheme of tasks in the heterogeneous hardware, and dynamically adjusting the working frequency of the heterogeneous hardware; monitoring states of task execution and heterogeneous hardware in real time, judging whether resource overload or task timeout risks occur in the states or not, and if yes, triggering scheduling scheme updating. According to the method, local optimum is effectively avoided, the solution efficiency and the solution quality are remarkably improved, and the frequency-to-voltage linkage dynamic power consumption regulation and control closed loop is realized by triggering scheduling scheme updating.

The invention discloses a dynamic power consumption optimization control method based on a bidirectional DC-DC power management chip, relates to the technical field of power consumption control, and solves the problem that power consumption cannot be fully optimized and controlled due to the fact that the power consumption is easily influenced by temperature. The dynamic power consumption optimization of the bidirectional DC-DC power supply under all working conditions is realized through closed-loop control of'precise modeling-dynamic optimization-adaptive regulation and control-gradient convergence ', and the defects of a traditional control method in the aspects of loss balance, parameter drift, dynamic response and the like are effectively overcome; an efficient and reliable power supply management technical scheme is provided for the fields of new energy automobiles, energy storage systems and the like, and when temperature rise and device parameter drift are caused by long-time operation of the circuit, a duty ratio iteration adjustment mechanism is triggered. Experimental data show that the mechanism can control the loss amplification in a high-temperature environment to be within 5%, which is reduced by 15%-20% compared with a traditional scheme.

The invention discloses a processor chip power consumption test method and test system, and belongs to the technical field of processor chips, and the method comprises the steps: collecting and processing the real-time test data of a processor chip, and determining the feature test data of the processor chip; training a processor chip power consumption test prediction model, analyzing the processor chip feature test data, predicting processor chip power consumption, and determining a processor chip power consumption prediction result; and displaying the power consumption test condition of the processor chip in a visual form, managing and controlling the processor chip, and adjusting the set dynamic power consumption threshold value by using the dynamic adjustment coefficient. The problem that the power consumption test effect of the processor chip is poor due to the fact that the power consumption characteristic of the processor chip cannot be comprehensively evaluated and the processor chip cannot be effectively controlled in the prior art is solved. The power consumption characteristic of the processor chip can be comprehensively evaluated, the processor chip can be effectively controlled, and the power consumption test effect of the processor chip can be improved.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

The invention discloses a lightweight MQTT heterogeneous protocol conversion gateway architecture system and method, and belongs to the technical field of protocol conversion, and the system comprises a core board which is used for operating a real-time operating system; the multi-protocol hardware interface module is integrated on the core board; the multi-protocol hardware interface module comprises an RS-232 / 485 serial port, an RJ45 Ethernet interface, a USB (Universal Serial Bus) interface and a WiFi (Wireless Fidelity) module; the protocol converter is arranged on the core board in a layered manner and is used for realizing dynamic conversion between PROFIBUS-DP and Modbus protocols on each layer of the OSI model; the communication architecture on the core board comprises a message publishing or subscribing agent mechanism; and the power management module is connected with the core board and is used for dynamic power consumption adjustment and a power-off protection mechanism. According to the method, intelligent mapping between a physical address, namely a PROFIBUS-DP station address and an IP address, is established, plug and play of field equipment is supported, and the deployment time is shortened from several hours traditionally to 10 minutes.

The invention provides a spatial heterogeneous computing resource scheduling method and device based on dynamic power consumption budget, a terminal, a medium and a product. The method is applied to task initiating equipment, and comprises the following steps: acquiring a current to-be-executed spatial computing task, and determining a current dynamic spatial heterogeneous computing group; obtaining the current power consumption budget score and equipment capability information of each computing equipment in the computing group; and selecting one or more optimal computing devices from the computing devices by utilizing a multi-objective optimization scheduling algorithm according to the spatial computing task and based on the obtained current power consumption budget score and the device capability information of the computing devices, so that the one or more optimal computing devices execute the spatial computing task. Through power consumption budget scoring and a multi-objective optimization scheduling algorithm, the method effectively prevents a low-power or energy-shortage device from undertaking a high-energy-consumption task, thereby remarkably reducing energy consumption, prolonging the effective service time of the computing device, and improving the stability.

The invention relates to the technical field of electronic timers, in particular to an environment self-adaption low-power-consumption management system and method for an electronic timer, and the system comprises an environment sensing array, a physical state evaluator, a dynamic power consumption strategy generator, a closed loop execution and calibration unit and a self-adaption compensator. According to the method, multi-dimensional environment parameters are dynamically collected, a coupling model representing the relation between frequency deviation and compensation power consumption is constructed, combined regulation and control parameters are generated through multi-target optimization by combining the residual electric quantity of equipment and a timing error accumulated value, hardware execution is driven, operation deviation is monitored in real time, and strategy self-adaptive iterative optimization is achieved through a feedback closed loop. According to the invention, the pain point that the precision and the power consumption of a traditional electronic timer are mutually restricted is effectively solved, and the equipment environment adaptive capability, the endurance time and the full life cycle operation stability are greatly improved.

The invention provides a dual-conversion gain reading circuit, a reading method and an image sensor, and the circuit comprises a comparison module which carries out the pre-comparison of a high-gain photosensitive signal and a ramp signal, so as to obtain a pre-comparison result, comparing the low-gain reset signal, the high-gain reset signal, the high-gain photosensitive signal and the low-gain photosensitive signal with a ramp signal to output corresponding comparison signals; and the counting module selects a counting mode according to the pre-comparison result to count the comparison signals so as to output data signals. A comparison module is used for pre-comparing a high-gain photosensitive signal with a ramp signal, and a counting module is used for selecting a corresponding counting mode for counting quantization according to a pre-comparison result, so that the corresponding counting mode can be adaptively selected according to a voltage difference value between a high-gain reset signal and the high-gain photosensitive signal; therefore, the dynamic power consumption of the counting module is effectively reduced, the overall power consumption of the reading circuit is reduced, and the problem that an existing dual-conversion gain reading circuit is large in dynamic power consumption is solved.

The invention relates to the technical field of LED lighting control, and discloses an intelligent LED lamp strip power supply control system with an automatic voltage jump function, which comprises an intelligent control power supply, a series topology LED lamp strip and a plurality of cascaded constant current voltage division control chips, and further comprises a topology discovery and automatic addressing module for detecting the total node number and allocating addresses; the cascade voltage division and dynamic power consumption balancing module is used for calculating a target voltage division value according to the total node number; the power and data cooperative transmission module broadcasts a target partial voltage value on a power supply bus and realizes two-way communication; the node localization constant-current driving module is used for the chip to receive the target voltage division value, adjust the actual voltage division value and drive the LED in a constant-current mode; and the intelligent fault diagnosis and controllable bypass module is used for monitoring a fault of the chip, reporting a fault containing an address and responding to an instruction to activate a bypass. According to the invention, the cascade voltage division and dynamic power consumption equalization module is adopted, so that the technical effects of consistent power and highly uniform brightness obtained by all LED nodes in an ultra-long distance are achieved.

The invention provides an intelligent temperature control system and method based on chip heat energy guiding. The method comprises the steps of obtaining running state information of a target chip set; the working mode of the loop heat pipe is determined according to the operation state information of the target chip set, and stepped energy recovery is conducted on conduction heat of the loop heat pipe through the recovery heat pump; thermal state information of the target chipset and energy recovery information of the recovery heat pump in different historical time windows are obtained, correlation verification analysis is carried out according to the thermal state information and the energy recovery information, and an intermittent boiling threshold value of the loop heat pipe is determined; acquiring operation instruction stream data of the chip, and performing dynamic power consumption prediction according to the operation instruction stream data to obtain a dynamic power consumption prediction value; when the dynamic power consumption predicted value is higher than the intermittent boiling threshold value, the liquid return rate of the loop heat pipe is adjusted based on the dynamic power consumption predicted value, the liquid return rate in the heat transfer process can be controlled according to dynamic power consumption prediction, and the heat energy guiding and recycling efficiency is improved.

The invention relates to the technical field of wearable equipment and chip power consumption management, and discloses a storage chip low power consumption management method and system for AI glasses, and the method comprises the steps: obtaining multi-application concurrent operation access request data and an instantaneous current change value; according to the access request data, carrying out access request time interval calculation to obtain concurrent access density distribution feature data; according to the instantaneous current change value and the concurrent access density distribution characteristic data, carrying out association binding to obtain access request characteristic data; and performing conflict request identification and risk assessment according to the access request feature data, and performing dynamic power consumption parameter adjustment in combination with real-time power consumption data to obtain a storage chip power consumption distribution scheme. The method can solve the technical problem of low power consumption management efficiency.

The invention discloses a random question number generator and method suitable for a question and answer mode watchdog, and belongs to the technical field of integrated circuit safety. Comprising an on-chip high-frequency oscillation source, an enabling controller, a low-power-consumption controller, a pseudo-random number generator and a random code hopping device. According to the method, an external dog feeding signal is used for triggering, a non-reproducible hopping code value is generated by using different sources of clock sources and physical deviation of signal transmission, a pseudo-random number generator is controlled to operate within a random duration, and a low-power-consumption state is entered after a final random problem number is output and latched. Through hardware-level entropy source enhancement and dynamic power consumption management, the predictable potential safety hazard of the traditional pseudo-random number sequence is fundamentally solved, and the balance of high randomness, high attack resistance and low power consumption is realized at low cost.