Method and device for designing standard cell library and integrated circuit

A technology of standard cell library and design method, applied in computing, electrical digital data processing, special data processing applications, etc., can solve the problems of waste of dynamic power consumption and insufficient use of clocks, etc., and achieve reduction of dynamic power consumption, The effect of reducing the amount of clock activity and reducing the number of clock transitions

Inactive Publication Date: 2009-09-23
北京芯汇中秀电子技术有限公司
View PDF0 Cites 22 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0019] In the traditional standard cell library, the basic sequential logic unit uses a single-edge trigger, and its flip is only triggered by a certain edge (rising edge or falling edge) of the clock, and the

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method and device for designing standard cell library and integrated circuit
  • Method and device for designing standard cell library and integrated circuit
  • Method and device for designing standard cell library and integrated circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0080] Reducing the dynamic power consumption in the circuit can be considered from two aspects: first, try to control the clock jumping activity of each node in the chip that does not work for the sequential logic function, and block its penetration into the circuit, thereby inhibiting its corresponding The dynamic power consumption; the second aspect, should try to improve the utilization rate of each clock jump activity, so that each jump, even the front and rear edges (rising edge and falling edge) of each jump can be used to realize the logic of the chip. Functional services, so that the number of clock jumps required to complete the same logic function is reduced, so as to achieve the purpose of reducing the amount of clock activity and reducing the dynamic power consumption of the circuit.

[0081] The embodiment of the present invention considers from the above-mentioned second aspect, in order to reduce the dynamic power consumption of the circuit, under the premise of...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a method and a device for designing a standard cell library. The method comprises a step of designing a common standard cell, and also comprises a step of designing a double-edge flip-flop cell, and the step of designing the double-edge flip-flop cell comprises: when determining the type of the standard cell, adding the double-edge flip-flop cell to the standard cell type; designing a schematic diagram of the double-edge flip-flop cell; and designing a diagram of the double-edge flip-flop cell. A mold of the double-edge flip-flop cell is established, and the method for establishing the mold comprises the following steps of: establishing a rising edge comprehensive library and a falling edge comprehensive library for the double-edge flip-flop; and establishing a double-edge flip-flop simulated library for the double-edge flip-flop. The invention also discloses a method and a device for designing an integrated circuit. Due to the method and the device, the rising edge and the falling edge for each jump of the clock signal can serve the logical function of a chip, so that the jumping frequency of the clock, needed to complete the same logical function, is reduced, and the dynamic energy consumption of the circuit is also lowered.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a standard cell library and an integrated circuit design method and device. Background technique [0002] The design of CMOS (Complementary Metal-Oxide Semiconductor, Complementary Metal-Oxide Semiconductor) digital IC (Integrated Circuit, integrated circuit) can be divided into full-custom design and semi-custom design. Full-custom design is a transistor-level design approach where all components, interconnects, and layouts of a circuit are designed directly. Semi-custom design is further divided into designs based on gate arrays and standard cell libraries. [0003] The design based on the standard cell library refers to designing some basic logic units (such as gate circuits, multi-way switches, flip-flops, etc.) in the circuit design according to the principle of optimal design, and storing them in the standard cell library as standard cells. When designing an integ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F17/50
Inventor 罗晋马亮赵劼张现聚倪伟新
Owner 北京芯汇中秀电子技术有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products