97 results about "Noise tolerance" patented technology

A system is disclosed for detecting and calculating the level of ambient and / or environmental noise, such as electromagnetic interference generated by electric power lines, ambient lights, light dimmers, television or computer displays, power supplies or transformers, and medical equipment. In some embodiments, the system performs frequency analysis on the interference signal detected by light photodetectors and determines the power of the interference signal concentrated in the analyzed frequency bands. The worst-case interference level can be determined by selecting the maximum from the computed power values. In some embodiments, the determined interference signal power can be compared with the noise tolerance of a patient monitoring system configured to reliably and non-invasively detect physiological parameters of a user. The results of the comparison can be presented to the user audio-visually. In some embodiments, the system can be used to perform spot check measurements of electromagnetic interference.

A system and method for increasing the accuracy of time delay estimates of signals propagating through an environment. The system includes one or more sensors for receiving a plurality of signals, and a time delay estimator for measuring time delays between multiple pairs of signals. At least some of the multiple pairs of signals are received and measured at different points in time. The system further includes a data analyzer for analyzing time delay estimation data, for generating a statistical distribution of time delay estimates from the data, and for calculating a statistical estimate of time delay from the distribution. By increasing the number of signals employed by the system, the accuracy of the time delay estimation is increased. Further, by calculating the median or the mode of the statistical distribution, noise tolerance is improved.

A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.