Subthreshold SRAM (Static Random Access memory) unit circuit capable of increasing read noise tolerance and writing margin

Abstract

The invention discloses a subthreshold SRAM (Static Random Access memory) unit circuit capable of increasing read noise tolerance and writing margin, first PMOS transistor MP1, first NMOS transistor MN1, third NMOS transistor MN3 and third PMOS transistor MP3 form a first inverter, second PMOS transistor MP2, second NMOS transistor MN2, fourth NMOS transistor MN4 and fourth PMOS transistor MP4 form a second inverter, the first inverter and the second inverter are used for storing opposite data, namely data of memory point Q and memory point QB; seventh NMOS transistor MN7 and eighth NMOS transistor MN8 are used for controlling read operation, the third NMOS transistor MN3, the third PMOS transistor MP3, the fourth NMOS transistor MN4 and the fourth PMOS transistor MP4 are used for improving writing capability. The SRAM (Static Random Access memory) unit circuit improves the ability of writing data, a new writing operation method is used, so that the data is easy to write in a unit, the write margin is greatly improved; meanwhile, the unit circuit adopts a read-write separation structure, so that the read noise tolerance reaches to the maximum, and the unit circuit can works in a subthreshold zone, and reduces power consumption.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a sub-threshold SRAM storage unit circuit which improves read noise tolerance and write margin. Background technique [0002] Sub-threshold design is widely used because of its ultra-low power consumption, especially for high-density integrated circuits such as SRAM. However, as the power supply voltage decreases, the circuit enters the sub-threshold region, and the memory cell is more significantly affected by process fluctuations. As a result, the stability of the memory cell is reduced or even errors occur, which imposes higher requirements on the design of the memory cell. [0003] At present, the mainstream unit of SRAM is 6T structure, such as figure 1 The schematic diagram of the circuit structure of the traditional 6T SRAM storage unit is shown. In order to make the 6T unit more stable, the size of the tube can be optimized, but the read and write ability of ...

AI Technical Summary

Problems solved by technology

However, as the power supply voltage decreases, the circuit enters the sub-threshold region, and the memory cell is more significantly affected by process fluctuations. As a result, the stability of the memory cell is reduced or even errors occur, which has higher requirements for the design of the memory cell.

[0003] At present, the mainstream unit of SRAM is 6T structure, such as figure 1 Shown is a schematic diagram of the traditional 6T SRAM storage unit circuit structure. In order to make the 6T unit more stable, the size of the tube can be optimized, but the read and write capabilities of the optimized 6T tube can only be improved to a limited extent.

Some tubes are designed with high read stability, but write stability is relatively poor. In order to work in the sub-threshold region, write assist technology must be used, which will undoubtedly increase the complexity of peripheral circuits.

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