156 results about "Asic technology" patented technology

The present disclosure provides a fast voltage regulation control circuit of an LDO, and relates to the technical field of integrated circuits, the LDO comprising an input voltage terminal, a power tube, an LDO self-control circuit and an output voltage terminal, the power tube being coupled between the input voltage terminal and the output voltage terminal; the fast voltage regulation control circuit is coupled with the control electrode of the power tube to control the LDO to switch between a fast voltage regulation mode and a self-voltage regulation mode; when the LDO enters the self-voltage regulation mode, the gate voltage applied to the control electrode of the power tube comprises a first gate voltage applied to the control electrode by the LDO self-control circuit; when the LDO enters the fast voltage regulation mode, the gate voltage applied to the control electrode of the power tube comprises the first gate voltage applied to the control electrode by the LDO self-control circuit and a second gate voltage applied to the control electrode by the fast voltage regulation control circuit, so that the gate voltage of the control electrode of the power tube is equal to the sum of the first gate voltage and the second gate voltage, and fast voltage regulation of the LDO output is realized in the fast voltage regulation scenario.

This application discloses an automatic calibration circuit and method for mismatch compensation current of a phase-locked loop (PLL) charge pump, relating to the field of integrated circuit technology. The calibration circuit includes: a frequency and phase detector, a charge pump, an XOR module, a filter capacitor, a digital-to-analog converter (DAC) module, and a digital logic state machine. The first output terminal of the frequency and phase detector is connected to the first input terminal of the charge pump and the first input terminal of the XOR module, respectively. The second output terminal of the frequency and phase detector is connected to the second input terminal of the charge pump and the second input terminal of the XOR module, respectively. The output terminal of the XOR module is connected to the first terminal of the filter capacitor and the input terminal of the DAC module, and the second terminal of the filter capacitor is grounded. The output terminal of the DAC module is connected to the input terminal of the digital logic state machine, and the output terminal of the digital logic state machine is connected to the third input terminal of the charge pump. The output terminal of the charge pump is used to connect to the input terminal of the low-pass filter in the PLL. This application can compensate for the mismatch current of the charge pump in real time.

This invention discloses a starting point control method based on twin logic, relating to the field of integrated circuit technology. The method includes: after the chip is powered on, the logic generation circuit begins to establish the state of the target logic channel, and the twin logic channel internally monitors the establishment of this state synchronously; when the twin logic channel determines that the target logic state has been established, it outputs a starting point latch signal and generates a starting point control signal, triggering a timing circuit to sequentially generate a logic lock signal and a shutdown signal; the logic lock signal securely locks the target logic to the latch matrix, and the shutdown signal subsequently shuts down the logic generation circuit. This invention uses "logic-driven timing" instead of the traditional "power-driven timing," truly binding the timing starting point to the physical establishment state of the module, fundamentally avoiding timing races and locking errors; and it can adapt to process and temperature fluctuations, significantly improving system reliability while precisely reducing additional power consumption.

The application is suitable for the field of integrated circuit technology, and provides a single-wire parallel data transmission method and a chip. The method comprises the following steps: receiving protocol data through an input end; the protocol data comprises a start code, a data segment and an end code. A current counter value of a built-in counter is extracted, and the built-in counter counts every time a single data segment in the data segment is received. When it is determined by a first comparator that the current counter value is equal to a preset counter value in a preset counter value storage module, a single data segment received is saved as valid data in a cache latch, and the built-in counter continues to count. When the end code is received, the valid data in the cache latch is stored in a data latch, and the valid data is validated, and the built-in counter is reset to an initial state. The problem that parallel input control and single-wire serial protocol cannot be compatible can be solved.

This application discloses a method and electronic device for detecting transmission parameters of through-silicon vias (TSVs), applied in the field of integrated circuit technology. The method includes: determining whether the total length of the TSV to be tested is greater than a preset first length; if so, dividing the TSV into multiple via segments such that the length of each segment is no greater than the first length; if not, treating the TSV as a TSV composed of single-segment vias; for each via segment, obtaining the pad capacitance, via pillar capacitance, anti-pad capacitance, via inductance, and via resistance of the via segment using preset parameter calculation rules, and constructing an equivalent circuit model of the via segment; cascading the equivalent circuit models of each via segment of the TSV to form an equivalent circuit model of the TSV, and performing transmission parameter detection on the TSV. Applying the scheme of this application can effectively determine the transmission parameters of the TSV, improving efficiency and ensuring the accuracy of the scheme.

Embodiments of the present disclosure provide a leakage compensation circuit, a chip and an electronic device, and belong to the technical field of integrated circuits. The leakage compensation circuit comprises an output stage circuit, a first sampling circuit, an operational amplifier circuit and a second sampling circuit. The operational amplifier circuit comprises an operational amplifier output stage circuit and an operational amplifier first stage circuit which are coupled to each other. The first sampling circuit samples the leakage current of the output stage circuit to obtain a first sampling current, and provides the first sampling current to the operational amplifier output stage circuit through a first node. The second sampling circuit samples the current of the operational amplifier output stage circuit to obtain a second sampling current, and provides the second sampling current to the output stage circuit through a second node to compensate for the leakage current of the output stage circuit. The operational amplifier first stage circuit clamps the voltage of the first node and the second node.

The application relates to the technical field of integrated circuits, in particular to a popular C-2C structure multi-section capacitor array and application thereof. The application comprises a capacitor array, a bridging capacitor, a redundant capacitor, an input stage and an output stage, wherein the capacitor array comprises n sections, each section comprises S-bit capacitors arranged in parallel, all the lower plates of the capacitors of the capacitor array are connected with the input stage, the bridging capacitor is arranged between the S-bit capacitors of the n sections of the capacitor array, the first section of the capacitor array is connected with the redundant capacitor, and the nth section is connected with the output stage. The application relieves the conflict between the effective number of bits and the chip area of the high-precision analog-to-digital converter and digital-to-analog converter capacitor array, and simultaneously improves the problem of traditional C-2C structure capacitor matching.

The application discloses an aging-aware precision reconfigurable logic synthesis method and system, and belongs to the technical field of integrated circuit EDA. The application aims to solve the problems of limited optimization space, introduced error from the beginning and lack of aging modeling in the existing aging-aware synthesis. The application constructs an aging standard cell library, iteratively applies constant replacement to the original circuit to generate multiple approximate candidate circuits, and then constructs a precision reconfigurable circuit composed of reconfigurable modules, which dynamically switches between accurate mode and approximate mode. Through aging-aware timing modeling, a power function model of gate delay with running time is established, and the aging continuity during mode switching is processed. The accurate mode life and the approximate mode remaining life are predicted, and the circuit with the highest score is automatically selected according to the score function. The application can improve the circuit life by about 9.5 times with an additional area overhead of about 3.72% under the premise of meeting the error constraint, which significantly enhances the long-term reliability of digital circuits.

The application discloses a memory chip processing method and a memory chip, and relates to the technical field of integrated circuits. The memory chip processing method comprises the following steps: providing a memory material and a control crystal grain, wherein the memory material comprises a plurality of memory crystal grains; packaging the memory crystal grains with a first substrate, so that the plurality of memory crystal grains are connected with the first substrate, and a first packaging body is obtained; cutting the first substrate, so that the plurality of memory crystal grains are separated, and a plurality of semi-finished memory modules are obtained, wherein each memory module comprises a memory crystal grain and a sub-substrate arranged on one side of the memory crystal grain, and the sub-substrate is divided from the first substrate; and packaging at least one memory module and the control crystal grain on a second substrate, so that a finished memory chip is obtained, and the control crystal grain is connected with the at least one memory module through a circuit. The memory chip processing method can improve the accuracy of testing and reduce the loss of testing of the memory chip.

The application discloses a tracking lock type maximum power point tracking circuit and an implementation method thereof, which comprises a rectifier circuit, a control circuit, a step-down-step-up converter control circuit and a step-down-step-up converter. The rectifier circuit is used for converting input alternating current energy into direct current energy. The control circuit is used for judging the length of current inductance demagnetization time, adjusting the current inductance demagnetization time, realizing indirect detection of inductance current zero-crossing point, and generating a switch timing control signal. The step-down-step-up converter control circuit is used for generating a first switch tube driving signal and a second switch tube driving signal. The step-down-step-up converter is used for adjusting input impedance according to the first switch tube driving signal and the second switch tube driving signal, and realizing maximum power point tracking. The application can realize adaptive locking of the maximum power point under different vibration frequencies and different open circuit voltages, improve the tracking speed of the circuit when the input changes, and can be widely applied to the technical field of integrated circuits.

This application relates to the field of analog integrated circuit technology and discloses a voltage reference circuit suitable for high power supply voltages. The circuit replaces the Zener diode pre-regulation architecture with a voltage-limiting loop biased by a positive temperature coefficient current source. A stable low power supply voltage is generated by forming a negative feedback loop through a high-voltage regulating transistor and a feedback sampling transistor. A reference voltage is generated by subtracting the gate-source voltages of two sets of transistors with different threshold voltages. Furthermore, it incorporates a frequency-band coordinated power supply rejection ratio enhancement module, a pre-charging and automatic loop exit startup acceleration module, and a dual-branch complementary control trimming module. This circuit achieves a comprehensive performance of small area, low power consumption, high power supply rejection ratio, and fast startup.

This invention belongs to the field of integrated circuit technology and discloses a dual-transformer load-gain-flat tunable low-noise amplifier, including an input matching circuit, a two-stage common-source current-multiplexed amplifier circuit, and an output matching circuit. It also includes a first transformer topology circuit, a second transformer topology circuit, a first adjustable bias voltage source, and a second adjustable bias voltage source. The two-stage common-source current-multiplexed amplifier circuit includes a first-stage common-source amplifier circuit and a second-stage common-source amplifier circuit. The first transformer topology circuit serves as the load for the first-stage common-source amplifier circuit; the second transformer topology circuit serves as the load for the second-stage common-source amplifier circuit. The low-noise amplifier of this invention features high gain, high linearity, and high gain flatness, while achieving a wide tuning range of gain adjustment. Furthermore, it achieves good gain flatness and good input-output matching at different gain adjustment levels.

The application provides an emergency power supply starting circuit, and belongs to the technical field of integrated circuits, and comprises a high-voltage input end for providing a high-voltage input; a voltage storage circuit comprising a first resistor R1 and a first capacitor C1, and an input end connected with the high-voltage input end; a comparator circuit comprising a comparator U1, a positive input end connected with an output end of the voltage storage circuit, a negative input end for providing a low-voltage input, and an output end connected with a control switch group; and the control switch group is connected with a control chip; the comparator U1 in the comparator circuit is reversed according to the voltage storage circuit and the low-voltage input, controls on-off of the control switch group, and supplies power to the control chip for starting, so that the problem that the existing emergency power supply starting circuit has high power consumption for high-voltage power taking and has high requirements on the control chip is solved.

This application discloses a time-interleaved ADC with redundant channels and its control method, relating to the field of integrated circuit technology. The time-interleaved ADC includes multiple analog signal input selection switches, multiple sub-ADCs, and an output data selector. Each sub-ADC is divided into a sampling conversion channel and a redundant channel. The sampling conversion channel is used to convert analog signals into digital signals, and the redundant channel is set to be in a non-data conversion state when the sampling conversion channel is working. Each sub-ADC is used to convert analog input signals into corresponding branched digital signals. The output data selector is used to combine the branched digital signals into a total digital signal by time-division multiplexing. This application improves the dynamic range performance of the time-interleaved ADC and eliminates the data dependency problem of ultra-high-speed ADCs by adding redundant sub-ADC channels.

The application relates to a self-aligned barrier structure forming method and a semiconductor structure, and relates to the technical field of integrated circuits. The self-aligned barrier structure forming method of the application forms a protective sidewall for protecting the line width of a barrier pattern on the sidewall of the barrier pattern before wet etching. In the wet etching process, the protective sidewall delays or avoids the contact between a wet etchant and the barrier pattern, thereby improving the problem of the lateral etching of the wet etchant on the barrier pattern, improving the line width precision of the formed self-aligned barrier structure, improving or eliminating the leakage problem caused by the reduction of the line width of the self-aligned barrier structure, and improving the stability of a device. The etching process or the wet etchant does not need to be changed, the current manufacturing process of the self-aligned barrier structure has good compatibility, the process is simple, and the cost is low.

The application relates to the technical field of integrated circuits, and provides a configurable reset device, a multi-chip reset system, an electronic device and a reset control method, which comprise a local reset source configured to generate a local reset signal; an external reset input interface configured to receive an external upstream reset signal; a configuration sensing unit configured to acquire working mode configuration information; a reset arbitration selector configured to determine an initial reset signal from the local reset signal and the upstream reset signal according to the working mode configuration information; and a reset output driving unit configured to selectively transmit a target reset signal generated based on the initial reset signal to a downstream node according to the working mode configuration information. The configurable reset device based on the working mode configuration information is integrated in a chip die to realize flexible routing of the reset signal in a multi-chip system and dynamic reconstruction of the reset role of a single chip die, and the system design flexibility is improved.

This invention belongs to the field of integrated circuit technology, specifically relating to an LDO circuit that achieves precise zero-point control through Cascode compensation. The circuit includes a first-stage error amplifier, a second-stage buffer, a third-stage output power transistor, a feedback circuit, and a compensation module for precise zero-point control. By employing a unique controlled resistor combined with Cascode compensation technology, this invention achieves precise zero-point tracking of the output power transistor's load current changes during compensation. This solves the core problem of difficulty in controlling the Q-value of the conjugate pole under heavy loads in Cascode compensation, which leads to low bandwidth and slow output transient response.

The application belongs to the technical field of aerospace electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system resisting single event upsets, a double-layer error correction method of "bit-symbol" based on RS decoding operator error correction of a finite field algebra on the basis of a "two out of three" majority voting logic, which can correct single particle independent upsets and multiple copy common mode failures at the same time, and solve the traditional TMR error locking problem. Meanwhile, when configuration data is written into a non-volatile memory, a cross-sector spatial staggered dispersion storage mechanism is introduced, so that the symbols in the same RS code word are separated as much as possible in the physical position, so as to convert the aggregation physical damage into dispersed symbol level errors.

The application discloses an analog-to-digital converter integrating ReLU and maximum pooling based on time quantization, and belongs to the technical field of integrated circuits.The analog-to-digital converter comprises a threshold voltage initialization module, a voltage sampling and holding module, a constant current integration module, an integration capacitor module, a comparator module, a digital logic module and a counter module.It initializes the comparator input to a configurable ReLU threshold value, sequentially processes an input voltage sequence, controls the charging of the integration capacitor by the constant current and the counting of the counter by the comparator comparison result, and only performs operations on effective peak signals that exceed the threshold value and are greater than the current holding voltage.The application deeply integrates the three functions of ReLU activation, maximum pooling and time domain analog-to-digital conversion in a single circuit, has the advantages of small area, high energy efficiency, low delay, strong anti-interference and flexible parameter configuration, and is especially suitable for edge side storage-in-computing artificial intelligence applications.

The application discloses a wafer-level chip, a chip system, an electronic device and a communication method, and relates to the technical field of integrated circuits. The wafer-level chip comprises a reconfigurable computing wafer, a cache storage wafer and an interconnection communication wafer which are stacked in sequence, and adjacent wafers are directly bonded wafer-to-wafer; the interconnection communication wafer comprises a photonic logic circuit, the cache storage wafer comprises an optical communication cache unit, and the optical communication cache unit is bonded with the photonic logic circuit; the optical communication cache unit caches data packets to be sent written by the reconfigurable computing wafer; the photonic logic circuit reads the data packets to be sent from the optical communication cache unit and converts the data packets to optical signals and sends out the optical signals; and / or the photonic logic circuit receives optical signals and converts the optical signals to electrical signals and writes the electrical signals into the optical communication cache unit; the optical communication cache unit caches the electrical signals and informs the reconfigurable computing wafer to read the electrical signals.

This invention discloses a method and apparatus for predicting the performance degradation of integrated circuit power supplies, relating to the field of integrated circuit technology. The method includes: smoothing and denoising the first health index data of the collected sample power supply using a Kalman filter algorithm to obtain a historical health index dataset; truncating the historical health index dataset into multiple first data sequences of preset window lengths, determining the true remaining service life label corresponding to each first data sequence, and generating a supervised learning dataset; determining the initial parameters of an LSTM-Attention prediction model based on a particle swarm optimization algorithm and the supervised learning dataset; iteratively training the model to obtain a target LSTM-Attention prediction model; and predicting the remaining service life of the collected second health index data of the power supply to be monitored based on the target LSTM-Attention prediction model, enabling early warning and switching processing of the power supply before a serious fault occurs.

The application discloses a short circuit detection circuit and a buck-boost converter, and belongs to the technical field of integrated circuits. The short circuit detection circuit comprises a first pull-up circuit, a second pull-up circuit, a pull-down circuit and a detection circuit. The first pull-up circuit is connected with the positive electrode of a voltage output end, is used for being turned on when four switch tubes are all turned off, and is used for increasing the voltage of the voltage output end. The second pull-up circuit is connected with two switch nodes respectively, is used for being turned on when the voltage of the voltage output end is increased to a target voltage, and is used for providing the same voltage to the two switch nodes. The pull-down circuit is connected with the two switch nodes and the detection circuit respectively, is used for being turned on when the voltage of the voltage output end is increased to the target voltage, and is used for providing a node voltage to the detection circuit. The detection circuit is used for outputting a detection result of whether the four switch tubes are short-circuited according to the node voltage. The application can perform short circuit detection on the switch tubes, improves the reliability and safety of a converter system, and has a simple circuit structure.

This invention relates to the field of integrated circuit technology, and in particular to an FPGA prototype verification system for a 16-channel clock-interleaved ADC, comprising a host computer and a verification board connected thereto; the verification board has an FPGA core board in the center and 16 ADC acquisition modules arranged compactly around it, the ADC acquisition modules being connected to the FPGA core board via a JTAG interface; the ADC acquisition module includes an ADC module and a clock generation module and a power supply module connected thereto; this invention innovatively introduces a hardware-level correction mechanism based on programmable phase-locked loop phase modulation, effectively reducing the complexity and logic resource overhead of subsequent digital domain signal processing.

This invention provides a two-dimensional lateral heterojunction transistor, its fabrication method, and a phase-locked loop circuit, applicable to the field of integrated circuit technology. The transistor's bottom-to-top structure is as follows: substrate – lateral heterojunction channel layer – insulating layer, two sources and a shared drain – two gates. In this structure, the two gates are primarily used to acquire corresponding charging and discharging signals. When a charging signal is acquired, the current from the corresponding source flows through the P-type channel to the shared drain for charging. When a discharging signal is acquired, the current from the shared drain flows through the N-type channel to the corresponding source for discharging. However, when both charging and discharging signals are acquired simultaneously, due to the lateral heterojunction structure of the channel layer itself, the source current flows through the channel layer to the other source, thus preventing charging and discharging operations. Therefore, this structure effectively avoids the performance impact caused by current mismatch.

A programmable clock network module and array, relating to integrated circuit technology, are disclosed. The module comprises a first clock network unit, a second clock network unit, and a drive test unit. The programmable clock network module has two connection terminals in each of the up, down, left, and right directions. This invention features testability, low skewness, low duty cycle loss, low power consumption, and improved clock jitter.

This invention relates to the field of integrated circuit technology, specifically to an encoding representation method suitable for analog integrated circuit topology generation and parameter optimization. The method includes the following steps: encoding the analog integrated circuit; converting the circuit encoding into an adjacency matrix to represent circuit connection relationships; extending the encoding to support analog integrated circuit topology generation; and extending the encoding to support analog integrated circuit parameter optimization. This encoding representation method for analog integrated circuit topology generation and parameter optimization, while fully representing the analog integrated circuit, proposes an adjacency matrix to represent the circuit topology structure and serve as the input and output of the topology generation algorithm. It is applicable to analog integrated circuit topology generation and parameter optimization, and can fully represent the information required for circuit topology generation and parameter optimization. This invention has the advantages of strong integration integrity, support for mutual conversion with netlists, and adaptability to circuit topology generation and parameter optimization.

This invention discloses a power analysis self-healing control method and apparatus for integrated circuit power supplies, relating to the field of integrated circuit technology. The method includes: collecting detection data of the power supply to be evaluated; extracting features from the detection data to obtain a multi-dimensional feature data sequence; inputting the multi-dimensional feature data sequence into a pre-trained target network model to predict the power supply parameter degradation prediction result; determining the PWM control parameter adjustment amount based on the power supply parameter degradation prediction result; generating a self-healing control command based on the PWM control parameter adjustment amount and the power supply parameter degradation prediction result, and outputting the self-healing control command; the power supply system to be evaluated responds to the self-healing control command by adjusting the PWM control parameters. This method provides early identification of power supply faults and dynamic self-healing control of the power supply, thus effectively avoiding equipment downtime for maintenance and reducing equipment maintenance costs.