1154 results about "Asic technology" patented technology

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

The invention discloses a VLSI circuit layout optimization method and system based on deep learning in the technical field of integrated circuits, and the method comprises the steps: abstracting a large-scale integrated circuit into a hypergraph structure, receiving the hypergraph structure, generating a node embedding matrix through a hypergraph neural network, and optimizing a segmentation loss function through unsupervised training, obtaining a probability distribution matrix, determining segmented subsets based on the probability distribution matrix, mapping each subset to a physical layout unit, generating a physical region layout of the chip according to an area equilibrium constraint and a time sequence constraint, performing constraint feedback on a physical layout result, and dynamically adjusting parameters of the segmentation loss function. The method can be used for circuit layout of a super-large-scale integrated circuit, and an optimization method and means are provided for providing a high-quality VLSI circuit layout scheme.

The invention belongs to the technical field of integrated circuits, and particularly relates to a speed-adjustable fan driving and anomaly detection circuit with high reliability and low cost. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed; the open circuit and locked-rotor detection module is connected with the logic control module and the VIN port of the LDO; and the short circuit detection module is connected with the logic control module and the output end of the LDO, outputs a signal to a state flag bit FTO, and judges whether the fan is in a normal working state, an open circuit state, a locked-rotor state or a short circuit state or not according to the waveform and the level of the state flag bit FTO. The speed-adjustable fan driving circuit is integrated, and the function of detecting various abnormal states of the fan is achieved.

The invention provides an integrated circuit chip electromagnetic interference intelligent suppression and shielding method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: collecting chip electromagnetic interference data, and carrying out the time-frequency domain decomposition and feature extraction, so as to obtain an initial electromagnetic interference feature vector; calculating an electromagnetic interference threat index based on state space mapping and action space search, and further evaluating the electromagnetic interference situation and determining the minimum shielding strength; carrying out optimization design on the electromagnetic shielding structure by adopting a gradient-guided genetic algorithm to obtain an optimal shielding structure parameter; real-time electromagnetic interference data are adjusted according to the parameters, the suppression ratio is calculated, and iterative design is carried out by combining the suppression ratio optimization genetic algorithm. According to the invention, intelligent evaluation and dynamic suppression of electromagnetic interference are realized, and the accuracy and adaptability of shielding structure design are improved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a speed regulation driving and anomaly detection circuit of a cooling fan. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the VIN port of the LDO, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to the level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention belongs to the technical field of integrated circuits, and particularly relates to an integrated speed regulation fan and an abnormal state detection circuit. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the fan, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to a level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention provides a rule-based layout check and automatic correction system, which relates to the technical field of integrated circuits, and comprises a rule input and management module, a layout data processing module, a rule check engine, a problem analysis and visualization module, an automatic correction module and a user interaction and control interface. Through a rule template library and a complex rule analysis mechanism, an efficient rule configuration mode is provided for a user, and the user can quickly adjust parameters based on a preset template to generate a user-defined design rule, or directly upload complex rule description containing a regular expression and a mathematical formula; and the system analyzes the data into executable logic units and stores the executable logic units in a rule database. According to the mode, the complexity and the time cost of design rule configuration are remarkably reduced, so that the system can flexibly adapt to different process nodes and design requirements, the universality and the efficiency of layout inspection are improved, and convenient and diversified rule management experience is provided for designers.

The invention discloses a high-voltage power amplifier with an over-temperature and over-current protection circuit, and relates to the technical field of integrated circuits. The high-voltage operational amplifier comprises a high-voltage operational amplifier core unit and a self-adaptive protection circuit unit, the high-voltage operational amplifier core unit comprises a rail-to-rail input stage, a gain amplification stage and an AB type push-pull output stage which are sequentially cascaded, and the AB type push-pull output stage comprises a PMOS upper power tube and an NMOS lower power tube; the self-adaptive protection circuit unit comprises a PMOS (P-channel Metal Oxide Semiconductor) current-limiting protection circuit, an NMOS (N-channel Metal Oxide Semiconductor) current-limiting protection circuit and an over-temperature protection circuit; the PMOS current-limiting protection circuit is used for generating a high-voltage domain over-current control signal when the power tube on the PMOS is over-current; the NMOS current-limiting protection circuit is used for generating a low-voltage domain overcurrent control signal when the NMOS lower power tube is in overcurrent; the over-temperature protection circuit is used for generating high-voltage domain over-temperature turn-off signals and low-voltage domain over-temperature turn-off signals when the amplifier is over-temperature; and finally, carrying out logic synthesis on the corresponding over-current control signal and the over-temperature turn-off signal to generate a gate clamping signal.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate, forming a third semiconductor layer covering a first semiconductor layer and a second semiconductor layer, the third semiconductor layer comprising an embedded part penetrating through the second semiconductor layer; forming a plurality of isolation parts penetrating through the third semiconductor layer, wherein the plurality of isolation parts are located right above the plurality of first semiconductor layers; forming a plurality of target semiconductor columns arranged at intervals along the first direction in the third semiconductor layer; target doping ions are injected into the remaining third semiconductor layer, so that the target semiconductor columns, the second semiconductor layer and the third semiconductor layer jointly form a plurality of photodiodes. The electron concentration of the photosensitive area is at least increased, and the photosensitive performance of the BSI image sensor is improved.

The invention discloses a multi-precision matrix calculation unit and a use method thereof, and relates to the technical field of integrated circuits, the multi-precision matrix calculation unit comprises a control logic unit, a cache module and a calculation array; wherein the control logic unit is used for configuring a computing array and controlling the cache module to read in and read out data; the cache module comprises three first cache sub-modules and one second cache sub-module; wherein the three first cache sub-modules are respectively used for caching a first to-be-processed matrix, a second to-be-processed matrix and a third to-be-processed matrix, and the second cache sub-module is used for caching a result matrix; and the calculation array is used for carrying out multiplication and addition operation on different types of to-be-processed matrixes to obtain a result matrix and writing the result matrix back to the cache module. The method can serve as a basic operation core for integrated processing of large-scale matrix multiplication and can also be integrated in processors such as RISC-V for matrix operation, universality is higher, and the method can adapt to fast and efficient calculation scenes.

The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking, relates to the technical field of integrated circuits, and is used for solving the technical problems that an existing injection locking oscillator limits the frequency tuning range and cannot effectively suppress noise. The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking. The low-phase noise ring voltage-controlled oscillator comprises a first ring oscillator unit and a second ring oscillator unit, the n first ring oscillator units are connected in series to form a chain structure; the second ring oscillator unit is provided with a cross coupling inverter complementary injection unit and a tail current source injection unit; a first output end of the chain structure is connected with a second input end of the second ring oscillator unit, and a second output end of the chain structure is connected with a first input end of the second ring oscillator unit; a first signal is injected into a cross-coupling inverter complementary injection unit and a tail current source injection unit, and a second ring oscillator unit receives a second signal output by a chain structure and then outputs a third signal.

The invention relates to the technical field of integrated circuits, in particular to a band-gap reference voltage source, which comprises a high-order compensation circuit, a low-order compensation circuit, a low-order compensation circuit, a low-order compensation circuit and a low-order reference circuit, the band-gap reference circuit is used for generating a positive temperature coefficient voltage and a negative temperature coefficient voltage, performing first-order temperature compensation on the negative temperature coefficient voltage by using the positive temperature coefficient voltage, performing high-order curvature compensation on the negative temperature coefficient voltage based on the target compensation current, determining the compensated voltage as a reference voltage and outputting the reference voltage; according to the band-gap reference voltage source, high-order compensation is introduced through the sub-threshold MOS tube, the negative temperature coefficient voltage can be well reduced, the reference voltage with the temperature coefficient approximate to zero is obtained, and practicability is high.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

The present invention belongs to the field of integrated circuit technology, and specifically is a sparse binary neural network hardware accelerator for gesture recognition. The accelerator of the present invention includes: an input cache module, a weight cache module, a data transmission on-chip network, 32 convolution calculation cores, a hierarchical accumulation tree, a subsequent processing unit, an HDMI interface, a UART interface, and a value prediction and sparse activation map compression / decompression module. The accelerator accelerates gesture recognition of sparse binary networks. The two-level value prediction method can skip the repeated calculations existing in the binary network, thereby accelerating the calculation cycle and reducing power consumption; the channel-level sparse activation compression and decompression method is used to reduce the required data storage volume; the present invention has the characteristics of low power consumption and low latency, effectively reducing hardware resources and improving the energy efficiency of the hardware.

The invention discloses a verification method of an integrated circuit, electronic equipment, a program product and a storage medium, and is applied to the technical field of integrated circuits, and the verification method comprises the following steps: obtaining a time sequence description file used for reflecting a time sequence of a hardware interface protocol of the integrated circuit; analyzing the time sequence description file to generate a structured rule corresponding to the time sequence description file; converting the structured rule into an executable assertion; and integrating the executable assertion into a verification environment, and performing function verification on the integrated circuit by using the verification environment to obtain a verification result of the integrated circuit. By applying the scheme of the invention, end-to-end automatic generation from the time sequence description file to the verification environment is realized, manual coding requirements of workers are not needed, the development cycle is greatly shortened, the efficiency is improved, manual coding of the workers is not needed, and thus human errors can be effectively avoided.

The invention relates to the technical field of integrated circuits, in particular to a multi-FPGA (field programmable gate array) interconnection method based on a data hub, electronic equipment and a medium. Then, obtaining a time division multiplexing proportional gain for adding a direct connection virtual cable to the group hypothesis of the FPGA with the communication requirement and each virtual path set is not empty, updating the virtual path combination set and the virtual path sets of the groups of all the FPGAs until all the virtual path sets are empty, determining a target path combination, and sending the target path combination to the FPGA; and establishing interconnection between the corresponding FPGAs on the basis of the initial topological structure through the data hub based on the target path combination. According to the method, the system frequency of communication between the multiple FPGAs is improved, and the system performance of communication between the multiple FPGAs is optimized.

The invention belongs to the technical field of integrated circuits, and particularly relates to a time mismatch extraction method based on parallel windowing autocorrelation. According to the method, firstly, clustering processing is carried out on signal points; thirdly, preliminarily screening out legal signals based on the time occupancy rate of the signals, and constructing an initial legal signal library; a similarity score between the signals is further calculated through an IDK algorithm, and adjacent frequency bands are divided through a Pettitt method; and finally, continuation of legal signals is realized by means of a DBSCAN clustering algorithm, and automatic construction of a legal signal library is completed. The method is not only suitable for scenes without prior information, but also can be applied under the condition with partial prior information, and can be dynamically updated according to actual requirements. The method is based on radio frequency spectrum monitoring big data, can construct a legal signal library with high reliability and strong generalization ability, provides effective support for subsequent illegal signal monitoring, and has important application value.

The invention provides a correlated double-sampling program-controlled gain amplifier for a high-energy particle detection pixel sensor and an implementation method, and solves the technical problem that a large dynamic range and high readout precision cannot be considered at the same time during existing high-energy particle detection. The circuit comprises a correlated double-sampling circuit, a signal polarity conversion circuit, an amplification feedback circuit and a configuration automatic judgment circuit. The correlated double sampling circuit is used for performing double sampling on the output voltage of the pixel signal to obtain twice sampling voltage; the configuration automatic judgment circuit is used for selecting configurations for switching according to the voltage difference between the two sampling voltages to obtain an output signal; and the amplification feedback circuit is used for performing fixed gain voltage amplification on the output signal to obtain an amplified voltage signal. The circuit can be widely applied to the technical field of integrated circuits.

The invention provides a voltage-controlled oscillator and a phase-locked loop circuit, and relates to the technical field of integrated circuits. The voltage-controlled oscillator comprises a voltage-controlled circuit, a current copying circuit and an oscillating circuit, the voltage control circuit comprises a comparison unit, a switch unit and a voltage acquisition unit. A first input end of the comparison unit is used for receiving input control voltage, a second input end of the comparison unit is grounded through the voltage acquisition unit, an output end of the comparison unit is connected with a control end of the switch unit, one end of the switch unit is grounded through the voltage acquisition unit, and the other end of the switch unit is connected with an input end of the current copying circuit; the output end of the current copying circuit is connected with the input end of the oscillation circuit, and the output end of the oscillation circuit is used for outputting a control signal with target oscillation frequency. According to the voltage-controlled oscillator, the linearity of voltage control current is optimized, and meanwhile, the working voltage range of the voltage-controlled oscillator is expanded.

The invention provides an interface chip, an electric vehicle controller and a control system thereof, relates to the technical field of integrated circuits, and can remarkably improve the universality of the electric vehicle controller and reduce the cost of the electric vehicle controller. The interface chip comprises: a plurality of universal pins, wherein the universal pins are used for providing an input port and / or an output port of a function signal communicated with the electric vehicle controller; the channel module is arranged for each universal pin, the channel module is provided with a plurality of functional ports, and the port types of the different functional ports are different; the communication pin and the plurality of function pins are used for being connected with components in the electric vehicle controller; the control module controls the universal pin to be communicated with the target function pin through the target function port in the corresponding channel module according to the configuration logic which is transmitted by the communication pin and is determined based on one or more function signals; wherein the target function port is matched with the signal type of the function signal communicated with the universal pin, and the target function pin is matched with the function signal communicated with the universal pin.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises a plurality of trench isolation parts distributed at intervals in a first direction; self-aligning the plurality of trench isolation parts to form a first type bottom semiconductor layer comprising a plurality of first target patterns which are distributed at intervals along the first direction, the first target patterns comprising a first type second semiconductor part, a first semiconductor part and a second semiconductor part which are sequentially distributed along the first direction; forming a second type photosensitive lamination layer on the surface, deviating from the substrate, of the bottom semiconductor layer; self-aligning the first semiconductor part, and forming a plurality of first type semiconductor columns which penetrate through the photosensitive lamination layer along a second direction and extend to the first semiconductor part; and forming a first type top semiconductor layer by adopting the same preparation process as the bottom semiconductor layer. The electron concentration of a photosensitive area can be increased at least, and the photosensitive performance of the BSI image sensor is improved.

The invention relates to the technical field of integrated circuits, in particular to a band-gap reference voltage source circuit with high-order compensation, which comprises a PTAT (proportional to absolute temperature) generation circuit, a high-order compensation circuit and a pre-voltage-stabilizing circuit, wherein the PTAT generation circuit generates PTAT current, and the high-order compensation circuit performs second-order compensation on the PTAT current; the pre-voltage-stabilizing circuit is used for driving the PTAT generation circuit and the high-order compensation circuit and comprises a starting circuit, a positive feedback loop and a negative feedback loop; the gain of the positive feedback loop is lower than that of the negative feedback loop; according to the band-gap reference voltage source circuit, the temperature coefficient and the power supply rejection ratio of the circuit are remarkably optimized by integrating high-order temperature compensation, a pre-adjusting power supply and a high-gain feedback loop, and the designed band-gap reference voltage source circuit has the advantages of being extremely low in temperature drift and high in precision.

The invention discloses a self-adaptive time sequence control circuit and method applied to an SRAM (Static Random Access Memory), relates to the technical field of integrated circuits, and aims to solve the problem that the traditional SRAM time sequence control circuit easily causes unstable performance of the SRAM under different temperature conditions. The adaptive time sequence control circuit comprises a temperature compensation code generation circuit and a time sequence compensation circuit. The time sequence compensation circuit at least comprises a delay chain circuit, a first AND gate and a second AND gate; the output end of the first AND gate is connected with the data input end of the delay chain circuit and the first input end of the second AND gate, the data selection end of the delay chain circuit is connected with the output end of the temperature compensation code generation circuit, the output end of the delay chain circuit is connected with the second input end of the second AND gate, and the output end of the second AND gate is connected with the SRAM. The self-adaptive time sequence control circuit applied to the SRAM is used for improving the performance stability of the SRAM under different working temperature conditions.

The embodiment of the invention discloses a deep learning model training method and device and electronic equipment, relates to the technical field of integrated circuits, and can effectively improve the training efficiency of a deep learning model and improve the training effect. The method comprises the steps that a plurality of configuration parameter sets are acquired, and the configuration parameter sets are used for describing training conditions of a deep learning model; inputting the plurality of configuration parameter groups into a pre-trained value model to obtain a plurality of performance index groups, the performance index groups being performances predicted by the value model and represented by deep learning model training under training conditions limited by the configuration parameter groups; the performance index groups are in one-to-one correspondence with the configuration parameter groups; screening out a recommended parameter group from the plurality of configuration parameter groups according to the performance index group; and configuring training conditions of a deep learning model according to the recommended parameter group so as to train the deep learning model. The method is suitable for training of the deep learning model.

The invention relates to the technical field of integrated circuits, discloses an electrothermal simulation and vertical interconnection planning system, method and device for integrated core particles, and solves the problems of low thermal simulation efficiency, incomplete electrothermal coupling modeling and VIC redundancy. The temperature simulation module is used for performing temperature simulation on core particle packaging based on an effective thermal conductivity model and a thermal resistance and thermal capacity network solver, and the effective thermal conductivity model determines thermal conductivity of different packaging layers through a predefined lookup table; a core particle architecture emulator for performing temperature dependent power consumption analysis in which the temperature dependencies of dynamic power consumption and leakage power consumption are modeled by a temperature scaling function; a vertical interconnect planning module to optimize the number of vertical interconnects (VICs) under signal connectivity, power routing constraints, and thermal integrity constraints; according to the system, through iteration of electrothermal coupling simulation and adjustment of power consumption distribution and VIC planning, the temperature of the core particles is lower than a preset threshold value, and the number of VICs is minimized.

The invention relates to the technical field of integrated circuits, and discloses a data transmission method and device for interconnection between core particles, the core particles and a processing system.The method is applied to a first core particle and comprises the steps that a protocol layer of the first core particle receives to-be-transmitted data sent by a processor of the first core particle; a protocol layer carries out protocol layer overall packing on data to be transmitted to obtain a protocol layer packet, the protocol layer packet comprises a packet header field and a load area, the packet header field is used for identifying a channel type and a channel signal field of the load area, the channel type comprises at least one monitoring channel used for monitoring cache consistency between core particles, and the monitoring channel is used for monitoring cache consistency between the core particles. The packet header field is used for identifying a channel type and a channel signal field of the load area; and the protocol layer sends the to-be-transmitted data to the second core grain through the link layer and the physical layer of the first core grain based on the protocol layer packet. The problem of cache access consistency of processors among core particles is effectively solved.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate comprising a first top surface; forming a first semiconductor layer on the first top surface of the substrate, wherein the first semiconductor layer internally comprises a plurality of first photosensitive parts which are distributed at intervals in the first direction, and the top surfaces of the first photosensitive parts are not lower than the top surface of the first semiconductor layer; forming a second semiconductor layer covering the first semiconductor layer, wherein the second semiconductor layer internally comprises a plurality of second photosensitive parts which are distributed at intervals along the first direction, penetrate through the second semiconductor layer along a second direction close to the substrate and extend to the top surfaces of the plurality of first photosensitive parts; and forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer internally comprises a plurality of third photosensitive parts which are distributed at intervals along the first direction, penetrate through the second semiconductor layer along the second direction and extend into the plurality of second photosensitive parts. The electron concentration of a photosensitive area can be increased at least, and the photosensitive performance of the BSI image sensor is improved.

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

The present invention discloses a domino-type multi-stage interlocking power consumption management circuit, which belongs to the field of integrated circuit technology. It mainly solves the problem that traditional energy consumption management chips are difficult to adapt to fluctuations in process, voltage, and temperature, which may cause the problem of chip logic locking failure under special working conditions. The circuit includes a fuse logic generation circuit, a latch matrix, a back-end module, and a power sensing front end, and also includes a multi-stage timing interlocking circuit with a domino effect. The present invention optimizes the concept of power consumption management and locking timing, optimizes and manages power consumption in a multi-stage interlocking manner, abandons the control function of the enable signal, and performs adaptive sequential control in the power supply dimension. It is a supplementary power-on timing management method that ensures effective logic locking while adaptively reducing additional power consumption, and has positive practical significance and practical value.

An error correction method for a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter (SAR ADC) are disclosed, which relate to integrated circuit technology. The successive approximation register analog-to-digital converter error correction method includes the following steps: a. detecting whether a comparator completes a data comparison within a specified time; if so, performing step b; if not, performing step c; b. after the comparator outputs data, starting a next data comparison cycle, and returning to step a; and c. interrupting the conversion, waiting for a signal to start a next conversion, starting the next data comparison cycle, and returning to step a. The method and SAR ADC can effectively prevent problems relating to (1) slow comparator speed caused by dead voltage and (2) burr interference.