607 results about "Asic technology" patented technology

An electrical-energy-storage unit (EESU) has as a basis material a high-permittivity composition-modified barium titanate ceramic powder. This powder is double coated with the first coating being aluminum oxide and the second coating calcium magnesium aluminosilicate glass. The components of the EESU are manufactured with the use of classical ceramic fabrication techniques which include screen printing alternating multilayers of nickel electrodes and high-permittivitiy composition-modified barium titanate powder, sintering to a closed-pore porous body, followed by hot-isostatic pressing to a void-free body. The components are configured into a multilayer array with the use of a solder-bump technique as the enabling technology so as to provide a parallel configuration of components that has the capability to store electrical energy in the range of 52 kW·h. The total weight of an EESU with this range of electrical energy storage is about 336 pounds.

An electrical-energy-storage unit (EESU) has as a basis material a high-permittivity composition-modified barium titanate ceramic powder. This powder is single coated with aluminum oxide and then immersed in a matrix of poly(ethylene terephthalate) (PET) plastic for use in screen-printing systems. The ink that is used to process the powders via screen-printing is based on a nitrocellulose resin that provide a binder burnout, sintering, and hot isostatic pressing temperatures that are allowed by the PET plastic. These lower temperatures that are in the range of 40° C. to 150° C. also allows aluminum powder to be used for the electrode material. The components of the EESU are manufactured with the use of conventional ceramic and plastic fabrication techniques which include screen printing alternating multilayers of aluminum electrodes and high-permittivity composition-modified barium titanate powder, sintering to a closed-pore porous body, followed by hot-isostatic pressing to a void-free body. The 31,351 components are configured into a multilayer array with the use of a solder-bump technique as the enabling technology so as to provide a parallel configuration of components that has the capability to store at least 52.22 kW·h of electrical energy. The total weight of an EESU with this amount of electrical energy storage is 281.56 pounds including the box, connectors, and associated hardware.

A method for determination of tunnel oxide weakness is provided. A tunnel oxide layer is formed on a semiconductor wafer. At least one poly gate is formed on the tunnel oxide layer in a flash memory region of the semiconductor wafer. At least one poly island, which is substantially larger than the poly gate, is formed on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer. The poly island and the tunnel oxide layer therebeneath form a voltage contrast tunnel oxide cell. A voltage contrast measurement is performed on the voltage contrast tunnel oxide cell. The voltage contrast measurement is then compared with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells. The tunnel oxide weakness of the tunnel oxide layer is then determined from the voltage contrast measurement comparisons.

Delay measurement and delay calibration methods and apparatus are described for use within distributed wireless base stations employing a remote radio head topology. The methods and apparatus are usable in any system that requires accurate delay measurement and/or constant delay through an electronic device. The methods and apparatus for measuring delay embody a highly accurate distributed delay measurement architecture that handles multiple delay paths within distributed wireless base stations employing a remote radio head topology. The method and apparatus are amenable to implementation with current integrated circuit technology. The methods and apparatus for calibrating electronic delay within distributed base stations employing a remote radio head topology are useful for implementing distributed wireless base stations where transmit diversity is desired. Using the methods disclosed herein, delay within a distributed wireless base station can be measured and calibrated to achieve very deterministic delay characteristics at the system level.

An improved hybrid integrated circuit is provided in order that the specification can quickly be modified and adjusted when required without need for preparing a new mask and without need for compromising the performance of the hybrid integrated circuit. The hybrid integrated circuit comprises: a common substrate on which an electrode pattern is formed; a first monolithic semiconductor chip designed by the use of an ASIC technology and mounted on the common substrate; a second monolithic semiconductor chip designed by the use of an FPGA technology and mounted on the common substrate; and external terminals provided for the common substrate; and an insulating material encapsulating the first monolithic semiconductor chip and the second monolithic semiconductor chip, wherein the second monolithic semiconductor chip is provided with a storage element which is rewritable by means of a control signal given through the external terminal in order to store circuit configuration data with which internal connections of the second monolithic semiconductor chip are modified to form a hardware configuration within the second monolithic semiconductor chip corresponding to a predetermined operational specification, and wherein the first monolithic semiconductor chip and the second monolithic semiconductor chip cooperate with each other by exchanging signals through the electrode pattern of the common substrate in order to implement the predetermined operational specification.

The invention relates to a D trigger used for single particle upsetting resistance and single particle transient pulse in the technical filed of an integrated circuit, comprising two multichannel switches, two delay circuits, two protecting gate circuits and three inverters; wherein, the multichannel switches are used for forming a feedback loop for latching data; the delay circuits are used for generating signals in delay modes; the protecting gate circuits are used for filtering voltage transient fluctuation of the input signals; in the feedback loop of the D trigger, data input signal D and the delayed mode thereof enter the protecting gate circuit; and the output signals of the protecting gate circuit filter the delayed voltage transient fluctuation of the data input signal D and the width of the voltage transient fluctuation is not wider than the delay of the delay circuit. The invention can be applied to application occasions needing higher radiation resistance, leads the single particle upsetting resistance and single particle transient pulse performance of D trigger to reach the same level as a time sampling D trigger; and simultaneously, the increasing of the unit area is less than that of the time sampling D trigger and the working speed is superior to that of the time sampling D trigger.

An integrated circuit is a baseboard management controller that is a fully integrated system-on-a-chip microprocessor incorporating function blocks and interfaces that provide remote management solution. The integrated circuit uses a microprocessor, a media co-processor to accelerate video processing, and a set of system and peripheral functions that are useful in a variety of remote management applications. It further includes an integrated USB high-speed device and an OTG interface to support keyboard, mouse and mass storage emulation without additional external components, and two integrated MII LAN interfaces and one FSB interface, a memory controller to support a variety of static and dynamic memory components, an encryption controller to ensure secure remote management sessions and IPMI2.0-compliant BMC interfaces. The integrated circuit is based on structured ASIC technology, which enables easy customization of function blocks according to customer demands or new industry standards.

A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

The present invention belongs to a technical field of an integrated circuit, and particularly to a low power consumption production line analog-digital converter which adopts an operational amplifier sharing. The analog-digital converter is composed of an input sampling holding circuit, a six-stage allowance gain circuit, an one-stage double-digit all-parallel analog-digital converter, a converting switch which is used for operational amplifier sharing, six sub-analog-digital converters, six sub-digital-analog converters, a production line output clock synchronous circuit and a digital correcting circuit. The sampling holding circuit and the six-stage allowance gain circuit are connected in sequence. The last stage is a double-digit all-parallel analog-digital converter. The input end of each stage of allowance gain circuit is connected with each stage of sub-analog-digital converter. Two continuous stages shares one operational amplifier. After the output clock synchronous circuit, the data with 14 digits is obtained, and after the digital correction of the digital correcting circuit, the final eight digit quantized output is obtained. The analog-digital converter realizes high speed and low power consumption.

The invention belongs to the technical field of integrated circuits, in particular to a successive approximation type analog-to-digital converter of an energy-saving capacitor array. The analog-to-digital converter comprises a sampling switch, a track and hold circuit, a comparator, control logic and a capacitor array digital-to-analog converter, wherein the capacitor array digital-to-analog converter adopts a switch mode of the novel capacitor array digital-to-analog converter provided by the invention. By using the mode, the average switch consumption of the capacitor can be reduced.

The invention discloses a radio-frequency ultra-wideband low-noise amplifier based on inductance compensation, relating to a radio-frequency integrated circuit technology. The radio-frequency ultra-wideband low-noise amplifier mainly consists of an input amplification-stage circuit, a feedback-stage circuit, a matching-stage circuit, a load-stage circuit, a bias-stage circuit and an output buffering-stage circuit jointly. According to the radio-frequency ultra-wideband low-noise amplifier, both the input matching stage and the load stage are subjected to inductance compensation, and the sensitivity of the low-noise amplifier on the technology is reduced by adopting a current multiplexing technology with independent bias, so that the performance is more stable, the ultra-wideband is also realized, and the working frequency range is 0.1-12GHz; meanwhile, the radio-frequency ultra-wideband low-noise amplifier gets favorable indexes, such as noise, linearity, gain, power consumption and the like and is suitable for an ultra-wideband multi-standard wireless communication receiving system.

The invention discloses a metallic film flexible strain sensor and a preparation method therefor. The sensor comprises a metallic film, a flexible base material, and at least two contacts. The metallic film is attached to the flexible base material in a weak attaching manner. The metallic film is provided with at least one through directional long crack, wherein the width of the directional long crack is at a nanometer scale. The directional long crack passes through the metallic film to the interior of the flexible base material in a thickness direction, and the direction of the directional long crack is perpendicular to a stretching direction. When the metallic film generates stretching deformation along with the flexible base material, the crack of the metallic film is extended and even broken. When the stretching deformation of the flexible base material is released, the crack of the metallic film narrows and finally returns to an initial state. The sensor is simple in structure, is higher in sensitivity, is simple in preparation technology, is abundant in raw material, is compatible with a conventional integrated circuit, and is convenient for large-scale production.

The invention relates to an LC quadrature VCO (voltage controlled oscillator) which can reduce the intermittent noise, belonging to the technical field of integrated circuit, . The invention is characterized in that two negative resistance oscillators are connected together with a quadrature coupler to output quadrature signals; the reduced phase noise is implemented by using a more linear narrow-band turning variable capacitor structure, multiband switching digital array with a lower parasitic capacitance and an intermittent noise eliminating circuit reducing the intermittent noise getting into the LC oscillator when inputting voltage crossing the zero point.

The invention provides a single address flow sorter of group network. The sorter binds several physical terminals into a virtual physical terminal to extend the upstream flow, and allocates network flow to different processing joints according to the IP address of client terminal and upgrade the process ability. The data pack applying the IP is allocated with a different physical terminal, the process is realized with ASIC technology, the flow classification accordance is to work out Hash value to the client terminal IP address, because the data of the same user is allocated to the same physical terminal, thus it can provides continuous service to the joint connected to the physical joint.

The invention belongs to the technical field of integrated circuits, and relates to a function traversal testing method for high performance SoC FPGA. A set of complete function traversal testing method is established for CLB, BRAM, DSP, CM, IOB, clock network, interconnection and other resources in the high performance SoC FPGA, and corresponding bit stream is generated to apply excitation on an FPGA port and read back the response of the FPGA port. The response is compared with an expected result to realize the traversal covering test on the Soc FPGA resources. The test method is applicable to various high performance Soc FPGA with complex function and abundant resources and if of high application value in the FPGA test field. The test coverage rate and the test efficiency are high, the test cost is low, and the transferability and the universality are good.

The invention belongs to the technical field of an integrated circuit, in particular to a traversal test method of a configurable logic block (CLB) of a field programmable gate array (FPGA) based on a look-up table (LUT) structure. The method comprises: carrying out traversal tests on the single-point fault of an LUT, testing the multiple-point fault of the LUT, carrying out traversal tests on a distributive RAM, assigning the initial value of the trigger to be 0 or 1, carrying out level fixing on a setting terminal and a resetting terminal, leading the enabling to be invalid, and carrying out traversal tests on setting, resetting and enabling and the like. The invention can complete all the tests on the confronting manufacturing of all the CLBs in FPGA chips, and can cover all the basic logic devices, programmable code points and internal interconnection resources inside the CLBs. The configuration times, configuration difficulty and test time required by the test can all be greatly optimized.

It is a high frequency loop oscillation type phase locked loop circuit with self-accommodation frequency compensation. It consists of a multichannel loop type voltage-control oscillator with self-accommodate central frequency correction function,a difference electric charge pump, a linear double / single conversion circuit, a frequency divider, etc. The voltage-control oscillator possesses two gain channels, fast and slow. Its load transistor connects in serial into the voltage control channel to form a positive feedback. A selectable load array and a switch designed for technology and temperature compensation work in parallel with the original PMOS load. According to the conditions of technology and temperature, an auto-switch control module monitors the loop's lockup status and decides the number of parallel loads. Via self-accommodation feedback monitoring and compensation, it greatly reduces the dependency of the phase lock loop against the technology and temperature.

The invention relates to a low power consumption RF front-end circuit of the wireless receiver, belonging to the technical field of the integrated circuit of the RF wireless receiver, , comprising an RF input matching network, an amplifier stage, a bridge transformer, an LO switch stage, an IF load and a current source bias circuit; wherein, the RF input matching network implements the impedance matching between an antenna and the amplifier stage; the amplifier stage is used for amplifying the signal, the bridge transformer transfers the signal amplified to the LO switch stage and implements DC isolation between the front stage and back stage; the LO switch stage is used for implementing frequency mixing of the RF current signal and the LO signal and outputting alternatively the IF signalon an outputting differential load. Compared with the traditional RF front-end circuit, the circuit structure can use an on-chip integrated transformer or an on-chip inductor to implement inputting matching, and use the on-chip integrated transformer to implement the amplifying and downward frequency mixing of the RF signals perfectly, which simplifies the circuit structure. The circuit can be used in a low power supply voltage environment, and has the advantages of low DC power consumption, and less circuit noise and signal distortion.

The invention discloses a resistive random access memory (RAM) and a manufacturing method thereof, belonging to the technical field of integrated circuits. The resistive RAM is of MIM structure, wherein, the bottom layer and the top layer of the MIM structure are respectively provided with metal electrodes; the intermediate layer of the MIM structure is provided with a first layer parylene polymer membrane, a metal or metal oxide nano-layer and a second layer parylene polymer membrane. By adopting the composition of a parylene polymer and metal/metal oxide as a resistive material, the invention can manufacture the resistive RAM with good resistive property and process compatibility. A preparation method of the parylene polymer adopts the chemical vapor deposition process at room temperature without by-products and solvent pollution, and is compatible with other modules of CMOS. Besides, the solution and solvents used in the parylene-resistant standard photolithography process can employ the CMOS standard photolithography process to manufacture the resistive RAM, thus increasing the memory density of the RAM.

The invention relates to a spaceborne digital signal processor turning reinforcing method which is achieved through a spaceborne digital signal processor turning reinforcing system. The spaceborne digital signal processor turning reinforcing system comprises a digital signal processor (DSP) chip, an application specific integrated circuit (ASIC) chip, a programmable read only memory (PROM) and a static random access memory (SRAM). The method includes the steps of utilizing the design integrating outside slice running, error detection and correction (EDAC), an ASIC technology and a watchdog, meanwhile utilizing a radiation-proof ASIC technology to organically combine various anti-spatial-single-particle measures together, and to form a unique novel anti-single-particle reinforcing method. The spaceborne digital signal processor turning reinforcing method has the advantages of being capable of simplifying the system and improving inherent reliability, few in hardware resources, low in design complexity, simple in achieving, and capable of greatly reducing the rate of occurrence of single-particle events when the DSP chip runs in a bad radiation environment.

A circuit and a method are given, to realize a very efficient driver device for igniters or squibs as used e.g. in airbag applications. Special attention has been turned to include secure and always reliable operating features into the device and at the same time to reach for a low-cost implementation with modern integrated circuit technologies. Controlled firing operation and sophisticated diagnostic mechanisms are realized. These design features have to a great extent been acquired by consequently using current mirror circuit principles. Current trimming and limitation to secure values are part of the solution.

The invention belongs to an RF wireless receiver integration circuit technical field, in particular to an orthogonal down-frequency mixer with low power loss and high performance. The invention consists of an RF conversion transformer, an LO switch class, an IF load class and a power supply bias; wherein, the RF conversion transformer amplifies and transmits the received RF current signals; the orthogonal LO switch class leads the RF current signals to be alternatively output on an output differential load by a LO frequency with the phase difference of 90 DEG, thus implementing that the RF frequency multiplied by the orthogonal LO frequency obtains the orthogonal IF signal which is then output on the load. Compared with traditional Kilbert frequency mixers, the circuit structure replaces the differential transistor of RF amplification class by an on-chip integration amplifier, which can lead the frequency mixer to be applicable to low power voltage and dramatically reduce circuit noise and signal distortion; two orthogonal LO switch classes are combined into one circuit, which leads the frequency mixer to output orthogonal IF signals, simplifies the design of the wireless receiver and obviously reduces the power loss of the frequency mixer module.

The invention discloses a content management system based on information sharing and interaction, and relates to the technical field of electronic information. The system is characterized in that the system comprises a data extraction module, a data classification module, a data fusion module, a data conversion module, a data storage module, a data analysis module, a data application module and a data service module. The system is advantageous in that a general information pushing method in a position service mode based on place names and address data is supported, the management with a unified interface is performed on access terminals and user equipment with different interfaces and different categories, the geographical information technology, the integrated circuit technology, and the electronic application technology are integrated during related operation, the goals of multi-field cross-functionality-department, cross-industry, and cross-discipline information sharing and cooperative operation are achieved, government-enterprise cooperation and business-enterprise cooperation are realized, and intelligent service and intelligent management between enterprises and institutions and ordinary audiences can be achieved.

A micropyrolyzer has applications to pyrolysis, heated chemistry, and thermal desorption from liquid or solid samples. The micropyrolyzer can be fabricated from semiconductor materials and metals using standard integrated circuit technologies. The micropyrolyzer enables very small volume samples of less than 3 microliters and high sample heating rates of greater than 20° C. per millisecond. A portable analyzer for the field analysis of liquid and solid samples can be realized when the micropyrolyzer is combined with a chemical preconcentrator, chemical separator, and chemical detector. Such a portable analyzer can be used in a variety of government and industrial applications, such as non-proliferation monitoring, chemical and biological warfare detection, industrial process control, water and air quality monitoring, and industrial hygiene.

Prior art architectures of power amplifiers employ a substantial die area, and utilize multiple integrated circuit technologies with a net higher manufacturing cost and large associated packaging area. A new scheme is presented wherein several sense and control signals are used to provide fine and gross control over the key figures of merit associated with integrated semiconductor power amplifiers. How and where these sense and control signals are used is crucial to achieving the most manufacturable and most economic integrated amplifier. In accordance with a first embodiment of the invention, a Dual Feedback-Low power regulation circuit for a three-stage power amplifier integrated circuit is provided. In accordance with a second embodiment of the invention, a current source feedback circuit having low RF output signal power regulation for a three-stage power amplifier integrated circuit is provided. In accordance with a third embodiment of the invention, a detector circuit in the form of an integrated logarithmic current detector circuit in conjunction with a three stage power amplifier integrated circuit. The three embodiments of the invention advantageously overcome the limitations of the prior art.

The invention belongs to the integrated circuit technical field, in particular to an embedded dynamic random access memory with multiple ports and multiple channels and a memory operating method thereof. The memory comprises a plurality of memory cells; n transistors which are arranged in each memory cell (n is a natural number and larger than or equal to 2); a word line bit line pair arranged in each transistor, wherein, the bit line of each transistor can be connected with an input/output port; different transistors in the memory cell are positioned in the same floating body which is electrically isolated from surrounding; word line bit line pairs of different transistors are independent form each other, and can be selected synchronously or time-sharing, then, corresponding different transistors selected at the same time or time-sharing can read memory and refresh memory operation synchronously or time-sharing through corresponding ports. The refreshing operation and the reading operation are independent mutually, thereby improving the speed of reading operation of the embedded type dynamic random access memory, and meeting different power consumption requirements through regulating frequency of the refreshing operation.

The invention belongs to the technical field of radio frequency wireless receiver integrated circuits, and relates to a quadrature voltage controlled oscillator in a wireless receiver integrated circuit. In the quadrature voltage controlled oscillator, the phase noise performance of the quadrature voltage controlled oscillator circuit is improved and the output phase mismatch is reduced by improving a coupling mode of the conventional quadrature voltage controlled oscillator and introducing a phase shift network at the source end of a coupling tube. By using a linearly changed an accumulation-type metal-oxide semiconductor (MOS) variable capacitor array, the linearity of a tuning curve of a quadrature voltage controlled oscillator (QVCO) is greatly improved so that the tuning range of a control voltage is increased. Because a bias current of the QVCO is variable, a relatively constant output oscillating voltage amplitude can be maintained; therefore, a low phase noise can be obtained by the QVCO in a broad output frequency range.

The invention relates to the technique of simulation integrated circuits, in particular to a band gap reference voltage source. The band gap reference voltage source comprises a biasing circuit, a band gap reference core circuit, a temperature detecting circuit, a switch capacitive circuit and an operational amplifier, wherein the biasing circuit supplies currents to the band gap reference core circuit, the output end of the band gap reference core circuit is connected with the input end of the switch capacitive circuit, the temperature detecting circuit is connected to a branch circuit of the band gap reference core circuit, the synclastic input end and the reverse input end of the operational amplifier are connected with the switch capacitive circuit, and the output end of the operational amplifier is connected with one output end of the switch capacitive circuit and serves as the output end of the reference voltage source. The band gap reference voltage source has the advantages that accuracy of output voltage of the first-order compensation band gap reference voltage source is improved, large resistors are not used, the circuit structure is simple, the layout area is saved, and cost is lowered. The band gap reference voltage source is particularly suitable for reference voltage sources.

The invention belongs to the technical field of integration circuits and particularly relates to a high spurious-free-dynamic-range (SFDR) multichannel time staggering successive approximation (SAR) type analog to digital converter. A capacitor array for sampling and quantifying at the front end of each channel of the conventional multichannel time staggering SARADC is often relatively independent and fixed; and the own capacitor array of each channel at the front end is dismantled into a number of equal modules so as to form a 'capacitance pool'. Before sampling, the capacitance pool is randomly distributed to each channel, so a fixed error of each channel is reduced and randomized then; from an energy spectrum, energy of a harmonic component is changed into noise which is normalized to a noise base; therefore, the nonlinearity caused by capacitance mismatch is improved effectively.

The invention belongs to the technical field of digital simulation hybrid-integrated-circuits, and discloses a digital correction circuit and a digital-to-analog converter of a current-steering structure and with the digital correction circuit. The digital-to-analog converter solves the problems that in the prior art, a digital-to-analog converter of a current-steering structure occupies a larger domain area, cost of chips is increased, large stray capacitance and parasitic resistance are brought to currents, and dynamic performance of the digital-to-analog converter is influenced. Voltage at the two ends of a first resistor is collected and compared when a current source control switch is under an opening state and a closing state through the digital correction circuit, control codes for a current source in high-order current source arrays are generated through successive approximation, and thus the digital-to-analog converter is corrected, namely actual values of the magnitude of the currents of the high-order current source are regulated to reference values through continuous comparison and the successive approximation. The digital-to-analog converter greatly shortens the domain area of the high-order current source of a thermometer code, meanwhile guarantees performance, and is suitable for digital-to-analog conversion operation.