843 results about "Asic technology" patented technology

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

The invention provides an integrated circuit chip electromagnetic interference intelligent suppression and shielding method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: collecting chip electromagnetic interference data, and carrying out the time-frequency domain decomposition and feature extraction, so as to obtain an initial electromagnetic interference feature vector; calculating an electromagnetic interference threat index based on state space mapping and action space search, and further evaluating the electromagnetic interference situation and determining the minimum shielding strength; carrying out optimization design on the electromagnetic shielding structure by adopting a gradient-guided genetic algorithm to obtain an optimal shielding structure parameter; real-time electromagnetic interference data are adjusted according to the parameters, the suppression ratio is calculated, and iterative design is carried out by combining the suppression ratio optimization genetic algorithm. According to the invention, intelligent evaluation and dynamic suppression of electromagnetic interference are realized, and the accuracy and adaptability of shielding structure design are improved.

The invention discloses a high-voltage power amplifier with an over-temperature and over-current protection circuit, and relates to the technical field of integrated circuits. The high-voltage operational amplifier comprises a high-voltage operational amplifier core unit and a self-adaptive protection circuit unit, the high-voltage operational amplifier core unit comprises a rail-to-rail input stage, a gain amplification stage and an AB type push-pull output stage which are sequentially cascaded, and the AB type push-pull output stage comprises a PMOS upper power tube and an NMOS lower power tube; the self-adaptive protection circuit unit comprises a PMOS (P-channel Metal Oxide Semiconductor) current-limiting protection circuit, an NMOS (N-channel Metal Oxide Semiconductor) current-limiting protection circuit and an over-temperature protection circuit; the PMOS current-limiting protection circuit is used for generating a high-voltage domain over-current control signal when the power tube on the PMOS is over-current; the NMOS current-limiting protection circuit is used for generating a low-voltage domain overcurrent control signal when the NMOS lower power tube is in overcurrent; the over-temperature protection circuit is used for generating high-voltage domain over-temperature turn-off signals and low-voltage domain over-temperature turn-off signals when the amplifier is over-temperature; and finally, carrying out logic synthesis on the corresponding over-current control signal and the over-temperature turn-off signal to generate a gate clamping signal.

The invention discloses a multi-precision matrix calculation unit and a use method thereof, and relates to the technical field of integrated circuits, the multi-precision matrix calculation unit comprises a control logic unit, a cache module and a calculation array; wherein the control logic unit is used for configuring a computing array and controlling the cache module to read in and read out data; the cache module comprises three first cache sub-modules and one second cache sub-module; wherein the three first cache sub-modules are respectively used for caching a first to-be-processed matrix, a second to-be-processed matrix and a third to-be-processed matrix, and the second cache sub-module is used for caching a result matrix; and the calculation array is used for carrying out multiplication and addition operation on different types of to-be-processed matrixes to obtain a result matrix and writing the result matrix back to the cache module. The method can serve as a basic operation core for integrated processing of large-scale matrix multiplication and can also be integrated in processors such as RISC-V for matrix operation, universality is higher, and the method can adapt to fast and efficient calculation scenes.

The invention relates to the technical field of integrated circuits, in particular to a band-gap reference voltage source, which comprises a high-order compensation circuit, a low-order compensation circuit, a low-order compensation circuit, a low-order compensation circuit and a low-order reference circuit, the band-gap reference circuit is used for generating a positive temperature coefficient voltage and a negative temperature coefficient voltage, performing first-order temperature compensation on the negative temperature coefficient voltage by using the positive temperature coefficient voltage, performing high-order curvature compensation on the negative temperature coefficient voltage based on the target compensation current, determining the compensated voltage as a reference voltage and outputting the reference voltage; according to the band-gap reference voltage source, high-order compensation is introduced through the sub-threshold MOS tube, the negative temperature coefficient voltage can be well reduced, the reference voltage with the temperature coefficient approximate to zero is obtained, and practicability is high.

The invention discloses a verification method of an integrated circuit, electronic equipment, a program product and a storage medium, and is applied to the technical field of integrated circuits, and the verification method comprises the following steps: obtaining a time sequence description file used for reflecting a time sequence of a hardware interface protocol of the integrated circuit; analyzing the time sequence description file to generate a structured rule corresponding to the time sequence description file; converting the structured rule into an executable assertion; and integrating the executable assertion into a verification environment, and performing function verification on the integrated circuit by using the verification environment to obtain a verification result of the integrated circuit. By applying the scheme of the invention, end-to-end automatic generation from the time sequence description file to the verification environment is realized, manual coding requirements of workers are not needed, the development cycle is greatly shortened, the efficiency is improved, manual coding of the workers is not needed, and thus human errors can be effectively avoided.

The invention belongs to the technical field of integrated circuits, and particularly relates to a time mismatch extraction method based on parallel windowing autocorrelation. According to the method, firstly, clustering processing is carried out on signal points; thirdly, preliminarily screening out legal signals based on the time occupancy rate of the signals, and constructing an initial legal signal library; a similarity score between the signals is further calculated through an IDK algorithm, and adjacent frequency bands are divided through a Pettitt method; and finally, continuation of legal signals is realized by means of a DBSCAN clustering algorithm, and automatic construction of a legal signal library is completed. The method is not only suitable for scenes without prior information, but also can be applied under the condition with partial prior information, and can be dynamically updated according to actual requirements. The method is based on radio frequency spectrum monitoring big data, can construct a legal signal library with high reliability and strong generalization ability, provides effective support for subsequent illegal signal monitoring, and has important application value.

The invention provides a correlated double-sampling program-controlled gain amplifier for a high-energy particle detection pixel sensor and an implementation method, and solves the technical problem that a large dynamic range and high readout precision cannot be considered at the same time during existing high-energy particle detection. The circuit comprises a correlated double-sampling circuit, a signal polarity conversion circuit, an amplification feedback circuit and a configuration automatic judgment circuit. The correlated double sampling circuit is used for performing double sampling on the output voltage of the pixel signal to obtain twice sampling voltage; the configuration automatic judgment circuit is used for selecting configurations for switching according to the voltage difference between the two sampling voltages to obtain an output signal; and the amplification feedback circuit is used for performing fixed gain voltage amplification on the output signal to obtain an amplified voltage signal. The circuit can be widely applied to the technical field of integrated circuits.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises a plurality of trench isolation parts distributed at intervals in a first direction; self-aligning the plurality of trench isolation parts to form a first type bottom semiconductor layer comprising a plurality of first target patterns which are distributed at intervals along the first direction, the first target patterns comprising a first type second semiconductor part, a first semiconductor part and a second semiconductor part which are sequentially distributed along the first direction; forming a second type photosensitive lamination layer on the surface, deviating from the substrate, of the bottom semiconductor layer; self-aligning the first semiconductor part, and forming a plurality of first type semiconductor columns which penetrate through the photosensitive lamination layer along a second direction and extend to the first semiconductor part; and forming a first type top semiconductor layer by adopting the same preparation process as the bottom semiconductor layer. The electron concentration of a photosensitive area can be increased at least, and the photosensitive performance of the BSI image sensor is improved.

The invention relates to the technical field of integrated circuits, in particular to a band-gap reference voltage source circuit with high-order compensation, which comprises a PTAT (proportional to absolute temperature) generation circuit, a high-order compensation circuit and a pre-voltage-stabilizing circuit, wherein the PTAT generation circuit generates PTAT current, and the high-order compensation circuit performs second-order compensation on the PTAT current; the pre-voltage-stabilizing circuit is used for driving the PTAT generation circuit and the high-order compensation circuit and comprises a starting circuit, a positive feedback loop and a negative feedback loop; the gain of the positive feedback loop is lower than that of the negative feedback loop; according to the band-gap reference voltage source circuit, the temperature coefficient and the power supply rejection ratio of the circuit are remarkably optimized by integrating high-order temperature compensation, a pre-adjusting power supply and a high-gain feedback loop, and the designed band-gap reference voltage source circuit has the advantages of being extremely low in temperature drift and high in precision.

The embodiment of the invention discloses a deep learning model training method and device and electronic equipment, relates to the technical field of integrated circuits, and can effectively improve the training efficiency of a deep learning model and improve the training effect. The method comprises the steps that a plurality of configuration parameter sets are acquired, and the configuration parameter sets are used for describing training conditions of a deep learning model; inputting the plurality of configuration parameter groups into a pre-trained value model to obtain a plurality of performance index groups, the performance index groups being performances predicted by the value model and represented by deep learning model training under training conditions limited by the configuration parameter groups; the performance index groups are in one-to-one correspondence with the configuration parameter groups; screening out a recommended parameter group from the plurality of configuration parameter groups according to the performance index group; and configuring training conditions of a deep learning model according to the recommended parameter group so as to train the deep learning model. The method is suitable for training of the deep learning model.

The invention relates to the technical field of integrated circuits, and discloses a data transmission method and device for interconnection between core particles, the core particles and a processing system.The method is applied to a first core particle and comprises the steps that a protocol layer of the first core particle receives to-be-transmitted data sent by a processor of the first core particle; a protocol layer carries out protocol layer overall packing on data to be transmitted to obtain a protocol layer packet, the protocol layer packet comprises a packet header field and a load area, the packet header field is used for identifying a channel type and a channel signal field of the load area, the channel type comprises at least one monitoring channel used for monitoring cache consistency between core particles, and the monitoring channel is used for monitoring cache consistency between the core particles. The packet header field is used for identifying a channel type and a channel signal field of the load area; and the protocol layer sends the to-be-transmitted data to the second core grain through the link layer and the physical layer of the first core grain based on the protocol layer packet. The problem of cache access consistency of processors among core particles is effectively solved.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate comprising a first top surface; forming a first semiconductor layer on the first top surface of the substrate, wherein the first semiconductor layer internally comprises a plurality of first photosensitive parts which are distributed at intervals in the first direction, and the top surfaces of the first photosensitive parts are not lower than the top surface of the first semiconductor layer; forming a second semiconductor layer covering the first semiconductor layer, wherein the second semiconductor layer internally comprises a plurality of second photosensitive parts which are distributed at intervals along the first direction, penetrate through the second semiconductor layer along a second direction close to the substrate and extend to the top surfaces of the plurality of first photosensitive parts; and forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer internally comprises a plurality of third photosensitive parts which are distributed at intervals along the first direction, penetrate through the second semiconductor layer along the second direction and extend into the plurality of second photosensitive parts. The electron concentration of a photosensitive area can be increased at least, and the photosensitive performance of the BSI image sensor is improved.

An error correction method for a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter (SAR ADC) are disclosed, which relate to integrated circuit technology. The successive approximation register analog-to-digital converter error correction method includes the following steps: a. detecting whether a comparator completes a data comparison within a specified time; if so, performing step b; if not, performing step c; b. after the comparator outputs data, starting a next data comparison cycle, and returning to step a; and c. interrupting the conversion, waiting for a signal to start a next conversion, starting the next data comparison cycle, and returning to step a. The method and SAR ADC can effectively prevent problems relating to (1) slow comparator speed caused by dead voltage and (2) burr interference.

The invention belongs to the technical field of integrated circuits, and relates to an automatic design optimization method suitable for a large-scale analog / radio frequency circuit, which comprises the following steps of: hierarchically dividing the large-scale analog / radio frequency circuit into a plurality of circuit modules; carrying out random sampling to obtain an initial data set, and establishing a Pareto frontier model of a lower-layer circuit module; the optimization of the performance index of the system circuit is converted into the optimization of the performance index of the lower circuit module; obtaining a'pseudo 'Pareto optimal point near the optimal performance index of each current lower-layer circuit module by using an improved evolutionary algorithm; updating the Pareto front of the lower layer module by using the extracted Pareto optimal point, and performing constraint mapping calculation until the Pareto front of the current lower layer module is partially overlapped with the actual Pareto front; and solving a design variable of the lower-layer circuit module by using the output optimal performance index of the lower-layer module. According to the method, good circuit performance indexes can be obtained with fewer SPICE simulation times, and the cost of automatic design of a large-scale analog / radio frequency circuit is reduced.

The invention provides an integrated circuit hot spot detection method based on multi-modal feature fusion and dynamic optimization, which relates to the technical field of integrated circuits, and comprises the following steps: acquiring multi-modal feature data, executing progressive block clustering to extract multi-scale features, fusing the features by using a multi-head attention mechanism, and constructing a hot spot feature map. A hot spot area is determined by combining spatial autocorrelation analysis, and a detection result is optimized based on synchronization analysis of a morphological evolution and energy evolution sequence. The hot spot detection accuracy and robustness can be improved, the false detection rate can be reduced, and the potential hot spot area in the complex layout can be effectively identified.

The invention provides a storage and calculation integrated structure and a chip, and belongs to the technical field of integrated circuits, and the storage and calculation integrated structure comprises at least one near storage core grain which is used for providing large-capacity storage; the in-memory computing unit is used for providing computing processing, and the near-memory core grains provide cache space for data and / or instructions processed by the in-memory computing unit; the at least one logic processing core particle is used for loading the data and / or instructions stored in the near memory core particle into the in-memory computing unit, and updating and storing the data and / or instructions processed by the in-memory computing unit into the near memory core particle; and the logic processing core particle is integrated with the near memory core particle and the in-memory computing unit through hybrid bonding and / or TSV (Through Silicon Via). The storage and calculation integrated structure is applied to high-performance calculation, the high-performance calculation requirement and the large-capacity storage requirement can be met at the same time, the high-performance calculation of the system is maximized, and support is provided for the development of the calculation power technology from the hardware structure.

The embodiment of the invention discloses a substrate-level temperature control device and method and a chip, relates to the technical field of integrated circuits, and can save substrate area resources and improve the heat management effect of the chip. The substrate-level temperature control device comprises a temperature detection unit which is configured to be arranged corresponding to each core particle and is used for acquiring a temperature sensing signal of each corresponding core particle; the temperature control unit is configured to obtain the temperature of each corresponding core particle according to the temperature sensing signal of each corresponding core particle; generating a heat dissipation control signal and a frequency regulation signal according to the temperature of each corresponding core particle, and dynamically and cooperatively controlling the temperature of the corresponding core particle according to the heat dissipation control signal and the frequency regulation signal; and the temperature control unit is integrated on the substrate and is interconnected with each temperature detection unit. The method is suitable for an integrated circuit thermal management scene.

The invention relates to the technical field of integrated circuits, in particular to a capacitive coupling type current steering digital-to-analog converter for transmitting switch control signals, which comprises a current steering unit and a switch signal control unit. The switching signal control unit comprises two capacitance coupling type level shifters; the current steering unit comprises a current source and transistors M1-M4, source electrodes of the transistors M1-M4 are connected with one end of the current source, and the other end of the current source is grounded; drain electrodes of the transistors M1-M2 are connected to form a positive output signal, and drain electrodes of the transistors M3-M4 are connected to form a negative output signal; the grid electrodes of the transistors M1-M2 are connected with a first capacitive coupling type level shifter, and the transistors M3-M4 are connected with a second capacitive coupling type level shifter; the on and off of the transistors M1-M4 are controlled through the two capacitance coupling type level shifters; the cross coupling unit is introduced to assist in transmitting switch control signals, and the dynamic performance of the digital-to-analog converter is improved.

The invention discloses a capacitor mismatch error shaping circuit and method suitable for a multi-bit quantization Sigma-Delta ADC, and belongs to the technical field of integrated circuits, and the capacitor mismatch error shaping circuit comprises a data weight averaging module which is used for adopting a data weight averaging technology for high-bit quantization code words, and correcting the high-bit quantization code words according to the data weight averaging technology; averaging the mismatch error of the capacitor corresponding to the high-order quantization code word to obtain an averaged high-order capacitor; and the mismatch error shaping module is used for taking the averaged high-order capacitance as a reference, adopting a mismatch error shaping technology, keeping low-order feedback of the current low-order quantization code word of the lower polar plate of the capacitive digital-to-analog converter during Sigma-Delta ADC sampling, and realizing subtraction operation between two adjacent low-order quantization code words. According to the invention, the error caused by the mismatch of the CDAC capacitor fed back by the multi-bit quantization Sigma-Delta ADC can be effectively suppressed, the linearity of the system is improved, and the circuit overhead is remarkably reduced.

The invention discloses a broadband digital phase shifter based on an inductor sharing topology and an equivalent band-pass network, relates to the technical field of microwave integrated circuits, and is suitable for being applied to a Sub-GHz frequency band. The phase shifter comprises a phase shift circuit module and a driving circuit module, and the phase shift circuit module comprises six basic phase shift units including a fine phase shift unit and a coarse phase shift unit which cooperatively realize full-range multi-state phase shift. The fine phase shift unit adopts an inductor sharing topology, so that a phase shift path and a reference path share a circuit architecture, the design is simplified, and the chip layout is optimized; the coarse tuning phase shifting unit adopts an all-pass network as a reference path, a phase shifting path is an equivalent band-pass network formed by cascading a high-pass network and a low-pass network, and the 180-degree phase shifter adopts a double-inductor all-pass network to optimize amplitude-frequency response. And the driving circuit module outputs complementary voltage pairs through the level conversion circuit to drive the switching transistor to realize path switching. The antenna has the advantages of being compact in structure, stable in amplitude, excellent in radio frequency performance and high in adaptability.

The invention belongs to the technical field of integrated circuits, and particularly relates to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, the dynamic comparator adopts a three-stage latch circuit structure to realize rapid comparison of weak input signals so as to generate corresponding digital signals, and the method specifically comprises the following steps of: in a pre-amplification stage, pre-amplification is carried out; the positive feedback effect of the cross-coupled transistor pair is utilized to efficiently convert a tiny input voltage difference (lt; 10mV) into a recognizable voltage difference, and then through two-stage regeneration of the main latch module and the auxiliary latch module, a logic level is quickly output to complete quantization judgment. The auxiliary latch stage is additionally arranged on the basis of a traditional cross coupling latch circuit, the working speed of the comparator is effectively increased under the condition that only small area overhead is introduced, and the probability that the dynamic comparator has a metastable state is greatly reduced.

The invention discloses a power supply fault detection method and electronic equipment, and relates to the technical field of integrated circuits, and the power supply fault detection method realizes fault detection of a power supply unit through the power supply unit, a control unit and a service system which are connected, and comprises the following steps: firstly, updating a timestamp of the power supply unit according to the time of the control unit; and the power supply log information is generated and stored in the power supply unit, so that the problem of inaccurate time of the power supply log information in related technologies can be relieved, and the accuracy of power supply fault detection is improved. And on the other hand, the power supply log information stored in the power supply unit is sent to the control unit through the received log reading instruction of the user, so that the problems of resource occupation and bandwidth occupation of the control unit caused by frequent access of the control unit to the power supply unit in related technologies can be relieved; and the operation efficiency of the control unit is improved.

The invention belongs to the technical field of spaceflight electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system capable of resisting single event upset, in particular to a bit-symbol double-layer error correction method of RS decoding operator error correction based on finite field algebra cascading on the basis of two-out-of-three majority voting logic. Single-particle independent upset and multi-copy common-mode failure can be corrected at the same time, and the problem of traditional TMR error locking is solved. Meanwhile, when configuration data are written into a nonvolatile memory, a cross-sector space staggered and dispersed storage mechanism is introduced, symbols in the same RS code word are separated as far as possible in physical positions, and therefore aggregated physical damage is converted into dispersed symbol-level errors.

The invention relates to the technical field of integrated circuits, and provides a multi-nuclear inductance-capacitance type voltage-controlled oscillator, which comprises at least two oscillation units which are symmetrically distributed and a digital control unit, wherein each oscillation unit comprises a switched capacitor array, and the oscillation units are in annular synchronous connection through a synchronous resistor; and the digital control unit is used for generating control signals for respectively controlling the oscillation units so as to control the switches of the switched capacitor arrays in the corresponding oscillation units through the control signals. According to the oscillator, the effect of improving the precision of the oscillator can be achieved by improving the precision of the switched capacitor array.

The invention provides an integrated circuit chip heat dissipation structure optimization design method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: obtaining chip physical structure parameters, power consumption distribution data and heat dissipation requirements, building a three-dimensional thermal field model, determining a hot spot region, designing a honeycomb-shaped phase change material, and optimizing the size and density distribution of the honeycomb-shaped phase change material. And carrying out lightweight design by adopting a topological optimization algorithm, and finally generating machining process parameters. According to the invention, accurate heat dissipation for the hot spot area of the chip is realized, the heat dissipation efficiency is improved, the material usage amount is reduced, and the service life of the chip is prolonged.

The invention discloses a bandwidth expansion circuit, a chip and a receiver, and belongs to the technical field of analog integrated circuits. The bandwidth expansion circuit comprises a signal compensation equalization module, a first bandwidth boosting module and a second bandwidth boosting module, the signal compensation equalization module is used for carrying out equalization amplification on a high-frequency component in the received first signal and outputting an equalized and amplified second signal; the second bandwidth boosting module is used for feeding back the extracted low-frequency component to the output end of the signal compensation equalization module so as to lower the low-frequency component in the second signal; the first bandwidth boosting module is used for offsetting high-frequency attenuation of the capacitive load on the second signal after the low-frequency component is reduced, and sending a third signal after offsetting the high-frequency attenuation through the signal output end; and the second bandwidth boosting module is also used for extracting a low-frequency component from the third signal. Through the combination of various technologies of compensating channel attenuation, counteracting capacitance influence, lowering low-frequency components and the like, the effective improvement of the circuit bandwidth is realized.

The invention relates to the technical field of photoelectric sensing and integrated circuits, and particularly provides a reconfigurable convolution weight loading and reading system of a sensing and computing integrated visual chip, which comprises a reconfigurable convolution weight loading system, a sensing and computing integrated pixel array, a column merging reading system and a time sequence control module, the reconfigurable convolution weight loading system is used for configuring a multi-scale convolution kernel, converting a digital weight into an analog voltage signal, and loading the analog voltage signal to the sensing and computing integrated pixel array by adopting a reconfigurable convolution weight loading mechanism based on a 13 * 13 weight loading array; the sensing and computing integrated pixel array is used for carrying out pixel-level visual information sensing and parallel convolution calculation on the analog voltage signals, the column merging reading system is used for reading a parallel convolution calculation result of the sensing and computing integrated pixel array, and the time sequence control module is used for providing time sequence control signals. According to the method and the device, multi-scale convolution kernel configuration is realized, convolution results of different convolution kernel sizes and step lengths are read, and diversified visual processing requirements are met.

The present application relates to a kind of pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection, belong to analog integrated circuit technical field.After the residual error signal is obtained in the first stage SAR ADC quantization, pseudo-random sequence is injected in the residual error signal, the superimposed signal is sampled and converted by the later stage ADC, finally cause nonlinear error in digital code output code, then the sequence input and digital output code are correlated to obtain the error information of non-ideal factor in circuit, finally the actual interstage gain value in circuit is approximated by variable step iterative algorithm for digital code reconstruction analog signal, finally reach the effect of calibration.The present application can avoid the influence of step on speed and accuracy in iterative process, be used to calibrate the interstage gain error caused by capacitor mismatch and the limited gain of operational amplifier, and in the iterative process of calibration, better speed and accuracy are realized, the performance of ADC is obviously improved, and signal-to-noise ratio and spurious-free dynamic range are improved.

The invention discloses a hybrid precision in-memory computing accelerator for low-illumination image enhancement, and relates to the technical field of integrated circuits. A top controller is used for global control and data scheduling; the SRAM read-write circuit is used for completing pre-loading and updating of weight data; the row / column decoder and the input buffer are used for realizing line-by-line input of activation data; the in-memory computing array comprises a plurality of SRAM (Static Random Access Memory) storage units and corresponding in-memory logic circuits, and is used for completing multiplication of weights and activated data; the peripheral accumulation circuit is used for receiving a calculation result of the in-memory calculation array, and completing multiplication and accumulation operation of convolution and a full connection layer through inter-row accumulation and channel fusion; and the ReLU activation module is used for realizing ReLU activation operation in the low-illumination image enhancement network. According to the in-memory computing accelerator, low-bit-width parallel and high-bit-width serial are adopted, so that the delay is halved, and the throughput rate is remarkably improved.