1846 results about "Asic technology" patented technology

The invention provides a dynamic method and system for thermal fatigue evaluation of integrated circuit packaging, and relates to the technical field of integrated circuits, and the method comprises the steps: employing a genetic algorithm to determine the arrangement position of a temperature sensor, and collecting a temperature data sequence of a temperature sensor array and the corresponding time information; establishing a thermal-mechanical coupling analysis model comprising a geometric model, a material constitutive relationship and a load boundary, and performing mesh generation on the thermal-mechanical coupling analysis model to obtain a finite element model; based on the finite element model, periodically solving by adopting a nonlinear iterative algorithm to obtain a welding spot stress-strain field data sequence and time information corresponding to the welding spot stress-strain field data sequence, establishing a corrected Coffin-Manson model considering a temperature-stress-time coupling effect, calculating a fatigue damage increment of the welding spot, and accumulating the fatigue damage increment in real time; and performing thermal fatigue state evaluation on the integrated circuit packaging structure according to the change rate of the accumulated fatigue damage value.

The invention relates to a backside illuminated image sensor and a preparation method thereof, and electronic equipment, and relates to the technical field of integrated circuits, the backside illuminated image sensor comprises a substrate, and photodiodes and laminated isolation structures which are located on the substrate, are alternately arranged along a first direction parallel to the surface of the substrate, and extend along the direction towards the substrate. The photodiode comprises an isolation layer, a first photosensitive layer, a second photosensitive layer and a third photosensitive layer which are sequentially stacked in the direction away from the substrate. The first photosensitive layer internally comprises a plurality of first SiP layers arranged at intervals in the first direction, and the first SiP layers penetrate through the first photosensitive layer in the second direction and extend to the isolation layer. And the third photosensitive layer internally comprises a plurality of second SiP layers which are arranged at intervals along the first direction, and the plurality of second SiP layers penetrate through the third photosensitive layer along the second direction and extend to the second photosensitive layer, so that the number of photon-generated carriers can be increased, and the quantum efficiency of the device can be improved.

The invention relates to a backside illuminated image sensor and a preparation method thereof, and electronic equipment, and relates to the technical field of integrated circuits, the backside illuminated image sensor comprises a substrate, and photodiodes and laminated target isolation structures which are located on a first surface of the substrate, are alternately arranged along a first direction parallel to the first surface, and extend towards the substrate; the substrate internally comprises a plurality of trench isolation structures which extend into the substrate through the first surface and are arranged at intervals in the first direction; the trench isolation structures and the laminated target isolation structures right above the trench isolation structures are arranged in a one-to-one manner; the laminated target isolation structure comprises isolation parts and insulation parts which are sequentially and alternately laminated along a second direction deviating from the substrate; the photodiode comprises at least two photosensitive layers which are sequentially stacked in the second direction, the longitudinal sections of the photosensitive layers are T-shaped, one photosensitive layer makes contact with the first surface of the substrate, substrate damage caused by ion implantation can be avoided, and meanwhile the photoelectric conversion efficiency and the quantum efficiency are improved.

The invention relates to a backside illuminated image sensor and a preparation method thereof, and an electronic device, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises an isolation layer and a plurality of first isolation structures which are arranged at intervals in a first direction parallel to the surface of the substrate; forming first isolation parts in the substrate, wherein the first isolation parts and the first isolation structures are arranged in a one-to-one manner and extend to the isolation layer through the back surface of the substrate; removing the substrate between the adjacent first isolation parts to obtain side wall semiconductor layers located on the side surfaces of the first isolation parts and first grooves between the adjacent side wall semiconductor layers; the size of the side wall semiconductor layer is gradually increased in the direction close to the isolation layer. And forming a bottom photosensitive layer in the first groove, and epitaxially growing a top photosensitive layer on the bottom photosensitive layer. And forming a second isolation part connected with the first isolation part in a gap between the adjacent top photosensitive layers, thereby improving the photoelectric conversion efficiency and the quantum efficiency.

The invention provides an integrated circuit packaging quality evaluation method and system based on a nondestructive testing technology, and relates to the technical field of integrated circuits, and the method comprises the steps: obtaining a three-dimensional fluorescence response signal of a packaging structure through a two-photon excitation microscopic system, and building a stress distribution characteristic graph and a stress gradient grading graph through the analysis of the spatial distribution of the fluorescence signal; a quantum state nitrogen vacancy probe array is arranged in the stress abnormal area, electromagnetic field response signals of the quantum state nitrogen vacancy probe array under the stress effect are collected, and accurate mapping of a stress field and an electromagnetic field of the packaging structure is achieved; based on the obtained multi-physical field data, establishing a thermal electromagnetic coupling equation set, and calculating an interaction relationship among the physical fields; by analyzing evolution characteristics of each detection area under the multi-field coupling effect, a stability evaluation system including a mechanical failure risk and an electromagnetic failure risk is established, and accurate evaluation of the quality grade of the packaging structure is realized.

The invention discloses a fault monitoring method and system for an analog integrated circuit, and relates to the technical field of integrated circuits, and the method comprises the steps: collecting and recording the electrical parameter data of the analog integrated circuit; preprocessing the electrical parameter data, calculating the resource utilization rate of each subunit and extracting fault feature information; constructing a digital twinborn model corresponding to the analog integrated circuit, and simulating and predicting a fault based on the digital twinborn model; according to the electrical parameter data, the resource utilization rate and the fault feature information, a reinforcement learning algorithm is introduced, and a fault early warning strategy is optimized based on a simulated predicted fault; and according to the fault early warning strategy, early warning thresholds and early warning levels of different fault types are dynamically adjusted, and fault monitoring is realized. According to the invention, abnormal conditions can be found in time, greater damage to the system caused by potential faults is avoided, the real-time performance and accuracy of the monitoring system are ensured, fault information is rapidly provided for maintenance personnel, and the maintenance efficiency is improved.

The invention relates to the technical field of integrated circuits, in particular to a processing system of a single-precision configurable matrix operation unit based on RISC-V instruction expansion, which comprises an RISC-V processor used for executing a software program and identifying a user-defined expansion instruction, and the RISC-V processor is connected with the single-precision configurable matrix operation unit through a user-defined coprocessor interface; the single-precision configurable matrix operation unit comprises an instruction response and decoding module and an instruction retirement and write-back module, and the instruction response and decoding module is used for receiving an instruction function code, source operation data and a destination register number and decoding the instruction function code; after decoding is completed, different execution units are selected according to a decoding result to send corresponding control signals; and after the execution unit completes the corresponding task, the instruction retirement and write-back module returns an execution result and a completion signal to the RISC-V processor, so that execution of a self-defined extension instruction is completed. According to the system, the matrix operation speed can be accelerated through bottom hardware under limited hardware resource consumption.

The invention relates to a backside illuminated image sensor and a manufacturing method thereof, and relates to the technical field of integrated circuits. The manufacturing method comprises the steps that a substrate is provided, the substrate comprises a first surface and a second surface which are opposite, a first isolation structure is formed in the substrate, and the first isolation structure extends from the first surface to the second surface; second isolation structures and metal grids are formed, the second isolation structures correspond to the first isolation structures and are arranged on the first surface, the second isolation structures are arranged on the first surface at intervals, and the second isolation structures and the metal grids are sequentially arranged in the direction away from the first surface; forming photodiodes between the second isolation structures, wherein the photodiodes and the second isolation structures are alternately arranged on the first surface; forming a light filtering element on one side, far away from the substrate, of the photodiode, wherein the light filtering element is located between the adjacent metal grids; according to the invention, the crosstalk problem of the backside illuminated image sensor is reduced.

The invention discloses a UVM verification platform and a verification test execution method, and relates to the technical field of integrated circuits, the verification platform comprises a file management module used for sending a test case file to a script processing module; the script processing module is used for acquiring a test case name and a hardware parameter according to the test case file, and sending the test case name and the hardware parameter to the command generation module; the command generation module is used for generating a target simulation command according to the test case name and the hardware parameters and sending the target simulation command to the compiling library; and the compiling library is used for verifying and testing the design unit according to the basic use case information and the target simulation command. According to the technical scheme, on the premise that the number of the test cases is not changed, the scale of the compiling library of the UVM verification platform is reduced, the compiling time consumption and the dynamic simulation time consumption of the compiling library are reduced, and the verification test execution efficiency of the UVM verification platform is improved.

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The invention relates to the technical field of integrated circuits, and provides a clock domain crossing synchronization circuit and method based on a multiphase clock, and the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor. Wherein serial data to be transmitted and a low-frequency clock are input into the selector, and the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and a clock of the digital signal processor; and the digital signal processor is used for carrying out data processing on the alignment data. According to the invention, stable transmission of low-delay cross-clock domain data can be realized.

The invention discloses a VLSI circuit layout optimization method and system based on deep learning in the technical field of integrated circuits, and the method comprises the steps: abstracting a large-scale integrated circuit into a hypergraph structure, receiving the hypergraph structure, generating a node embedding matrix through a hypergraph neural network, and optimizing a segmentation loss function through unsupervised training, obtaining a probability distribution matrix, determining segmented subsets based on the probability distribution matrix, mapping each subset to a physical layout unit, generating a physical region layout of the chip according to an area equilibrium constraint and a time sequence constraint, performing constraint feedback on a physical layout result, and dynamically adjusting parameters of the segmentation loss function. The method can be used for circuit layout of a super-large-scale integrated circuit, and an optimization method and means are provided for providing a high-quality VLSI circuit layout scheme.

The present application relates to the technical field of integrated circuits, relates to a computing-in-memory circuit based on BNN algorithm acceleration, and solves the problems in the prior art of a large circuit area, high energy consumption, and low energy efficiency of computing-in-memory. The circuit comprises: selecting a first algorithm network and a second algorithm network from a flexible RRAM storage array; inputting a plurality of rows of data into the first algorithm network and a multiply-accumulate module to obtain a multiply-accumulate result, and inputting the multiply-accumulate result into a shifter; the shifter shifting the multiply-accumulate result, outputting the shifting result to an adder-subtractor to obtain a sum-calculation result and outputting the sum-calculation result to a comparator; the comparator performing binarization on the sum-calculation result, outputting the binarized sum-calculation result to a second algorithm network, performing recalculation to output a column accumulate current, and sending the column accumulate current to a maximum value comparator output module; and the maximum value comparator output module determining a column having the maximum column sum as a classification result. While keeping the original network precision, the required circuit area is greatly reduced, the energy consumption is reduced, and the energy efficiency of the entire computing-in-memory circuit is improved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a speed-adjustable fan driving and anomaly detection circuit with high reliability and low cost. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed; the open circuit and locked-rotor detection module is connected with the logic control module and the VIN port of the LDO; and the short circuit detection module is connected with the logic control module and the output end of the LDO, outputs a signal to a state flag bit FTO, and judges whether the fan is in a normal working state, an open circuit state, a locked-rotor state or a short circuit state or not according to the waveform and the level of the state flag bit FTO. The speed-adjustable fan driving circuit is integrated, and the function of detecting various abnormal states of the fan is achieved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a nitride HEMT device with a light-emitting structure and a preparation method of the nitride HEMT device. The HEMT device comprises a heterojunction epitaxial wafer, a light-emitting structure, a grid electrode, a source electrode and a drain electrode. The heterojunction epitaxial wafer sequentially comprises a substrate, a buffer layer formed by III-group nitride, a channel layer and a barrier layer from bottom to top. The light-emitting structure is prepared through a selective area epitaxial growth technology and sequentially comprises a quantum well layer, a P-type nitride layer, a current expansion layer and a P-type electrode from bottom to top. Wherein the quantum well layer can also be used as a barrier layer, and the P-type electrode and the drain electrode are interconnected through metal. According to the invention, the drain electrode of the nitride device is connected with the P-type electrode of the light-emitting structure, so that when the device is turned on, the quantum well layer of the light-emitting structure emits light at the same time, photons are incident into the device body, electrons in various deep energy levels in the device body are effectively accelerated to break away from traps, the current collapse effect of the device is effectively inhibited, and the stability of the device is improved.

The invention provides an integrated circuit chip electromagnetic interference intelligent suppression and shielding method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: collecting chip electromagnetic interference data, and carrying out the time-frequency domain decomposition and feature extraction, so as to obtain an initial electromagnetic interference feature vector; calculating an electromagnetic interference threat index based on state space mapping and action space search, and further evaluating the electromagnetic interference situation and determining the minimum shielding strength; carrying out optimization design on the electromagnetic shielding structure by adopting a gradient-guided genetic algorithm to obtain an optimal shielding structure parameter; real-time electromagnetic interference data are adjusted according to the parameters, the suppression ratio is calculated, and iterative design is carried out by combining the suppression ratio optimization genetic algorithm. According to the invention, intelligent evaluation and dynamic suppression of electromagnetic interference are realized, and the accuracy and adaptability of shielding structure design are improved.

The invention belongs to the technical field of integrated circuits, and particularly relates to a speed regulation driving and anomaly detection circuit of a cooling fan. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the VIN port of the LDO, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to the level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention belongs to the technical field of integrated circuits, and particularly relates to an integrated speed regulation fan and an abnormal state detection circuit. Comprising a current expansion driving module for providing a voltage FCC stabilized by an LDO for a fan and performing current expansion on an output current of the LDO to drive the fan; the logic control module is connected with the current expansion driving module and is used for adjusting a control signal ADJlt; n: 0gt; the value of the voltage FCC output by the LDO is changed, so that the speed of the fan is regulated; and the sampling detection module is connected with the logic control module and the fan, samples the current of the fan through a sampling resistor, converts the current into a voltage V0, compares the voltage V0 with a reference voltage Vref, and outputs a voltage signal to a level shift circuit. The speed-adjustable fan driving circuit is integrated, detection of various abnormal states of the fan is achieved, and the speed-adjustable fan driving circuit has the outstanding advantages of being simple in PCB layout and low in cost.

The invention provides a rule-based layout check and automatic correction system, which relates to the technical field of integrated circuits, and comprises a rule input and management module, a layout data processing module, a rule check engine, a problem analysis and visualization module, an automatic correction module and a user interaction and control interface. Through a rule template library and a complex rule analysis mechanism, an efficient rule configuration mode is provided for a user, and the user can quickly adjust parameters based on a preset template to generate a user-defined design rule, or directly upload complex rule description containing a regular expression and a mathematical formula; and the system analyzes the data into executable logic units and stores the executable logic units in a rule database. According to the mode, the complexity and the time cost of design rule configuration are remarkably reduced, so that the system can flexibly adapt to different process nodes and design requirements, the universality and the efficiency of layout inspection are improved, and convenient and diversified rule management experience is provided for designers.

The invention discloses a high-voltage power amplifier with an over-temperature and over-current protection circuit, and relates to the technical field of integrated circuits. The high-voltage operational amplifier comprises a high-voltage operational amplifier core unit and a self-adaptive protection circuit unit, the high-voltage operational amplifier core unit comprises a rail-to-rail input stage, a gain amplification stage and an AB type push-pull output stage which are sequentially cascaded, and the AB type push-pull output stage comprises a PMOS upper power tube and an NMOS lower power tube; the self-adaptive protection circuit unit comprises a PMOS (P-channel Metal Oxide Semiconductor) current-limiting protection circuit, an NMOS (N-channel Metal Oxide Semiconductor) current-limiting protection circuit and an over-temperature protection circuit; the PMOS current-limiting protection circuit is used for generating a high-voltage domain over-current control signal when the power tube on the PMOS is over-current; the NMOS current-limiting protection circuit is used for generating a low-voltage domain overcurrent control signal when the NMOS lower power tube is in overcurrent; the over-temperature protection circuit is used for generating high-voltage domain over-temperature turn-off signals and low-voltage domain over-temperature turn-off signals when the amplifier is over-temperature; and finally, carrying out logic synthesis on the corresponding over-current control signal and the over-temperature turn-off signal to generate a gate clamping signal.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate, forming a third semiconductor layer covering a first semiconductor layer and a second semiconductor layer, the third semiconductor layer comprising an embedded part penetrating through the second semiconductor layer; forming a plurality of isolation parts penetrating through the third semiconductor layer, wherein the plurality of isolation parts are located right above the plurality of first semiconductor layers; forming a plurality of target semiconductor columns arranged at intervals along the first direction in the third semiconductor layer; target doping ions are injected into the remaining third semiconductor layer, so that the target semiconductor columns, the second semiconductor layer and the third semiconductor layer jointly form a plurality of photodiodes. The electron concentration of the photosensitive area is at least increased, and the photosensitive performance of the BSI image sensor is improved.

The present invention relates to the field of integrated circuit technology, and in particular to a method and system for printed circuit board layout. The method comprises the following steps: obtaining printed circuit board data; preprocessing the printed circuit board data to obtain standard printed circuit board data; identifying component features of the standard printed circuit board data to generate circuit board component feature data; extracting power feature information of the standard printed circuit board data to obtain circuit board power feature data; identifying the direction of signal lines of the circuit board component feature data to obtain signal line data; the present invention uses data processing technology, pattern recognition technology, feature mapping technology and deep learning technology to perform electromagnetic coupling analysis on printed circuit board data, and adjusts and optimizes the printed circuit board layout based on the electromagnetic coupling analysis data, thereby ensuring the accuracy of printed circuit board design.

The invention belongs to the technical field of integrated circuits, and particularly relates to a chip-level integrated circuit fault diagnosis method based on improved wavelet entropy, which comprises the following steps: S1, acquiring an original signal of a chip-level integrated circuit, and reconstructing the original signal by using a VMD signal reconstruction technology; s2, performing deep processing on the reconstructed signal by adopting an improved wavelet entropy method, and extracting key features of a fault signal; s3, monitoring the voltage change of each node through the key characteristics of the fault signal, and effectively positioning the fault position; and S4, setting a fault factor which can comprehensively consider the fault position, the attenuation degree and the fault length, comparing the fault factor with a set threshold value, and judging the severity of the fault, thereby realizing the online diagnosis of the fault of the chip-level integrated circuit. According to the invention, by introducing the adaptive wavelet basis selection and multi-scale wavelet entropy fusion technology, the accuracy and efficiency of diagnosis are significantly improved, the repeatability of fault signal feature extraction is reduced, and the real-time performance and stability of a diagnosis system are improved.

The invention discloses a multi-precision matrix calculation unit and a use method thereof, and relates to the technical field of integrated circuits, the multi-precision matrix calculation unit comprises a control logic unit, a cache module and a calculation array; wherein the control logic unit is used for configuring a computing array and controlling the cache module to read in and read out data; the cache module comprises three first cache sub-modules and one second cache sub-module; wherein the three first cache sub-modules are respectively used for caching a first to-be-processed matrix, a second to-be-processed matrix and a third to-be-processed matrix, and the second cache sub-module is used for caching a result matrix; and the calculation array is used for carrying out multiplication and addition operation on different types of to-be-processed matrixes to obtain a result matrix and writing the result matrix back to the cache module. The method can serve as a basic operation core for integrated processing of large-scale matrix multiplication and can also be integrated in processors such as RISC-V for matrix operation, universality is higher, and the method can adapt to fast and efficient calculation scenes.

The invention belongs to the technical field of integrated circuits, and particularly relates to an analog circuit yield optimization method under multiple environment angles based on a Bayesian neural network. According to the method, a Bayesian neural network (BNN) is used for carrying out synchronous modeling on yield and nominal performance under multiple environment angles, and yield optimization under the multiple environment angles is executed by embedding the BNN into a Bayesian optimization framework. The BNN model provided by the invention can better learn the correlation between the yield and the performance under different environmental angles, provides a strong modeling capability for the yield and the uncertainty thereof, and improves the yield optimization efficiency. Compared with other baseline methods, under the condition that the same target yield is achieved, the circuit simulation time cost can be saved by 45.3%, under the same circuit simulation time cost, a design point with the higher yield can be obtained, and the yield is improved by 3.2%.

The utility model relates to the technical field of radio frequency integrated circuits, in particular to a phase shifter circuit and a multi-phase shifter circuit, which comprise an input node, an output node, a first signal path and a second signal path, the first signal path comprises a first switch, a second switch and a decoupling structure, the decoupling structure comprises a first inductor, a second inductor and a third inductor, the first inductor and the second inductor are connected in series, one end of the third inductor is connected to a connecting line node of the first inductor and the second inductor, and the other end of the third inductor is grounded; the second end of the second inductor is connected to the second switch; the second signal path includes a third switch, a fourth switch, and an anti-coupling transformer. The phase shifter circuit provided by the utility model solves the technical problem of poor phase flatness of a phase shift unit in a traditional phase shifter, improves the phase flatness, has broadband operating characteristics and low insertion loss, and reduces the chip area of the phase shifter circuit.

The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking, relates to the technical field of integrated circuits, and is used for solving the technical problems that an existing injection locking oscillator limits the frequency tuning range and cannot effectively suppress noise. The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking. The low-phase noise ring voltage-controlled oscillator comprises a first ring oscillator unit and a second ring oscillator unit, the n first ring oscillator units are connected in series to form a chain structure; the second ring oscillator unit is provided with a cross coupling inverter complementary injection unit and a tail current source injection unit; a first output end of the chain structure is connected with a second input end of the second ring oscillator unit, and a second output end of the chain structure is connected with a first input end of the second ring oscillator unit; a first signal is injected into a cross-coupling inverter complementary injection unit and a tail current source injection unit, and a second ring oscillator unit receives a second signal output by a chain structure and then outputs a third signal.

The invention belongs to the technical field of integrated circuits, and particularly relates to a multichannel ultrasonic imaging special integrated circuit suitable for integrated packaging. The application-specific integrated circuit is formed by cascading a plurality of multi-channel single chips, the multi-channel single chips adopt four ultrasonic channel input architectures, and each channel comprises an ultrasonic analog front end, an analog-to-digital converter and an ultrasonic digital signal processing module; the ultrasonic analog front end comprises four sub-modules, namely a low-noise amplifier, a voltage control attenuator, a programmable gain amplifier and an anti-aliasing low-pass filter; the analog-to-digital converter adopts a three-stage successive approximation register pipeline cascade structure to realize 14-bit digital output; the ultrasonic digital signal processing module is used for processing the ultrasonic signals quantized by the ADC, including ADC data preprocessing, data demodulation, signal interpolation and extraction, beam forming, test signal generation and the like; the number of channels is expanded through SIP packaging, and the method can be used for ultrasonic imaging of medical ultrasonic diagnosis and has high flexibility and expandability.

The present application relates to the technical field of integrated circuits and relates to a matrix operation apparatus based on a flexible RRAM memory-computing array, and solves the problem in the prior art of the inability to reduce the area of the memory-computing array without affecting the precision. The apparatus comprises: the flexible RRAM memory-computing array for outputting cumulative currents of columns of memory-computing units to a multiplexer (MUX) on the basis of multiple rows of inputs; the MUX for selecting the cumulative current of one column of memory-computing units from among the columns of memory-computing units and sending said cumulative current to an analog-to-digital converter (ADC); the ADC for converting the received cumulative current into a digital signal and sending said digital signal to a subtractor; a popcount module for receiving the multiple rows of inputs, obtaining the number of 1 in the multiple rows of inputs, and outputting the number of 1 to a multiplier; the multiplier for multiplying the number of 1 by a fixed value β and sending a product result to the subtractor; and the subtractor for subtracting the product result from the digital signal to obtain a multiply-accumulate result of the matrix. The present application realizes high-precision memory-computing based on a small-area memory-computing array, further enhances energy efficiency, and can be applied to flexible computing chips to create electronic skin.

The invention relates to the technical field of integrated circuits, in particular to a band-gap reference voltage source, which comprises a high-order compensation circuit, a low-order compensation circuit, a low-order compensation circuit, a low-order compensation circuit and a low-order reference circuit, the band-gap reference circuit is used for generating a positive temperature coefficient voltage and a negative temperature coefficient voltage, performing first-order temperature compensation on the negative temperature coefficient voltage by using the positive temperature coefficient voltage, performing high-order curvature compensation on the negative temperature coefficient voltage based on the target compensation current, determining the compensated voltage as a reference voltage and outputting the reference voltage; according to the band-gap reference voltage source, high-order compensation is introduced through the sub-threshold MOS tube, the negative temperature coefficient voltage can be well reduced, the reference voltage with the temperature coefficient approximate to zero is obtained, and practicability is high.