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781 results about "Frequency correction" patented technology

The Frequency Correction Channel is a broadcast channel used by GSM base stations. It provides a unique tone of 67.7 kHz for the Mobile Stations. This tone is used to synchronize the local clock of the mobile receiver with the base station. This is needed to correctly extract the data.

Low energy consumption RF telemetry control for an implantable medical device

In an implantable medical device, a frequency synthesizer employed in the RF transceiver of the IMD operating system functions in a PLL LOCK mode wherein the VCO frequency is governed by the PLL and an energy saving HOLD mode wherein the PLL is not operational and the VCO generated carrier frequency can drift over time. The PLL circuit is powered up and coupled with a control voltage input and the output of the VCO to develop a frequency control voltage stored by a capacitive loop filter during initial LOCK portions of both uplink and downlink telemetry transmission time periods. A frequency modulation (FM) input of the VCO receives data bit modulation voltages that modulates the carrier frequency during uplink transmission of patient data. During the HOLD portion of a downlink telemetry transmission, an AFC algorithm is enabled and derives a frequency correction value from the difference in frequency of the constant received carrier frequency and the drifting VCO generated carrier frequency, and the frequency correction value is applied to the VCO FM input to compensate for loop filter capacitor discharge of the control voltage causing the drift. The AFC algorithm derived frequency correction value is stored in memory and is also applied during the HOLD portion of an uplink telemetry transmission to the VCO FM input to compensate for loop filter capacitor discharge of the control voltage causing the drift. In addition, a recharge current is applied to the capacitive loop filter.
Owner:MEDTRONIC INC

Method for automatic frequency control

A radio signal transmitted from a transmitter to a receiver of a mobile communications system, such as the GSM system, often suffers from a phenomenon known as frequency offset by which the frequency of the radio signal is changed from a first frequency to a second frequency. A method is therefore provided for automatically correcting the frequency at the receiver to restore the received radio signal to approximately the first frequency using a multistage frequency correction algorithm. The radio signal comprises a training sequence that is known to the receiver and data symbols that are not known to the receiver. In the first stage of the frequency correction, the frequency offset is coarsely estimated based on the training sequence only, and the data symbols are frequency corrected by back-rotating the received data symbols and the training sequence by the frequency offset estimate. The frequency corrected data symbols and training sequence are then input into the second stage of the frequency correction where they are used to determine a second estimate of the frequency offset that should be more accurate because the second estimate of the frequency offset is based on a larger number of symbols including symbols in the previously frequency corrected training sequence and data symbols. Using this second frequency offset estimate, the data symbols in the received radio signal are frequency corrected by back-rotating the received data symbols by the second frequency offset estimate and are output for detection.
Owner:NOKIA NETWORKS OY

Automatic circuit and method for temperature compensation of oscillator frequency variation over temperature for a real time clock chip

An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the frequency correction.
Owner:INTERSIL INC

Wireless receiver

A wireless receiver designed to conform to the standard IEEE 802.15.4. The receiver comprises an analog front-end and a digital decoder. The analog components of the front end include one or more amplifiers and an analog-to-digital converter (ADC). The digital decoder receives the output of the ADC and demodulates it in a demodulator which is driven at an a chip frequency by an internal or external clock. The demodulator comprises a sampler operable to sample the digital signal at a sampling frequency and a correlation unit operable to process a set of bits, referred to as a chip code, in the sampled digitized signal and output therefrom a set of correlation values. The set of correlation values is an indicator of likely mapping between the chip code that has been processed and a set of possible chip codes defined according to the standard. The demodulator further comprises a symbol selection unit and a frequency correction unit. The symbol selection unit has the function of deciding which symbol has been received based on an analysis of each set of correlation values. The frequency correction unit is operable to make adjustments to the chip frequency based on the correlation values output from the correlation unit, specifically to increase or decrease the chip frequency based on a measurement of whether the maximum correlation value among each set of correlation values occurs earlier or later than predicted. This scheme has the advantage that phase and frequency compensation is done after correlation avoiding the need for coherent demodulation while at the same time not requiring the stringent specifications of a conventional non-coherent demodulation scheme.
Owner:CASCODA

Frequency synchronizer

A frequency synchronizer system is based on the maximum likelihood criterion from estimation theory and that can achieve both frequency acquisition and frequency tracking without requiring knowledge at the receiver of the carrier's phase angle, baud timing, or a preamble consisting of known signal symbols. The synchronizer includes a processor for executing the following sequence of operations: a) initializing an estimated frequency correction factor; b) determining a corrected frequency offset value from a first product of a sample signal and the estimated frequency correction factor; c) filtering a first sample of the corrected frequency offset value to obtain a filtered corrected frequency offset value; d) imparting a delay to a second sample of the corrected frequency offset value to obtain a delayed corrected frequency offset value; e) determining a conjugate product value from a second product of the filtered corrected frequency offset value and a conjugate of the filtered corrected frequency offset value; f) determining a delay conjugate value from a third product of the delayed corrected frequency offset value and the conjugate product value; g) determining an error signal from the delay conjugate value; h) determining a frequency offset value from the error signal; and i) determining an updated value of the estimated frequency correction factor from the frequency offset value.
Owner:THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY

Data aided frequency synchronisation in cellular mobile equipments

Some improvements to the conventional algorithms for data aided frequency synchronisation in cellular systems are introduced in a new method executable by the user equipments of various standards, i.e. 3GPP CDMA-TDMA, FDD mode at 3.84 Mcps, TDD mode at 3.84 Mcps, TDD mode at 1.28 Mcps; CWTS TD-SCDMA; GSM/DCS/GPRS. The method begins to obtain the suboptimal frequency errors Deltafi using a well known formula which calculates the argument of the autocorrelation over a subset of the baseband samples of the detected training sequence. The errors Deltafi are stored into a shift register L-position long and averaged to obtain an estimated frequency error Deltafi used for recursively correcting the reference frequency of the local oscillator, as: fi=fi-1+KDeltafi where K (0<=K<=1) is a weighting factor. Contrarily to the simple averaged error of the prior art, a sign criterion is used by which the average is performed on the only terms having the most recurrent algebraic sign among the stored terms Deltafi. The content of the shift register is corrected after each non-null frequency correction by subtracting K.Deltafi to all the stored terms Deltafi. Besides the frequency is corrected upon the following optional conditions, each other independents: The number of terms Deltafi having equal algebraic sign is greater than a constant alpha lower than L. The standard deviation sigma of the averaged terms Deltafi is lower than beta.sigmaold, being sigmaold the sigma of the last non-null frequency correction, and beta a constant >=1. After a minimum number gamma of iterations between two non-null frequency corrections are spent, being gamma a constant comprised between 1 and L. According to another variant the iterations of the recursive update are subdivided into an initial group with a higher K value for achieving fast convergence and a subsequent group with a lower K for achieving the required accuracy (FIG. 13).
Owner:SIEMENS INFORMATION & COMM NEWTWORKS INC

Frequency correction method and system of phase-locked loop

The invention provides a frequency correction method and system of a phase-locked loop. The frequency correction method and system of the phase-locked loop are applied to selection of sub-bands of multi-band voltage-controlled oscillators. The method includes the steps that in the counting time TCNT [k], frequency counting is conducted on frequency signals output by a voltage-controlled oscillator at the current working sub-band, and a frequency count value FCNT[k] is obtained, wherein the current working sub-band corresponds to a binary value of a current node in a binary search tree; the error between the FCNT [k] and a target frequency count value FCNTTARGET [k] is calculated, the absolute value of the error is compared with a predetermined value, the TCNT [k] is adjusted dynamically in value range of the TCNT [k] according to a comparison result, and a target working sub-band of the voltage-controlled oscillator is determined by combining the binary search algorithm. According to the method, the measurement error is compared with the predetermined value, and therefore whether a counting time reference is increased or not is controlled; a correct choice is made between correction time and correction accuracy, and therefore the correction time is effectively controlled; the dynamic correction method can effectively shorten the correction time on the whole.
Owner:HUAWEI TECH CO LTD

High speed multi-dimensional vibration measuring device and method based on stripe target

The invention relates to a high speed multi-dimensional vibration measuring device and method based on a stripe target. The device comprises a stripe target, an imaging module, a signal control and processing module and a display module. The method includes the following steps: arranging the stripe target on a vibration structure to be measured; adopting an image module to conduct continuous imaging and recording on the stripe target; utilizing the imaging module to transmit the image of the stripe target to the signal control and processing module; utilizing the signal control and processing module to conduct Fourier transform on the stripes at the same position of the same stripe target in each frame of the image, adopting a certain peak value frequency correction method to accurate correct the peak value frequency, and then utilizing the imaging mathematical relation and the corrected peak value frequency to obtain a time domain curve with stripe target structure vibration, namely acquiring structure vibration signals through reduction; displaying an image processing result through a display module or conducting further data processing through vibration signals. By means of the device and method, vibration measurement of points, lines and faces in certain range is achieved, the measurement speed is high, and the accuracy is high.
Owner:FUZHOU UNIV

Self-correcting frequency synthesizer capable of optimizing properties of voltage-controlled oscillator and optimizing method of self-correcting frequency synthesizer

The invention discloses an optimizing method of a self-correcting frequency synthesizer capable of optimizing properties of a voltage-controlled oscillator. The method comprises the following steps that: when a chip is electrified or a channel is changed each time, a frequency self-correcting loop in a synthesizer self-correcting circuit is started firstly, and a frequency sub-wave band code necessary for the voltage-controlled oscillator is searched; secondly a current self-correcting loop in the synthesizer self-correcting circuit is started, and a current sub-wave band code that an output amplitude of the voltage-controlled oscillator achieves an appointed amplitude is searched, so that the voltage-controlled oscillator works in a minimum power consumption, a good phase noise property is obtained, and at the same time the properties of the voltage-controlled oscillator are not changed when process deviation and temperature change occur; after the accomplishment of frequency correction and current correction is judged by a state machine, a synthesizer enters into the frequency self-locking process of a phase-locked loop; and the optimization and correction process is ended. The invention further discloses the self-correcting frequency synthesizer capable of optimizing the properties of the voltage-controlled oscillator. A wider frequency adjustment range can be obtained, and good local oscillator spectrum purity is obtained through small power consumption; and the optimizing method is suitable for the self-correcting frequency synthesizer of a transceiver with low power consumption, multiple modes and multi-band frequency.
Owner:杭州中科微电子有限公司

Frequency control method, frequency control device, multi-split air conditioner and storage medium

The invention discloses a frequency control method, a frequency control device, a multi-split air conditioner and a storage medium. The frequency control method comprises the following steps that whenthe multi-split air conditioner is in the heating operation, a capability requirement identification value corresponding to each indoor unit in all indoor units in the running state, set temperatureand indoor environment temperature are acquired at interval preset time so as to determine the initial operating frequency of a compressor in each preset time; in each preset time, outdoor environmenttemperature is acquired; a target frequency correction coefficient within each preset time is determined according to the outdoor environment temperature; and the initial operation frequency within each preset time is corrected according to the target frequency correction coefficient so as to determine the target operating frequency of the compressor. According to the frequency control method, the frequency control device, the multi-split air conditioner and the storage medium, the problems that the accuracy of the tube temperature correction frequency of the middle of the indoor unit is lowand the needed time is too long are solved, and the effect of improving the heating capacity of the multi-split air conditioner is achieved.
Owner:GD MIDEA AIR-CONDITIONING EQUIP CO LTD +1
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