36 results about "Frequency-locked loop" patented technology

The invention discloses a wide-frequency three-phase phase-locked loop method, which relates to the technical field of three-phase phase-locked loops and comprises an alternating-current signal acquisition and coordinate transformation unit, a double-reduced-order generalized integrator, a frequency-locked loop frequency estimation unit, a double-second-order generalized integrator, a parallel delay signal cancellation filtering module and a phase-locked loop phase estimation unit. A three-phase power grid voltage signal is input into the alternating current signal acquisition and coordinate conversion unit to obtain a two-phase voltage under a static coordinate system; the double-reduced-order generalized integrator and frequency-locked loop frequency estimation unit outputs a three-phase power grid frequency estimation value and carries out feedforward; and the bisecond-order generalized integrator outputs a three-phase power grid positive sequence component, inputs the three-phase power grid positive sequence component into the parallel delay signal cancellation filtering module to filter out a higher harmonic component, and then inputs the three-phase power grid positive sequence component into the phase-locked loop phase estimation unit to output a three-phase power grid phase estimation value. The method can effectively solve the problem that a traditional phase-locked loop is difficult to lock the phase quickly and accurately when the ship microgrid frequency fluctuates in a large range, and improves the phase-locking precision and dynamic performance.

The invention discloses an electric energy metering method and device based on harmonic self-adaptive observation and zero point tracking type SOGI-FLL. The electric energy metering method comprises the following steps: step 1, carrying out ADC sampling on voltage and current signals of a power grid; 2, performing frequency rapid estimation on the voltage signal based on a zero point tracking frequency-locked loop, and obtaining a fundamental wave angular frequency of a power grid in real time; step 3, constructing adaptive observers of voltage and current by using the fundamental wave angular frequency, and estimating parameters of fundamental waves, harmonic waves and direct current components in voltage and current signals in real time through an adaptive law based on Lyapunov stability; 4, according to the parameter estimation value, the amplitude and phase of the voltage and current are calculated; and step 5, calculating active power and reactive power of each harmonic based on the voltage and current amplitudes and phases obtained in the step 4, and summing to obtain total active power and total reactive power so as to realize metering of active electric energy and reactive electric energy. According to the invention, rapid and accurate metering of fundamental wave and harmonic wave electric energy under complex working conditions is realized.

The application discloses a frequency divider-free phase-locked loop and a reference double-delay frequency locking method thereof. The sub-sampling phase-locked loop architecture receives an output of an oscillator and feeds back the output to a reference double-delay frequency locking loop. The output end of a reference double-delay generator in the reference double-delay frequency locking loop is electrically connected with the input end of a sample-and-hold circuit, and the output end of the sample-and-hold circuit is electrically connected with the input end of an automatic phase error state detector. The sample-and-hold circuit simultaneously receives an oscillator output feedback signal of the sub-sampling phase-locked loop architecture. The output end of the automatic phase error state detector is electrically connected with the input end of an adaptive output frequency corrector, and the output end of the adaptive output frequency corrector is electrically connected with the sub-sampling phase-locked loop architecture. Unequal double-reference clock delays are introduced, the sample-and-hold circuit is combined to realize the detection of the output frequency, a new frequency locking loop working at a reference frequency is used to replace a traditional frequency locking loop, and the problem of high power consumption caused by a high-frequency frequency divider is solved.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a first fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code. A second fast-propagation path is configured to propagate a second code to the digitally controlled oscillator.

The invention relates to a decision-guided frequency compensation type carrier tracking method and system, and belongs to the field of satellite navigation. According to the method, aiming at the tracking lock losing problem caused by overlarge capture frequency deviation and navigation signal bit hopping in a capture-to-tracking link of a traditional frequency-locked loop, after receiving initial frequency deviation and code phase for delay alignment, down-conversion and coherent integration are carried out on intermediate frequency data based on the initial frequency deviation to obtain two groups of values; a frequency discriminator is used for calculating a first frequency difference, reverse frequency compensation is carried out on the first frequency difference to obtain a second frequency difference, frequency offset is synthesized to form two frequency assumptions, subsequent signals are processed in parallel, and correct frequency offset is output by comparing absolute values of coherent integration results, so that the frequency tracking range is effectively expanded, and the bit hopping interference resistance is enhanced. And the stability and the reliability of the navigation receiver in a high dynamic environment are improved.

A system for frequency regulation in a AC power supply system is disclosed, wherein the system comprises an uninterruptible power supply being electrically connected to the AC power supply system and comprising a phase-locked loop and / or a frequency-locked loop for monitoring the frequency of an AC input voltage received from the AC power supply system, wherein the phase-locked loop and / or the frequency-locked loop is / are designed to be operated with an operation frequency being higher than a nominal grid frequency and being selected to detect a deviation of the monitored frequency from the nominal grid frequency within a predefined time span after a frequency drop-off of the monitored frequency occurred, wherein a control signal (19) is generated based on the detected deviation of the monitored frequency from the nominal grid frequency, and wherein the generated control signal is used to regulate the power flow between the uninterruptible power supply.

The invention discloses a fault ride-through method and system for a follow-up network type converter based on linear active disturbance rejection control, and the method comprises the steps: obtaining the actual angular frequency of a power grid and the phase angle of the actual voltage of the power grid, and obtaining the amplitude of the estimated voltage of the power grid and the estimated angular frequency of the power grid through a frequency-locked loop based on an oscillator; adopting an optimal discrete wavelet transform method based on a decision tree, and utilizing the amplitude of the power grid estimation voltage and the power grid estimation angular frequency to judge whether the power grid has a fault; when it is judged that the power grid breaks down, the current difference value between the normal operation current amplitude of the power grid and the fault current amplitude is obtained, and when the current difference value is larger than a current threshold value, the converter is switched from a grid construction type to a grid following type; when it is judged that the power grid breaks down, broadband disturbance of the detected actual voltage of the power grid is compensated, the voltage difference value between the compensated actual voltage amplitude of the power grid and the reference voltage amplitude is obtained, when the voltage difference value is within the voltage range, the converter is switched from a grid following type to a grid constructing type, and dynamic tracking compensation is conducted on fault signals; and the fault ride-through capability is good.

The application discloses a satellite signal lock loss relocation method, system, device and storage medium, the method comprises the following steps: taking the carrier NCO value and code NCO value before lock loss as the center, a two-dimensional search range is constructed; searching in the two-dimensional search range, calculating the non-coherent accumulation value of each grid point, and finding the maximum non-coherent accumulation value; according to the size of the maximum non-coherent accumulation value, judging the peak interval to which the maximum non-coherent accumulation value belongs; when the maximum non-coherent accumulation value belongs to the first peak interval, a traditional frequency-locked loop reentry locking mode is adopted; when the maximum non-coherent accumulation value belongs to the second peak interval, a high-sensitivity reentry locking mode is adopted. The application improves the lock loss relocation sensitivity under weak signals, effectively guarantees the availability of the receiver under weak signals, and solves the problem of lock loss relocation under weak signals.

The present invention constitutes a frequency synchronization loop of an oscillation circuit without using an amplifier for comparing voltages.　This oscillation circuit comprises: an oscillator; and a phase comparison unit that constitutes a feedback loop for the oscillator on the basis of the result of comparing phases obtained by converting the oscillation frequency of the oscillator. The phase comparison unit may include a first sub-oscillator that converts a reference voltage into a phase, and a second sub-oscillator that converts a control voltage obtained by converting the oscillation frequency of the oscillator into a phase. The phase comparison unit may include: a phase frequency detector (PFD) connected to subsequent stages of the first sub-oscillator and the second sub-oscillator; a charge pump circuit connected to a subsequent stage of the PFD; and a loop filter connected to a subsequent stage of the charge pump circuit.

The invention discloses a carrier tracking method, system, equipment and medium for a second-order frequency-locked loop assisted third-order phase-locked loop, and the method comprises the steps: receiving an in-phase integral value and a quadrature integral value outputted by a correlator, and carrying out the second-order frequency-locked loop tracking and the third-order phase-locked loop tracking based on the in-phase integral value and the quadrature integral value, the control quantity of the frequency-locked loop and the phase-locked loop is obtained; estimating a carrier-to-noise ratio and a carrier wave attitude of the received signal corresponding to the in-phase integral value and the orthogonal integral value in real time, and determining a first gain coefficient and a second gain coefficient according to the carrier-to-noise ratio and the carrier wave attitude; and generating a final control quantity of the carrier numerical control oscillator based on the control quantities of the frequency-locked loop and the phase-locked loop, the first gain coefficient and the second gain coefficient. By introducing a real-time sensing and dynamic gain control mechanism based on the carrier-to-noise ratio and the carrier wave fluctuation attitude, weighted fusion of contribution of the frequency-locked loop and the phase-locked loop is realized, and the robustness, the precision and the adaptive capacity of the carrier tracking loop under all working conditions can be improved.

The application provides a virtual synchronous generator control method and system, and belongs to the technical field of virtual synchronous generator control. The value of the grid frequency observed by a low-bandwidth frequency-locked loop, a phase-locked loop or a high-bandwidth frequency-locked loop or phase-locked loop after low-pass filtering is used as a feedforward value of the frequency of the virtual synchronous generator. When the grid frequency observed by the low-bandwidth frequency-locked loop or phase-locked loop is used as the feedforward value, the poles of the equivalent closed-loop transfer function of the frequency-locked loop or phase-locked loop and the zeros of the active-frequency transfer function of the virtual synchronous generator are cancelled. When the value of the grid frequency obtained by using the high-bandwidth frequency-locked loop or phase-locked loop and after low-pass filtering is used as the feedforward value, the poles of the low-pass filter transfer function and the zeros of the active-frequency transfer function of the virtual synchronous generator are cancelled. The application can eliminate the steady-state error of the active power regulation of the virtual synchronous generator, enhance the effect of suppressing the grid frequency change in the low-frequency band, and improve the effect of the virtual synchronous generator on the inertia support of the grid.

This application discloses a method and system for tracking spread spectrum signals, belonging to the field of signal processing. This application generates a spread spectrum digital signal by oversampling the acquired spread spectrum modulated signal. In-phase and quadrature components are generated by mixing, despreading, and coherent integration of this digital signal. Frequency and phase error information are calculated based on the components at continuous time intervals to correct the local carrier. The corrected local carrier is then used to mix the signal to baseband. An adjustable fractional delay is applied, and the instantaneous correlation energy peak is searched to determine the target fractional delay, thereby obtaining code phase error information. After correcting the local pseudocode using this code phase error information, the corrected local carrier and local pseudocode are used to initialize a narrow-bandwidth frequency-locked loop, phase-locked loop, and delay-locked loop, thus initiating precise tracking. This enables high-precision and stable locking of the spread spectrum signal in a short time.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code.

The invention discloses a complex power grid frequency-locked loop method and system based on a steady-state Kalman filter, and the method comprises the steps: constructing a harmonic decoupling network, a steady-state linear Kalman filter based on a dual-second-order generalized integrator, and a frequency-locked loop module with a self-adaptive function, collecting the voltage of a three-phase power grid, and carrying out the calculation of the three-phase power grid. The three-phase power grid voltage is sequentially input into the harmonic decoupling network, the steady-state linear Kalman filter based on the bisecond-order generalized integrator and the frequency-locked loop module with the self-adaptive function, and the estimated voltage angular frequency is output, so that the accuracy and the stability of the frequency-locked loop are improved, and more effective power grid voltage synchronization is realized.

A universal serial bus device for coupling to a universal serial bus host includes a transceiver to receive a data signal having a first frequency from the universal serial bus host, wherein the data signal includes a plurality of specific packets having a periodic characteristic; a packet detector coupled to the transceiver to receive the data signal via the transceiver to generate a reference signal based on the periodic characteristic of the plurality of specific packets; and a frequency locked loop circuit coupled to the transceiver and the packet detector to generate a clock signal having a second frequency based on the reference signal; wherein the first frequency is substantially equal to the second frequency. In other words, the second frequency is adjusted to be close to the first frequency, and the frequency difference between the first frequency and the second frequency is less than 500 ppm.

The invention discloses a DC-DC converter with a frequency locking control loop and a control method of the DC-DC converter, and belongs to the technical field of analog integrated circuits. The converter comprises an error amplifier, a pulse width modulation module, a turn-off time control module and a power tube driving module. According to the method, the output voltage is quickly stabilized and the conduction time is determined through the voltage loop and the current loop; meanwhile, the innovative frequency locking loop detects the switching frequency in real time, compares the switching frequency with an external reference clock, generates a turn-off time reference signal after frequency error integration, further dynamically adjusts the turn-off time of each period by comparing the reference signal with a synchronously generated linear ramp signal, and finally forms closed-loop negative feedback. And the switching frequency is accurately locked at a target value. On the premise that input voltage does not need to be sampled completely, rapid dynamic response comparable with frequency conversion control and accurate frequency locking and excellent EMI characteristics comparable with fixed frequency control are achieved at the same time, and system safety, reliability and electromagnetic compatibility are remarkably improved.

This invention belongs to the field of wireless communication technology and provides a low-jitter, low-reference-spurious orthogonal subsampling phase-locked loop (PLL). It includes a subsampling PLL and a frequency-locked loop. The subsampling PLL includes a functionally multiplexed QVCO, which is a Class F noise-cycled VCO. It comprises two identically structured Class F VCOs with I-core and Q-core noise cycles. The I-core and Q-core Class F VCOs achieve orthogonal outputs through cross-coupling of transistor gates. The sources of the oscillating transistors of both the I-core and Q-core Class F VCOs are connected in series with transistors and form a sixth-order resonant cavity, creating a noise-cycled path. The source output signal of the oscillating transistor is sent to a gate-isolated subsampling phase detector. The sampling switch of the gate-isolated subsampling phase detector is isolated from the outputs of the I-core and Q-core Class F VCOs by transistors to suppress binary frequency shift keying (BFS) effects. This invention features lower jitter, lower reference spurious emissions, lower power consumption, and a higher FoMJ value.

A voltage controller circuit is provided for dynamic frequency and voltage scaling. The voltage controller circuit receives an error signal indicating a frequency error and a code error. The frequency error indicates a first difference between a target frequency and an actual frequency generated by an oscillator, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency. The minimum code corresponds to a maximum frequency that the oscillator generates for a processor to safely operate under a given voltage. The voltage controller circuit calculates a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error, and sends a request to a power management circuit to cause an updated voltage to be supplied to the processor.

The invention discloses an optical storage collaborative transient voltage control method and system. The method comprises the following steps: step 1, observing a grid-connected point voltage amplitude change rate, a grid-connected point voltage frequency and a grid-connected point voltage frequency change rate by using a complex frequency lock loop (CFLL); step 2, in a fault detection module, generating a fault control signal by using the grid-connected point voltage amplitude change rate, the grid-connected point voltage amplitude deviation, the grid-connected point voltage frequency change rate and the deviation between the grid-connected point voltage frequency and a reference value; and step 3, according to the fault control signal output by the fault detection module, performing optical storage cooperative transient voltage control. According to the method, high-performance dynamic support on the system voltage can be realized in a disturbance scene, and the voltage stability in a transient scene is improved.

In order to solve the problems that according to an existing energy storage converter virtual inertia control method, a power grid angular frequency differential signal needs to serve as input, noise is likely to be introduced in a differential operation link, and implementation complexity is high, the invention discloses a virtual inertia implementation method based on a reconstructed second-order generalized integrator-frequency locked loop (RSOGI). According to the method, on the basis of a typical SOGI-FLL control architecture, the mathematical operation relation of output signals of the typical SOGI-FLL control architecture is reconfigured, a frequency-locked loop control loop is constructed, an RSOGI-FLL architecture is formed, power grid angular frequency differential signals can be accurately extracted, and therefore differential operation does not need to be carried out on the power grid angular frequency. According to the method, the problems of noise sensitivity and implementation complexity caused by angular frequency differential operation are effectively avoided, reliable input signals are provided for virtual inertia implementation of the energy storage converter, the energy storage converter can effectively provide virtual inertia support for a power grid, and the method can be widely applied to grid-connected control scenes of various energy storage converters.

This invention discloses an APF control method with frequency adaptation under grid voltage imbalance. The inner loop (voltage loop) uses PI control to stabilize the DC bus voltage, achieving stable energy exchange between the two sides of the converter. The outer loop (current loop) employs a composite control algorithm combining proportional-integral (PI), proportional-complex-integral (PCI), and proportional-resonant (PR) control to achieve precise control of the compensation current. When the grid voltage is balanced, only PI plus PCI control is used, resulting in a large stability margin and fast dynamic response. When the grid voltage is unbalanced, a full-pass filter separates the reference signal into positive and negative sequences. The positive sequence component still uses PI plus PCI control, while the negative sequence component uses PI plus PR control, addressing the poor stability of single PCI control under grid voltage imbalance. A frequency-locked loop is introduced into the system to track and control the grid frequency in real time, improving current control accuracy and simplifying the computational complexity of the control algorithm. This method is applicable to other three-phase inverter control systems.

The application provides a wide-frequency oscillation component detection method and system based on a cascade high-order complex filter, and belongs to the technical field of novel power system wide-frequency oscillation component detection. The method comprises the following steps: a plurality of high-order decoupled complex filters are cascaded to form a cascade high-order decoupled complex filter, and a frequency-locked loop is arranged in each high-order decoupled complex filter; the input of the cascade high-order decoupled complex filter is an alpha-beta voltage component, and the wide-frequency oscillation component including a fundamental component and a plurality of resonance components is detected through the cascade high-order decoupled complex filter; the input of each intermediate high-order decoupled complex filter is the fundamental component or the resonance component output by the high-order decoupled complex filter at the previous stage and a voltage error signal; and the high-order decoupled complex filter is formed by cascading a plurality of first-order decoupled complex filters. The application can eliminate the influence of unknown frequency on the detection of the fundamental component, accurately detect the fundamental component, and simultaneously realize the detection of a plurality of resonance components and their resonance frequencies.

The application discloses a clock data recovery circuit and a clock data recovery method. The clock data recovery circuit comprises a time delay loop, a frequency locking loop and a deserializer. The time delay loop is used for delaying input data according to the phase of a clock signal to realize phase alignment. The frequency locking loop is connected with the time delay loop and is used for adjusting the frequency of the clock signal according to the delayed input data, so that the frequency of the clock signal is consistent with the frequency of the input data. The deserializer is connected with the time delay loop and the frequency locking loop respectively and is used for deserializing the input data according to the clock signal. According to the scheme provided in the embodiment, the phase integral factor can be avoided in the whole circuit system, an absolutely stable system with only a single pole can be obtained, and the circuit structure can be simplified.

The invention relates to a frequency offset compensation method, a frequency offset compensation device, a chip and a chip module. The method comprises the following steps: acquiring a satellite signal, performing frequency discrimination on the satellite signal through a frequency-locked loop to obtain a frequency discrimination result, determining an updated locking state of the frequency-locked loop according to the frequency discrimination result and a frequency discrimination threshold value, and controlling the locking state of the frequency-locked loop based on the updated locking state. By adopting the method, the GNSS positioning precision can be improved.

The invention belongs to the technical field of integrated circuit design, and discloses a high-noise suppression frequency-locked loop circuit based on closed-loop power supply tuning and a control method. A current comparator in the frequency-locked loop circuit is used for generating an error current signal; the loop filter is used for generating a control voltage based on the error current signal; the low dropout linear regulator receives the control voltage and takes the output voltage as the power supply voltage and the frequency tuning voltage of the voltage-controlled oscillator at the same time; the voltage-controlled oscillator performs frequency tuning through the change of the output voltage to generate an output clock signal; and the frequency divider is used for carrying out frequency division on the output clock signal, generating a feedback clock signal and transmitting the feedback clock signal to the current comparator to be compared with the reference current so as to form a closed-loop control path. The output voltage of the low dropout linear regulator is multiplexed as the tuning voltage of the voltage-controlled oscillator and is introduced into the frequency-locked loop feedback loop, so that an independent, clean and voltage-adjustable power supply domain is provided, and the frequency stability and the phase purity are improved.

The invention discloses a low-orbit satellite QPSK (Quadrature Phase Shift Keying) signal demodulation method based on data caching, and relates to the technical field of satellite navigation. According to the invention, after down-conversion and AD sampling are carried out on radio-frequency signals, the radio-frequency signals are filtered by a digital filter, then down-sampling is carried out, and then the radio-frequency signals are captured and written into a ping-pong RAM (Random Access Memory) in an FPGA (Field Programmable Gate Array) for caching for data post-processing. Data in the RAM cache is read through a system clock and played back to a plurality of tracking channels in sequence, down-conversion and dispreading of intermediate frequency signals are completed in the tracking channels, and frequency deviation of local carriers and received signals is rapidly reduced through a frequency-locked loop (FLL) by means of preamble data; and meanwhile, pseudo code phases are kept synchronous. And demodulation is carried out by adopting a differential demodulation method when telegraph text data is carried out. On one hand, the coherent integration time in the signal capturing stage is prolonged, so that the capturing sensitivity and the frequency estimation precision are improved; on the other hand, the frequency-locked loop is used for tracking by using the preamble data, so that the loop is fast and stable, and the message data demodulation speed is increased.

The invention relates to the technical field of control circuits, and discloses a low-jitter two-stage LC-ring hybrid architecture phase-locked loop suitable for multi-channel SerDes, which comprises a frequency locking loop which comprises a time-to-digital converter, a digital control oscillator and a frequency control module, the output end of the digital control oscillator is connected to the first control end of the digital control oscillator through the time-to-digital converter and the frequency control module in sequence, and the digital control oscillator is used for achieving rapid coarse tuning of the frequency. According to the invention, a two-stage control architecture with separated frequency locking and phase locking is adopted, an LC-ring mixed DCO structure is combined, the ring oscillator is utilized to quickly converge the frequency in a frequency capture stage, and the LC oscillator is switched to provide a low-phase noise clock in a phase locking stage, so that the frequency of the low-phase noise clock is reduced. The contradiction between the locking speed and the output jitter of the traditional phase-locked loop in the high-speed SerDes application is effectively solved, and the clock generation efficiency and quality are remarkably improved.

The application provides a signal synchronization method, device, equipment and storage medium, comprising: processing the obtained wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result; determining a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result; processing the first feedback gain to obtain a second carrier frequency offset estimation value, and generating a second phase-locked loop compensation result according to the second carrier frequency offset estimation value; determining a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result; determining a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain; demodulating and decoding the first code loop compensation result and the first frequency-locked loop carrier compensation result to obtain the electric text information; for eliminating most frequency dynamics while realizing high-precision phase tracking, and effectively isolating noise through a gain adaptive mechanism, significantly improving the locking speed and tracking stability.

The invention discloses a piston displacement detection method for a free piston Stirling power generation system, and the method comprises the steps: 1, constructing a second-order sliding-mode observer based on the power generation principle of a linear motor, and carrying out the observation of a counter electromotive force signal of the power generation system; 2, a third-order generalized integrator with a frequency-locked loop is adopted to suppress a direct-current component, filtering integration is carried out on the back electromotive force signal, and the filtered back electromotive force signal and an orthogonal signal of the filtered back electromotive force signal are output; 3, according to the relation between the piston displacement amplitude and the back electromotive force amplitude and the relation between the piston speed phase and the back electromotive force, the real-time displacement amplitude and speed phase information of the piston are calculated from the filtered back electromotive force signal and the orthogonal signal of the back electromotive force signal through a phase-locked loop; and 4, inputting the real-time displacement amplitude and the speed phase information of the piston into a control system of the power generation system to realize control operation of the power generation system. By means of the method, the real-time displacement amplitude and speed phase information of the piston can be accurately calculated, and efficient and stable control over the system is achieved.

The invention discloses a loop tracking system based on a satellite high-variable-speed motion scene, and the system comprises a matched filtering module, an EPL module, a DLL module, an FLL module, and a PLL module. After receiving data passes through a frequency offset compensation module, the matched filtering module is used for filtering noise; the EPL module calculates correlation values of advance, instant and delay of data after matched filtering, the DLL module compares the three correlation values to adjust a bit synchronization point, the FLL module and the PLL module calculate phase deviation in a mutual cascade mode, and the receiver adjusts a tracking strategy of a carrier ring in real time according to the current situation. According to the system, matched filtering, code loop tracking, a phase-locked loop and a frequency-locked loop are combined to realize loop tracking.