68 results about "Frequency-locked loop" patented technology

The invention discloses a wide-frequency three-phase phase-locked loop method, which relates to the technical field of three-phase phase-locked loops and comprises an alternating-current signal acquisition and coordinate transformation unit, a double-reduced-order generalized integrator, a frequency-locked loop frequency estimation unit, a double-second-order generalized integrator, a parallel delay signal cancellation filtering module and a phase-locked loop phase estimation unit. A three-phase power grid voltage signal is input into the alternating current signal acquisition and coordinate conversion unit to obtain a two-phase voltage under a static coordinate system; the double-reduced-order generalized integrator and frequency-locked loop frequency estimation unit outputs a three-phase power grid frequency estimation value and carries out feedforward; and the bisecond-order generalized integrator outputs a three-phase power grid positive sequence component, inputs the three-phase power grid positive sequence component into the parallel delay signal cancellation filtering module to filter out a higher harmonic component, and then inputs the three-phase power grid positive sequence component into the phase-locked loop phase estimation unit to output a three-phase power grid phase estimation value. The method can effectively solve the problem that a traditional phase-locked loop is difficult to lock the phase quickly and accurately when the ship microgrid frequency fluctuates in a large range, and improves the phase-locking precision and dynamic performance.

The invention discloses an electric energy metering method and device based on harmonic self-adaptive observation and zero point tracking type SOGI-FLL. The electric energy metering method comprises the following steps: step 1, carrying out ADC sampling on voltage and current signals of a power grid; 2, performing frequency rapid estimation on the voltage signal based on a zero point tracking frequency-locked loop, and obtaining a fundamental wave angular frequency of a power grid in real time; step 3, constructing adaptive observers of voltage and current by using the fundamental wave angular frequency, and estimating parameters of fundamental waves, harmonic waves and direct current components in voltage and current signals in real time through an adaptive law based on Lyapunov stability; 4, according to the parameter estimation value, the amplitude and phase of the voltage and current are calculated; and step 5, calculating active power and reactive power of each harmonic based on the voltage and current amplitudes and phases obtained in the step 4, and summing to obtain total active power and total reactive power so as to realize metering of active electric energy and reactive electric energy. According to the invention, rapid and accurate metering of fundamental wave and harmonic wave electric energy under complex working conditions is realized.

The invention discloses a frequency-locked loop of a self-adaptive delay signal elimination filter, which comprises a first filter, a second filter, a Park transformation module, a low-pass filter, an amplitude normalization module, an inverse Park transformation module, a frequency estimation module and a low-pass filter, and is characterized in that the first filter is used for eliminating higher harmonics, the second filter is used for eliminating low-order single harmonics, and the amplitude normalization module is used for normalizing the amplitude of the inverse Park transformation module. A signal passing through the filter is converted into a direct current component under a dq coordinate system through the Park conversion module, high-frequency clutter is filtered out through the low-pass filter, then the signal enters the amplitude normalization module, the signal amplitude is standardized to be 1, the signal is recovered into an alternating current signal through the reverse Park conversion module, the alternating current signal is input into the frequency estimation module, and the frequency estimation module estimates the frequency of the signal. And finally, a stable power grid frequency estimation value is obtained after processing by a low-pass filter. The invention aims to eliminate rounding errors and introduce a novel prefilter with relatively small time delay, so that the dynamic and steady-state performance of the first-order frequency-locked loop is improved.

The invention relates to a satellite navigation signal weak signal tracking loop switching method. The method comprises the following steps: designing a loop filter of a double-frequency phase-locked loop, a loop filter of a double-frequency frequency-locked loop and a loop filter of a pilot component single-frequency frequency-locked loop based on a Kalman filtering algorithm; constructing observed quantity and state quantity of a Kalman filter based on phase discrimination, frequency discrimination and code discrimination results of the B2a signal and the B1I signal; the state quantity output by the loop filter is fed back to a local carrier generator and a composite spreading code generator for error correction; in the filtering process, the adopted loop filter is switched according to the carrier-to-noise ratio, the phase locking detection index and the frequency locking detection index of the two signals, the corresponding loop filter is adaptively selected to complete parameter estimation, loop locking is further carried out, and signal tracking and positioning are achieved.

The invention relates to the technical field of power systems, in particular to a frequency-locked loop control method and system based on a double-second-order generalized integrator. According to the method, a traditional phase-locked loop is replaced by a frequency-locked loop to provide center frequency for the bisecond-order generalized integrator, and high-precision and high-response-speed real-time tracking of power grid frequency is achieved. And based on a DSOGI-FLL structure, parallel processing is carried out on the axis signal and the axis signal after Clark transformation, an orthogonal signal is generated, a positive sequence component and a negative sequence component are decoupled, and frequency doubling fluctuation under the asymmetric working condition of the power grid is eliminated. A phase angle of a positive sequence component is locked by combining a single synchronous coordinate system phase-locked loop, a positive sequence dq-axis component and a negative sequence dq-axis component are output through dq conversion, and a power grid synchronizing signal is rapidly obtained when voltage drops, frequency abrupt changes and three-phase faults occur. According to the method, the dynamic response speed and the detection precision can be remarkably improved, additional parameter compensation calculation is avoided, the universality of the method is enhanced, and a high-reliability synchronization reference is provided for fault ride-through of the power electronic converter.

The application discloses a frequency divider-free phase-locked loop and a reference double-delay frequency locking method thereof. The sub-sampling phase-locked loop architecture receives an output of an oscillator and feeds back the output to a reference double-delay frequency locking loop. The output end of a reference double-delay generator in the reference double-delay frequency locking loop is electrically connected with the input end of a sample-and-hold circuit, and the output end of the sample-and-hold circuit is electrically connected with the input end of an automatic phase error state detector. The sample-and-hold circuit simultaneously receives an oscillator output feedback signal of the sub-sampling phase-locked loop architecture. The output end of the automatic phase error state detector is electrically connected with the input end of an adaptive output frequency corrector, and the output end of the adaptive output frequency corrector is electrically connected with the sub-sampling phase-locked loop architecture. Unequal double-reference clock delays are introduced, the sample-and-hold circuit is combined to realize the detection of the output frequency, a new frequency locking loop working at a reference frequency is used to replace a traditional frequency locking loop, and the problem of high power consumption caused by a high-frequency frequency divider is solved.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a first fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code. A second fast-propagation path is configured to propagate a second code to the digitally controlled oscillator.

The invention relates to a decision-guided frequency compensation type carrier tracking method and system, and belongs to the field of satellite navigation. According to the method, aiming at the tracking lock losing problem caused by overlarge capture frequency deviation and navigation signal bit hopping in a capture-to-tracking link of a traditional frequency-locked loop, after receiving initial frequency deviation and code phase for delay alignment, down-conversion and coherent integration are carried out on intermediate frequency data based on the initial frequency deviation to obtain two groups of values; a frequency discriminator is used for calculating a first frequency difference, reverse frequency compensation is carried out on the first frequency difference to obtain a second frequency difference, frequency offset is synthesized to form two frequency assumptions, subsequent signals are processed in parallel, and correct frequency offset is output by comparing absolute values of coherent integration results, so that the frequency tracking range is effectively expanded, and the bit hopping interference resistance is enhanced. And the stability and the reliability of the navigation receiver in a high dynamic environment are improved.

A Signal-Agnostic Apparatus, System, and Method for Doppler Correction. In one embodiment, for the correction of significant Doppler shifts such as those present in signal transmissions involving satellites in low-earth orbit. The frequency locked loop apparatus and system for correcting Doppler frequency offset comprising an amplitude normalizer, a positive, a negative frequency band edge filter having a plurality of negative band edge coefficients, a positive or negative frequency content filter output for calculating a raw Doppler frequency offset, a leaky integrator, a zero-crossing counter, a plurality of locking filters, a plurality of tracking filters, an array, and a numerically controlled oscillator.

A system for frequency regulation in a AC power supply system is disclosed, wherein the system comprises an uninterruptible power supply being electrically connected to the AC power supply system and comprising a phase-locked loop and / or a frequency-locked loop for monitoring the frequency of an AC input voltage received from the AC power supply system, wherein the phase-locked loop and / or the frequency-locked loop is / are designed to be operated with an operation frequency being higher than a nominal grid frequency and being selected to detect a deviation of the monitored frequency from the nominal grid frequency within a predefined time span after a frequency drop-off of the monitored frequency occurred, wherein a control signal (19) is generated based on the detected deviation of the monitored frequency from the nominal grid frequency, and wherein the generated control signal is used to regulate the power flow between the uninterruptible power supply.

The invention discloses a fault-tolerant sensorless control method for a dual three-phase synchronous reluctance motor, and the method carries out the filtering of an observation flux linkage after an open-circuit fault based on a second-order generalized integrator with a frequency-locked loop, and achieves the purpose of improving the position-less control performance of the dual three-phase synchronous reluctance motor after the open-circuit fault. According to the invention, the hybrid flux linkage observer based on SOGI-FLL is adopted to carry out adaptive compensation on harmonic distortion under a single-phase open-circuit fault condition, so that the precision of flux linkage observation and rotor position estimation is improved. Compared with a traditional position-free control method, the three-time flux linkage harmonic caused by an open-circuit fault can be effectively inhibited, and the position observation precision and stability are remarkably improved. Meanwhile, high-precision position estimation can still be kept under the low-speed and zero-speed working conditions, the position-free stable operation speed range of the dual three-phase synchronous reluctance motor is expanded, and the method is suitable for high-reliability position-sensorless control application under various operation conditions such as the healthy working condition and the single-phase open-circuit fault.

The invention relates to a wireless circuit with optical frequency detection. An electronic device is provided with a wireless circuit. The wireless circuitry includes an optical mixer, a first laser and a second laser coupled to the optical mixer through a first optical path and a second optical path, a first optical resonator along the first optical path, a second optical resonator along the second optical path, and a third optical resonator along the second optical path. A phase-locked loop coupling the optical mixer to the first optical resonator; and a frequency-locked loop coupling an optical mixer to the second optical resonator. The first optical resonator and the second optical resonator may have optical resonant combs with different comb pitches, and the first laser and the second laser may be injection-locked. Once injection-locked, a control circuit may estimate the frequency of the optical signals output by the first laser and the second laser based on the beat frequency signal output by the optical mixer and based on the comb pitch of the first optical resonator and the second optical resonator. The wireless circuitry may perform or adjust wireless communications based on the estimated frequency.

This application relates to methods and apparatus for delay locked loops (DLLs). A DLL circuit includes a variable delay line, a phase detector and a delay controller. The DLL circuit is operable in a DLL mode in which a reference clock signal is input to the variable delay line and the delay controller controls a delay setting to achieve phase lock between the reference signal and an output signal. The DLL circuit is also operable in a frequency-locked-loop (FLL) mode, in which part of variable delay line is configured as a controlled oscillator to provide an oscillator signal, a frequency monitor determines a frequency relationship between the reference clock signal and the oscillator signal and the delay controller controls the delay setting to achieve frequency lock. The DLL circuit may configured to operate in the frequency-locked-loop mode on start-up and then transition to the DLL mode.

This invention provides a grid synchronization frequency-locked loop based on a dual generalized integrator filter (GIMF), belonging to the technical field of grid voltage and frequency signal detection and extraction. Addressing the shortcomings of conventional frequency-locked loops' poor frequency-locking performance under non-ideal grid conditions, this invention proposes a grid synchronization frequency-locked loop based on a dual GIMF. To enhance the frequency-locked loop's anti-disturbance performance, this invention designs a generalized integrator filter capable of filtering out the fundamental negative-sequence component of the grid, and thereby constructs and designs a frequency-locked loop based on the dual GIMF with DC offset cancellation function. Two frequency-locked loops based on the dual GIMF are connected in parallel to form a parallel dual GIMF frequency-locked loop. This designed frequency-locked loop is then incorporated into a three-phase grid-connected phase-locked loop (PLL), achieving the goal of accurately acquiring the grid voltage frequency and phase under non-ideal grid conditions. This invention is mainly used in grid-connected synchronization processes under non-ideal grid conditions.

The invention discloses a fault ride-through method and system for a follow-up network type converter based on linear active disturbance rejection control, and the method comprises the steps: obtaining the actual angular frequency of a power grid and the phase angle of the actual voltage of the power grid, and obtaining the amplitude of the estimated voltage of the power grid and the estimated angular frequency of the power grid through a frequency-locked loop based on an oscillator; adopting an optimal discrete wavelet transform method based on a decision tree, and utilizing the amplitude of the power grid estimation voltage and the power grid estimation angular frequency to judge whether the power grid has a fault; when it is judged that the power grid breaks down, the current difference value between the normal operation current amplitude of the power grid and the fault current amplitude is obtained, and when the current difference value is larger than a current threshold value, the converter is switched from a grid construction type to a grid following type; when it is judged that the power grid breaks down, broadband disturbance of the detected actual voltage of the power grid is compensated, the voltage difference value between the compensated actual voltage amplitude of the power grid and the reference voltage amplitude is obtained, when the voltage difference value is within the voltage range, the converter is switched from a grid following type to a grid constructing type, and dynamic tracking compensation is conducted on fault signals; and the fault ride-through capability is good.

The invention discloses a spread spectrum signal tracking method and system, and belongs to the field of signal processing. According to the invention, the spread spectrum digital signal is generated by performing oversampling on the acquired spread spectrum modulation signal. In-phase and quadrature components are generated by performing mixing, de-spreading and coherent integration on the digital signal, and frequency and phase error information is calculated based on the components at continuous moments for correcting local carriers. The corrected local carrier is then utilized to mix the signal to a baseband, and a target fractional delay is determined by applying an adjustable fractional delay and searching for an instant correlation energy peak to obtain code phase error information. After the code phase error information is utilized to correct the local pseudo code, the corrected local carrier and local pseudo code are utilized to initialize a narrow-bandwidth frequency-locked loop, a phase-locked loop and a delay-locked loop so as to start accurate tracking, and high-precision stable locking of spread spectrum signals can be realized in a short time.

The application discloses a satellite signal lock loss relocation method, system, device and storage medium, the method comprises the following steps: taking the carrier NCO value and code NCO value before lock loss as the center, a two-dimensional search range is constructed; searching in the two-dimensional search range, calculating the non-coherent accumulation value of each grid point, and finding the maximum non-coherent accumulation value; according to the size of the maximum non-coherent accumulation value, judging the peak interval to which the maximum non-coherent accumulation value belongs; when the maximum non-coherent accumulation value belongs to the first peak interval, a traditional frequency-locked loop reentry locking mode is adopted; when the maximum non-coherent accumulation value belongs to the second peak interval, a high-sensitivity reentry locking mode is adopted. The application improves the lock loss relocation sensitivity under weak signals, effectively guarantees the availability of the receiver under weak signals, and solves the problem of lock loss relocation under weak signals.

The invention discloses a Brillouin filter pumping laser frequency automatic tuning device, and belongs to the technical field of information transmission and processing. The frequency-locked loop comprises a pump laser, a Brillouin filter, a coupler, a combiner, a photoelectric converter, a filtering detection module, a frequency discriminator, a loop filter, a frequency-locked monitoring module and the like, and the frequency-locked loop is used for maintaining the frequency difference between the pump laser frequency and the Brillouin filter output working signal laser frequency to be Brillouin frequency shift. Therefore, the center frequency of the Brillouin filter automatically tracks the center frequency of the signal needing to be filtered, and the drift of the frequency of the pump laser and the change of the laser frequency of the input working signal along with time are eliminated. The device integrates the advantages of a microwave technology and a photon technology, can be used for filtering various continuous single-frequency and modulated laser signals, has the remarkable advantages of low cost, small size and low power consumption, and is an important improvement on the prior art.

The present invention constitutes a frequency synchronization loop of an oscillation circuit without using an amplifier for comparing voltages.　This oscillation circuit comprises: an oscillator; and a phase comparison unit that constitutes a feedback loop for the oscillator on the basis of the result of comparing phases obtained by converting the oscillation frequency of the oscillator. The phase comparison unit may include a first sub-oscillator that converts a reference voltage into a phase, and a second sub-oscillator that converts a control voltage obtained by converting the oscillation frequency of the oscillator into a phase. The phase comparison unit may include: a phase frequency detector (PFD) connected to subsequent stages of the first sub-oscillator and the second sub-oscillator; a charge pump circuit connected to a subsequent stage of the PFD; and a loop filter connected to a subsequent stage of the charge pump circuit.

The invention discloses a carrier tracking method, system, equipment and medium for a second-order frequency-locked loop assisted third-order phase-locked loop, and the method comprises the steps: receiving an in-phase integral value and a quadrature integral value outputted by a correlator, and carrying out the second-order frequency-locked loop tracking and the third-order phase-locked loop tracking based on the in-phase integral value and the quadrature integral value, the control quantity of the frequency-locked loop and the phase-locked loop is obtained; estimating a carrier-to-noise ratio and a carrier wave attitude of the received signal corresponding to the in-phase integral value and the orthogonal integral value in real time, and determining a first gain coefficient and a second gain coefficient according to the carrier-to-noise ratio and the carrier wave attitude; and generating a final control quantity of the carrier numerical control oscillator based on the control quantities of the frequency-locked loop and the phase-locked loop, the first gain coefficient and the second gain coefficient. By introducing a real-time sensing and dynamic gain control mechanism based on the carrier-to-noise ratio and the carrier wave fluctuation attitude, weighted fusion of contribution of the frequency-locked loop and the phase-locked loop is realized, and the robustness, the precision and the adaptive capacity of the carrier tracking loop under all working conditions can be improved.

The application provides a virtual synchronous generator control method and system, and belongs to the technical field of virtual synchronous generator control. The value of the grid frequency observed by a low-bandwidth frequency-locked loop, a phase-locked loop or a high-bandwidth frequency-locked loop or phase-locked loop after low-pass filtering is used as a feedforward value of the frequency of the virtual synchronous generator. When the grid frequency observed by the low-bandwidth frequency-locked loop or phase-locked loop is used as the feedforward value, the poles of the equivalent closed-loop transfer function of the frequency-locked loop or phase-locked loop and the zeros of the active-frequency transfer function of the virtual synchronous generator are cancelled. When the value of the grid frequency obtained by using the high-bandwidth frequency-locked loop or phase-locked loop and after low-pass filtering is used as the feedforward value, the poles of the low-pass filter transfer function and the zeros of the active-frequency transfer function of the virtual synchronous generator are cancelled. The application can eliminate the steady-state error of the active power regulation of the virtual synchronous generator, enhance the effect of suppressing the grid frequency change in the low-frequency band, and improve the effect of the virtual synchronous generator on the inertia support of the grid.

This application discloses a method and system for tracking spread spectrum signals, belonging to the field of signal processing. This application generates a spread spectrum digital signal by oversampling the acquired spread spectrum modulated signal. In-phase and quadrature components are generated by mixing, despreading, and coherent integration of this digital signal. Frequency and phase error information are calculated based on the components at continuous time intervals to correct the local carrier. The corrected local carrier is then used to mix the signal to baseband. An adjustable fractional delay is applied, and the instantaneous correlation energy peak is searched to determine the target fractional delay, thereby obtaining code phase error information. After correcting the local pseudocode using this code phase error information, the corrected local carrier and local pseudocode are used to initialize a narrow-bandwidth frequency-locked loop, phase-locked loop, and delay-locked loop, thus initiating precise tracking. This enables high-precision and stable locking of the spread spectrum signal in a short time.

Voltage-Frequency domain switching circuits that include multiple stages each configured to receive a throttle code, each of the stages providing a fast-propagation path for the throttle code to a digitally controlled oscillator, and a frequency locked loop configured to (a) generate a code to the digitally controlled oscillator over a slow path, and (2) disable the fast path to the digitally controlled oscillator upon the code satisfying a match with the throttle code.

The coherent phase sensitive OTDR partial discharge detection system solves the problem that residual frequency interference destroys a coherent mechanism of an existing phi-OTDR system, and belongs to the technical field of solid insulation equipment detection. A laser module outputs high-power and narrow-linewidth optical pulses to be injected into a sensing optical fiber through an optical circulator, backscattered Rayleigh signals enter a polarization controller through the optical circulator and are injected into a first coupler after the polarization angle is adjusted through the polarization controller, the first coupler outputs two paths, one path passes through a time-delay optical fiber, and the other path passes through a time-delay optical fiber; and a frequency shift signal is applied to the other path through the first acousto-optic modulator and is converged in the second coupler, an alternating current component output by the second coupler is detected by the photoelectric detector, and the signal detected by the photoelectric detector is processed to complete demodulation. According to the invention, a local electric oscillator and a complex frequency locking loop required in traditional demodulation are omitted, and residual frequency interference caused by instability of beat frequency signals is also eliminated.

The invention discloses a complex power grid frequency-locked loop method and system based on a steady-state Kalman filter, and the method comprises the steps: constructing a harmonic decoupling network, a steady-state linear Kalman filter based on a dual-second-order generalized integrator, and a frequency-locked loop module with a self-adaptive function, collecting the voltage of a three-phase power grid, and carrying out the calculation of the three-phase power grid. The three-phase power grid voltage is sequentially input into the harmonic decoupling network, the steady-state linear Kalman filter based on the bisecond-order generalized integrator and the frequency-locked loop module with the self-adaptive function, and the estimated voltage angular frequency is output, so that the accuracy and the stability of the frequency-locked loop are improved, and more effective power grid voltage synchronization is realized.

This invention discloses a segmented LPDSLIM primary field orientation method and apparatus, belonging to the field of motor control technology. The method includes: calculating the primary total flux linkage based on the primary voltage and current, and designing a third-order bandpass filter to effectively remove the DC and ramp components in the flux linkage, while significantly reducing harmonic levels. This greatly improves the estimation accuracy of the primary total flux linkage, laying the foundation for high-precision primary field orientation control. Furthermore, to obtain the key frequency parameters for third-order bandpass filter design, this invention directly calculates the frequency value by analyzing the phase angle of the primary total flux linkage, eliminating the need for the cumbersome frequency-locked loop structure found in traditional control systems and greatly simplifying the control system structure.

Certain aspects of the present disclosure provide a relatively compact frequency- locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

A hardware apparatus includes a frequency locked loop (FLL) including a phase loop filter and a phase locked loop (PLL), such as an all-digital PLL (ADPLL), including a frequency loop filter. When the apparatus operates a controller, the controller provides a first control signal to the FLL and a second control signal to the PLL. The apparatus can also include a digitally controlled oscillator (DCO) and a portion of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a frequency divider receive input from the DCO. The controller forms a first loop with the first filter, the TDC, and the frequency divider, and the controller forms a second loop with the second filter, the TDC, and the frequency divider.

A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.

A universal serial bus device for coupling to a universal serial bus host includes a transceiver to receive a data signal having a first frequency from the universal serial bus host, wherein the data signal includes a plurality of specific packets having a periodic characteristic; a packet detector coupled to the transceiver to receive the data signal via the transceiver to generate a reference signal based on the periodic characteristic of the plurality of specific packets; and a frequency locked loop circuit coupled to the transceiver and the packet detector to generate a clock signal having a second frequency based on the reference signal; wherein the first frequency is substantially equal to the second frequency. In other words, the second frequency is adjusted to be close to the first frequency, and the frequency difference between the first frequency and the second frequency is less than 500 ppm.