Time clock and data recovery circuit and integrated chip having the circuit

A technology for recovering circuits and data, applied in the field of data transmission, can solve the problems of large volume and high cost of quartz crystal clock circuits, and achieve the effects of simple circuit structure, low cost and easy implementation.

Inactive Publication Date: 2009-03-25
ANALOGIX CHINA SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] The present invention aims to provide a clock and data recovery circuit and an integrated chip with

Method used

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  • Time clock and data recovery circuit and integrated chip having the circuit
  • Time clock and data recovery circuit and integrated chip having the circuit
  • Time clock and data recovery circuit and integrated chip having the circuit

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Embodiment Construction

[0028] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0029] figure 2 A clock and data recovery circuit according to an embodiment of the present invention is shown, including a data channel 10, a FLL (Frequency Locked Loop, frequency locked loop) 20 and a phase adjustment loop 30, wherein the frequency locked loop is generated using a training signal The clock signal locked to the desired frequency; the phase adjustment loop uses the training signal to adjust the clock signal locked to the desired frequency to the desired phase; the data channel uses the clock signal locked to the desired frequency and adjusted to the desired phase to transmit the recovered data synchronously.

[0030] In this circuit, the training signal is directly used to establish the clock signal, so there is no need to transmit the clock signal during the data transmission process, and it is not necessary to use...

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Abstract

The invention provides a clock and data recovery circuit and an integrated chip provided with the circuit. The clock and data recovery circuit comprises a data channel, a frequency locking loop and a phasing loop, wherein the frequency locking loop utilizes a training signal to generate a clock signal which is locked on an expected frequency; the phasing loop utilizes the training signal to adjust the clock signal which is locked on the expected frequency to an expected phase; and the data channel utilizes recovery data of synchronous transmission of the clock signal which is locked on the expected frequency, and the clock signal which is adjusted on the expected phase. The invention has the advantages of simple structure, low cost, and easy realization.

Description

technical field [0001] The invention relates to the field of data transmission, in particular to a clock and data recovery circuit and an integrated chip with the circuit. Background technique [0002] DisplayPort (Display Port) is a digital video interface standard promoted by the Video Electronics Standards Association (VESA). It was set in May 2006, and the current version 1.1 is set on April 2, 2007. The interface stipulates certification-free, license-free, and a new digital audio / video interface under development, with the purpose of replacing the existing computer screen or home theater interface. [0003] DisplayPort supports 10.8Gbit / s bandwidth, and can support 2560×1600 high-resolution displays with only a single transmission line; realize 8B / 10B data transmission; support 6, 8, 10, 12 and 16-bit color depth; support cables The guaranteed length of the complete bandwidth is 3 meters; the guaranteed length of the effective transmission bandwidth of 1080p is 15 met...

Claims

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Application Information

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IPC IPC(8): H03L7/18G09G5/12
Inventor 李奇
Owner ANALOGIX CHINA SEMICON
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