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211results about How to "Minimize disturbance" patented technology

Bandwidth control in a mostly-digital pll/fll

InactiveUS20090108891A1Minimize disturbanceFaster frequency switching timePulse automatic controlLoop filterLoop bandwidth
Methods and apparatus for controlling a controlled oscillator using a phase-locked loop (PLL) or frequency-locked loop (FLL) having a digital loop filter with programmable filter parameters. An exemplary PLL (or FLL) includes a digital loop filter having one or more of the programmable filter parameters, which are changed by increments during operation in order to minimize disturbances (e.g., settling transients) as the loop bandwidth of the PLL is varied from a narrow loop bandwidth to a wide loop bandwidth, or vice versa. By changing the loop filter parameters in increments the loop bandwidth can be varied with substantially no perturbation. The end result is a much faster frequency switching time, improved settling dynamics, and predictable and stable loop operating performance. According to another aspect of the invention, one or more of the programmable filter parameters are changed in order to oppose a change in tuning sensitivity of the controlled oscillator (e.g., in order to maintain a constant loop bandwidth). By holding the loop bandwidth constant, switching time is maintained substantially constant under all conditions. This allows design and production margins to be reduced in a frequency agile system, and also relaxes the tuning sensitivity linearity requirements of the controlled oscillator.
Owner:PANASONIC CORP
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