16 results about "Binary search algorithm" patented technology

The invention provides a cellular-free mMIMO (multiple input multiple output) system computing power resource allocation and beam forming optimization method and a cellular-free mMIMO system computing power resource allocation and beam forming optimization system, and belongs to the technical field of wireless communication. The method specifically comprises the following steps of: respectively establishing a double-queue model based on a first-in first-out criterion at a central processing unit (CPU) and an access point (APs), taking a dequeue rate at the CPU as an enqueue rate at the AP, constructing a data volume relationship in a queue of a current frame and a previous frame, and analyzing system downlink end-to-end time delay based on an M / D / 1 queuing model. In a first layer queue, a binary search algorithm is provided to design computing power resource allocation at a CPU, and in a second layer queue, a path tracking algorithm is provided to optimize a beam forming vector at an AP. According to the method, the instantaneous channel state information is utilized, the worst user time delay is minimized under an alternating iteration algorithm framework, the calculation complexity is reduced, and meanwhile an effective solution is provided for ultra-low time delay communication.

This invention relates to the field of multi-processor multi-task joint scheduling technology, specifically disclosing a typed task joint scheduling system and method based on a heterogeneous multi-core architecture. It introduces a joint scheduling mechanism to divide and sort tasks according to task size and priority. Based on this, for the time-limited characteristics of real-time tasks, an inertial weight coefficient particle swarm optimization method is used to iteratively update the load balancing strategy, minimizing the maximum response time of real-time tasks while meeting their schedulability requirements. Simultaneously, for the low-priority characteristics of non-real-time tasks, the problem-solving is simplified using a Lagrange-based convex optimization approach, and an energy-constrained binary search algorithm is employed to effectively reduce the average response time of non-real-time tasks, achieving optimal load distribution for the system.

The invention relates to the technical field of avionics networks, and discloses a TSN redundant frame filtering method and system based on an IEEE802.1 CB protocol, and the method comprises the steps: receiving a data frame through an MAC layer of an end system, and extracting a destination MAC address and a source MAC address of the data frame; constructing an address two-tuple by using the destination MAC address and the source MAC address, and performing matching query in a pre-configured flow table by adopting a binary search algorithm to obtain a flow identifier corresponding to the address two-tuple; searching data stream state information bound with the stream identifier, wherein the data stream state information comprises a currently received maximum frame sequence number and historical window information for recording a historical frame receiving state; comparing the serial number of the data frame with the maximum frame serial number; according to the comparison result and the historical window information, corresponding data frame receiving or filtering operation is executed, and the problems that the flow identification query efficiency is low, and the out-of-order redundant frame processing logic is not accurate are solved.

The invention relates to the technical field of power system risk assessment, in particular to a power system cascading failure event sampling method, system and device and a storage medium. An initial fault event set is constructed by acquiring power system parameters, a dynamic probability correction model is constructed based on a current system state, and a load state influence factor, a new energy fluctuation influence factor and a topological correlation influence factor are introduced to correct a candidate event probability in real time. And converting the corrected dynamic probability into a roulette selection weight, optimizing the sampling efficiency by adopting a binary search algorithm, and outputting a complete fault sequence through iterative evolution until a termination condition is met. The technical problems of insufficient coverage of high-risk events, large deviation between static probability setting and an actual fault propagation path, low calculation efficiency and the like in a traditional sampling method are solved, the dynamic evolution law of cascading faults can be accurately reflected, the authenticity and reliability of a risk assessment result are improved, and important technical support is provided for safe operation of a power system.

This invention provides a microservice optimization method for industrial edge networks based on dynamic orchestration and migration expansion, comprising: abstracting the industrial edge network into an intelligent industrial network model composed of heterogeneous edge nodes and links; modeling industrial application requests as request chains composed of multiple microservices with data dependencies; calculating microservice instance deployment schemes and request routing schemes; statistically analyzing time-varying request flows; and utilizing a method based on... m / m / c This invention utilizes a multivariate performance analysis model of queue networks and a binary search algorithm to analyze and statistically determine the minimum number of cores that satisfy latency constraints. It then dynamically scales and adjusts the core resources of deployed microservice instances. Based on the preliminary dynamic scaling and adjustment results and migration costs, it solves a mixed-integer nonlinear programming migration decision problem to optimize the optimal collaborative deployment and request routing of microservice instances among edge nodes. This invention improves the service continuity and overall energy efficiency of industrial edge network systems.

The invention relates to the technical field of mobile communication network optimization, in particular to a base station position intelligent prediction method and device based on an improved DBSCAN algorithm, and the method comprises the steps: carrying out the rasterization of collected original data and stock base station data, obtaining an effective Enodeb list, carrying out the classification according to an operator and a network type, and obtaining a plurality of effective Enodeb sub-lists; positioning a raster data index of each Enodeb by using a binary search algorithm, extracting latitude and longitude coordinates of all grids under the same Enodeb, and constructing a clustering data list; performing clustering analysis on the raster data in each Enodeb to generate a predicted base station position data table; wherein during clustering analysis, clustering parameters are dynamically adjusted based on the number of cell identifiers under each Enodeb; and quantitatively predicting the matching degree of the base station and the actual base station, screening out the optimal parameter of the improved DBSCAN algorithm, and predicting the position of the base station based on the optimal parameter. Therefore, different base station density scenes are adapted, and the base station position prediction precision and efficiency are improved.

The application provides a method and system for improving the diversity of bit-level autoregressive image generation, and relates to the technical fields of artificial intelligence and computer vision, and has the characteristics that in the sampling process of a bit-level autoregressive image generation model, for each generation scale k, the original prediction logits of all token bits at the scale are obtained; based on the original prediction logits, an adaptive temperature coefficient τk is dynamically solved by a binary search algorithm, so that after the logits are scaled by the τk and normalized by softmax, the difference between the actual average maximum bit probability of the current scale k and the preset target average maximum bit probability Sk is less than the preset tolerance; an adaptive temperature coefficient τk is dynamically determined by binary search, so that after the softmax normalization is applied to the τk. The application has the advantages that the generation diversity is improved by adaptively smoothing the early prediction distribution, and the visual quality is maintained by means of energy-based path search; the method mainly operates in the early stage with low computational overhead, and the inference delay is only slightly increased, and the core design can be extended to similar autoregressive generation models.

The application discloses a nonvolatile reconfigurable compact all-optical logic gate based on a phase change material Sb2Se3 and belongs to the technical field of photonic information devices; the all-optical logic gate structure is designed on an insulating substrate silicon wafer and comprises a first input waveguide A, an intermediate control waveguide C, a second input waveguide B, an intermediate design region and an output waveguide Y. The all-optical logic gate device has an ultra-small footprint of 2.4mu m x 2.4mu m, realizes the reconfigurable characteristic through the nonvolatility of the fused phase change material, realizes four all-optical logic gates of NOT, OR, AND and XOR on the insulating substrate silicon wafer through a direct binary search algorithm (DBS), and simulation results show that the designed device has good logic contrast; the reconfigurable ultra-compact logic gate will become a potential advantage of nanophotonic integrated circuit application.

According to at least one embodiment, a multi-angle multi-time-point method authenticates 2D objects with high confidence by sampling the object through space and time while being capable of automatically authenticating and inputting object information. Some embodiments further enhance authentication confidence by utilizing unique characteristics of hologram and / or personal photo. While this method possesses artificial intelligence comparable to human's in term of authenticating and extracting information from 2D objects, it's also highly efficient and can achieve real-time performance (e.g., processing 5 frames per second) on ordinary personal computers. Structural information is first extracted from a 2D image to reduce processing time for subsequent steps as more operations on the 2D images are avoided. By employing similar divide-and-conquer strategy according to a binary search algorithm for 1D data array, a Visual Binary Edge Search Algorithm is applied to a 2D image application.

The invention relates to the technical field of high-speed network communication and testing, in particular to an FPGA message flow scheduling method and system based on a low-difference sequence, and the method comprises the steps: mapping the expected sending frame rate proportion of each message flow to an unsigned integer space, and distributing a continuous numerical interval; constructing a configuration tuple consisting of an interval right boundary and a flow identifier, generating sequence values uniformly distributed in an integer space by utilizing a low-difference sequence generator realized in the FPGA, performing interval matching with the configuration tuple through a binary search algorithm by taking the sequence values as an index, determining a message flow identifier to be sent currently, and sending the message flow identifier to the FPGA. And generating a specific message based on the identifier and sending the specific message. On the premise of not depending on an external high-speed memory, high-uniformity and low-delay dynamic proportional scheduling is carried out on multiple message flows, and meanwhile, the limitation of an external storage bandwidth bottleneck on the high-speed network test performance is eliminated.

The invention relates to clock synchronization, in particular to a low-complexity clock offset synchronization method for quantum key distribution, which comprises the following steps: Alice and Bob agree in advance to determine the maximum level of maximum recoverable offset and interleaving degree; the Alice sends a starting signal to the Bob through the data channel; alice generates a synchronization mode and sends the synchronization mode to Bob through a quantum channel; after Bob receives the starting signal, single photon events are collected, and clock skew is recovered by adopting a binary search algorithm; according to the technical scheme provided by the invention, the defects of high calculation complexity, high resource consumption and need of a large amount of information interaction in the prior art can be effectively overcome.

This invention discloses a file organization and indexing method for UAV flight data. The method comprises the following steps: S1: Write the received flight data into a data file and generate an index file record and an event log file; S2: Read and cache the index file, select a playback file, and enter playback mode; S3: Read the first data record and calculate the time interval for the next data record; S4: Use binary search based on the index file to locate the time; S5: Set the data file read position according to the result of the binary search and perform local parsing; S6: Parse the event log file and locate the time using event parameters; S7: Locate the data position using the index file based on the timestamp. This method employs a dual-file structure of data file and index file, and uses a binary search algorithm for time location, thus eliminating the need for sequential scanning from the file header. It can determine the position near the target time within logarithmic time complexity, significantly reducing I / O and parsing overhead, and is suitable for long-duration flight recordings.

This invention discloses an adaptive MLP pruning method for large-scale vision Transformers, addressing the practical deployment requirements of real-time visual perception, low power consumption, low latency, and high throughput in scenarios such as robots, drones, and mobile terminals. It solves the technical problems of existing large-scale vision Transformers, including redundant parameters, high computational and memory overhead, slow inference speed, and difficulty in edge deployment. The core method first accurately evaluates the importance of hidden neurons in the MLP based on Taylor expansion combined with the information entropy criterion. Then, it adaptively prunes and sorts the neurons according to the redundancy of different MLP modules using a binary search algorithm. Combined with knowledge distillation, it restores the performance of the pruned model, ultimately achieving a reduction of approximately 40% in parameters and computational load, and increasing the inference speed to about 1.5 times the original. This method not only demonstrates near-consistent performance with the original model in multiple benchmark tests such as zero-shot image classification, retrieval, and kNN evaluation, but also slightly surpasses it in some scenarios. Furthermore, it has the advantages of not relying on the original model's loss function and additional modules, and being compatible with word reduction methods. Ultimately, this invention provides a lightweight, high-performance, and easily adaptable practical solution for various application scenarios in the field of computer vision that require efficient model inference, and powerfully promotes the low-cost engineering deployment and commercialization of large-vision Transformer models.

The invention discloses a single-particle soft error simulation method, a single-particle soft error simulation system and single-particle soft error simulation equipment, belongs to the technical field of integrated circuits, and is used for solving the problems of low fault injection simulation efficiency and poor accuracy of a single-particle soft error simulation method in the prior art. Comprising the steps of receiving system design parameters of a to-be-tested system; on the basis of the parameters, compiling design codes through a simulation tool, executing segmented storage operation, and establishing a plurality of simulation state snapshots; calculating the sampling weight according to the relative proportion of the overturning cross section of the time sequence unit, carrying out the random sampling of the position and time dimensions, and generating an overturning sample for fault injection; based on a plurality of simulation state snapshots, starting simulation from the initialized snapshot, injecting a flipping sample according to a predetermined sequence, integrating an error detection mechanism, and when an output error is detected, gradually reducing the range in a flipping injection sequence by adopting a binary search algorithm, and determining a flipping event causing the error; and calculating the whole single-particle soft error section of the chip and generating a sensitive unit list.

This invention discloses a method, apparatus, device, medium, and product for optimizing computing power node scheduling. The method includes quantifying the allocable computing power of each node in a computing power cluster; obtaining a set of nodes that meet the computing power threshold requirements based on the quantified cluster computing power matrix and a preset computing power threshold matrix; and using a greedy binary search algorithm based on the node set and target business requirements to find a subset of nodes corresponding to each type of computing power that meets the target business requirements, thereby optimizing computing power node scheduling. This method can quickly filter the remaining computing power matrix using the computing power quantification method and calculate each node that meets each type of computing power requirement based on the greedy binary search algorithm, reducing the computational cost and algorithm complexity of computing power node scheduling.