33 results about "Binary search algorithm" patented technology

The invention provides a cellular-free mMIMO (multiple input multiple output) system computing power resource allocation and beam forming optimization method and a cellular-free mMIMO system computing power resource allocation and beam forming optimization system, and belongs to the technical field of wireless communication. The method specifically comprises the following steps of: respectively establishing a double-queue model based on a first-in first-out criterion at a central processing unit (CPU) and an access point (APs), taking a dequeue rate at the CPU as an enqueue rate at the AP, constructing a data volume relationship in a queue of a current frame and a previous frame, and analyzing system downlink end-to-end time delay based on an M / D / 1 queuing model. In a first layer queue, a binary search algorithm is provided to design computing power resource allocation at a CPU, and in a second layer queue, a path tracking algorithm is provided to optimize a beam forming vector at an AP. According to the method, the instantaneous channel state information is utilized, the worst user time delay is minimized under an alternating iteration algorithm framework, the calculation complexity is reduced, and meanwhile an effective solution is provided for ultra-low time delay communication.

This invention relates to the field of multi-processor multi-task joint scheduling technology, specifically disclosing a typed task joint scheduling system and method based on a heterogeneous multi-core architecture. It introduces a joint scheduling mechanism to divide and sort tasks according to task size and priority. Based on this, for the time-limited characteristics of real-time tasks, an inertial weight coefficient particle swarm optimization method is used to iteratively update the load balancing strategy, minimizing the maximum response time of real-time tasks while meeting their schedulability requirements. Simultaneously, for the low-priority characteristics of non-real-time tasks, the problem-solving is simplified using a Lagrange-based convex optimization approach, and an energy-constrained binary search algorithm is employed to effectively reduce the average response time of non-real-time tasks, achieving optimal load distribution for the system.

The invention provides an industrial edge network micro-service optimization method based on dynamic arrangement and migration expansion, which comprises the following steps: abstracting an industrial edge network into an intelligent industrial network model formed by heterogeneous edge nodes and links, modeling an industrial application request into a request chain formed by combining a plurality of micro-services with a data dependency relationship in sequence, calculating a micro-service instance deployment scheme and a request routing scheme; counting a time-varying request stream, analyzing the minimum core number meeting the time delay constraint in a statistical result by using a multivariate performance analysis model based on an m / m / c queue network and a binary search algorithm, and carrying out dynamic expansion and contraction adjustment on core resources of deployed micro-service instances; and solving a mixed integer nonlinear programming migration decision problem according to the initial dynamic scaling adjustment result and the migration cost so as to optimize the optimal collaborative deployment and request routing of the micro-service instance between the edge nodes. According to the invention, the service continuity and the overall energy efficiency of the industrial edge network system are improved.

The invention provides a tunnel monitoring emergency system and method based on an interpolation algorithm and a binary search algorithm, and the system comprises an Internet of Things data collection module, a data processing module, an alarm module, a plan strategy module and an event handling module which are connected in sequence, and all the modules work cooperatively. According to the method, abnormal or missing data is intelligently complemented through an interpolation algorithm, alarm parameters are dynamically configured for event monitoring equipment in advance based on a tunnel environment, an operation time period and the equipment type of the event monitoring equipment, and a nearest camera and upstream and downstream cameras thereof are rapidly positioned through pile number sorting and a binary search algorithm. In combination with an intelligent analysis and plan linkage mechanism, automatic screen projection of infield pictures and outfield traffic situation awareness are realized, and evacuation decision making is assisted; and finally, by generating and grading emergencies, related units are linked to perform timely processing, so that all-directional perception and intelligent management of the tunnel operation state are realized, and the tunnel safety management level and the emergency response capability are improved.

The invention relates to the technical field of avionics networks, and discloses a TSN redundant frame filtering method and system based on an IEEE802.1 CB protocol, and the method comprises the steps: receiving a data frame through an MAC layer of an end system, and extracting a destination MAC address and a source MAC address of the data frame; constructing an address two-tuple by using the destination MAC address and the source MAC address, and performing matching query in a pre-configured flow table by adopting a binary search algorithm to obtain a flow identifier corresponding to the address two-tuple; searching data stream state information bound with the stream identifier, wherein the data stream state information comprises a currently received maximum frame sequence number and historical window information for recording a historical frame receiving state; comparing the serial number of the data frame with the maximum frame serial number; according to the comparison result and the historical window information, corresponding data frame receiving or filtering operation is executed, and the problems that the flow identification query efficiency is low, and the out-of-order redundant frame processing logic is not accurate are solved.

The invention relates to the technical field of power system risk assessment, in particular to a power system cascading failure event sampling method, system and device and a storage medium. An initial fault event set is constructed by acquiring power system parameters, a dynamic probability correction model is constructed based on a current system state, and a load state influence factor, a new energy fluctuation influence factor and a topological correlation influence factor are introduced to correct a candidate event probability in real time. And converting the corrected dynamic probability into a roulette selection weight, optimizing the sampling efficiency by adopting a binary search algorithm, and outputting a complete fault sequence through iterative evolution until a termination condition is met. The technical problems of insufficient coverage of high-risk events, large deviation between static probability setting and an actual fault propagation path, low calculation efficiency and the like in a traditional sampling method are solved, the dynamic evolution law of cascading faults can be accurately reflected, the authenticity and reliability of a risk assessment result are improved, and important technical support is provided for safe operation of a power system.

The invention provides a satellite-ground network OFDM (Orthogonal Frequency Division Multiplexing) anti-interception waveform design method based on security coding, and relates to the technical field of communication. The method comprises the following steps: determining a first signal to interference plus noise ratio at a legal receiver and a second signal to interference plus noise ratio at an eavesdropper according to a source symbol transmitted on each subcarrier, a security coding matrix in a time domain, a power allocation scheme, a frequency domain channel matrix and a frequency domain noise vector; according to the first signal to interference plus noise ratio and the second signal to interference plus noise ratio, a target optimization problem is established, and the target optimization problem takes the signal quality of the legal receiver end as an optimization target; and solving the target optimization problem by using a binary search algorithm and a neural network to obtain a final security coding matrix and a final power allocation scheme, and designing a satellite-ground network OFDM anti-interception waveform based on security coding by using the final security coding matrix and the final power allocation scheme. Therefore, the secrecy performance of the satellite-to-ground link is relatively high, and the computing power resource occupation of the satellite-to-ground fusion network is reduced.

According to the anti-noise bi-clustering method and system for the gene expression data, the thought that a seed list is obtained through a longest common subsequence searching method is utilized, the longest approximate common subsequence is searched through an element exchange permitting strategy, interference of noise in a data set on sequence matching can be effectively reduced, and the anti-noise bi-clustering method and system for the gene expression data are provided. The algorithm can still accurately identify the similarity in the gene expression mode in a complex noise environment, so that the accuracy of a bi-clustering result is improved; the binary search algorithm is adopted to determine the insertion interval, the method can fully consider the characteristics of noise data, and compared with a traditional expansion mode, the method can more reasonably process the influence of noise and avoid error expansion caused by the noise, so that the bi-clustering structure is more accurately constructed.

The application relates to a high-speed SAR-ADC circuit with a redundancy algorithm, comprising: a DAC array unit, which samples an input signal and completes a binary search algorithm by utilizing inter-capacitor charge redistribution; a dynamic comparator, which is used for comparing the size of a differential analog input signal, outputting a binary digital signal and completing quantization; a clock logic unit, which is used for providing a sample-and-hold clock, a reset clock and a synchronization clock, and the clock output end of the clock logic unit is connected with the DAC array unit, the comparator, the bit latch and the combination logic unit; and a combination logic unit, which controls signal switching of a capacitor array according to the output result of the comparator, completes conversion of redundant bits and buffers and outputs a quantization code. The application uses an asynchronous SAR-ADC architecture with redundancy, and since the asynchronous SAR-ADC is adopted, the time of each cycle can be fully utilized, the speed is improved, the redundancy method is used, the fault tolerance of conversion is improved, and the precision is improved.

This invention provides a microservice optimization method for industrial edge networks based on dynamic orchestration and migration expansion, comprising: abstracting the industrial edge network into an intelligent industrial network model composed of heterogeneous edge nodes and links; modeling industrial application requests as request chains composed of multiple microservices with data dependencies; calculating microservice instance deployment schemes and request routing schemes; statistically analyzing time-varying request flows; and utilizing a method based on... m / m / c This invention utilizes a multivariate performance analysis model of queue networks and a binary search algorithm to analyze and statistically determine the minimum number of cores that satisfy latency constraints. It then dynamically scales and adjusts the core resources of deployed microservice instances. Based on the preliminary dynamic scaling and adjustment results and migration costs, it solves a mixed-integer nonlinear programming migration decision problem to optimize the optimal collaborative deployment and request routing of microservice instances among edge nodes. This invention improves the service continuity and overall energy efficiency of industrial edge network systems.

The invention relates to the technical field of mobile communication network optimization, in particular to a base station position intelligent prediction method and device based on an improved DBSCAN algorithm, and the method comprises the steps: carrying out the rasterization of collected original data and stock base station data, obtaining an effective Enodeb list, carrying out the classification according to an operator and a network type, and obtaining a plurality of effective Enodeb sub-lists; positioning a raster data index of each Enodeb by using a binary search algorithm, extracting latitude and longitude coordinates of all grids under the same Enodeb, and constructing a clustering data list; performing clustering analysis on the raster data in each Enodeb to generate a predicted base station position data table; wherein during clustering analysis, clustering parameters are dynamically adjusted based on the number of cell identifiers under each Enodeb; and quantitatively predicting the matching degree of the base station and the actual base station, screening out the optimal parameter of the improved DBSCAN algorithm, and predicting the position of the base station based on the optimal parameter. Therefore, different base station density scenes are adapted, and the base station position prediction precision and efficiency are improved.

The application provides a method and system for improving the diversity of bit-level autoregressive image generation, and relates to the technical fields of artificial intelligence and computer vision, and has the characteristics that in the sampling process of a bit-level autoregressive image generation model, for each generation scale k, the original prediction logits of all token bits at the scale are obtained; based on the original prediction logits, an adaptive temperature coefficient τk is dynamically solved by a binary search algorithm, so that after the logits are scaled by the τk and normalized by softmax, the difference between the actual average maximum bit probability of the current scale k and the preset target average maximum bit probability Sk is less than the preset tolerance; an adaptive temperature coefficient τk is dynamically determined by binary search, so that after the softmax normalization is applied to the τk. The application has the advantages that the generation diversity is improved by adaptively smoothing the early prediction distribution, and the visual quality is maintained by means of energy-based path search; the method mainly operates in the early stage with low computational overhead, and the inference delay is only slightly increased, and the core design can be extended to similar autoregressive generation models.

The present application provides a method, apparatus, device, storage medium and product for searching strings in memory. The method includes: obtaining a target memory-resident string to be searched; determining a currently satisfied string search condition; if it is determined that the currently satisfied string search condition is a linear search condition, then using a binary search algorithm to search whether the target memory-resident string exists in the stored resident strings in the memory; if it is determined that the currently satisfied string search condition is a combined search condition, then searching whether the target memory-resident string exists in the stored resident strings in the memory based on a hash table corresponding to the stored resident strings and a data structure corresponding to a hash value index in the hash table. Using a binary search algorithm or searching for a target memory-resident string based on a hash table and a data structure corresponding to a hash value index in the hash table can reduce the algorithm's time complexity, improve search efficiency, and control the memory occupied by the stored resident strings.

The application discloses a nonvolatile reconfigurable compact all-optical logic gate based on a phase change material Sb2Se3 and belongs to the technical field of photonic information devices; the all-optical logic gate structure is designed on an insulating substrate silicon wafer and comprises a first input waveguide A, an intermediate control waveguide C, a second input waveguide B, an intermediate design region and an output waveguide Y. The all-optical logic gate device has an ultra-small footprint of 2.4mu m x 2.4mu m, realizes the reconfigurable characteristic through the nonvolatility of the fused phase change material, realizes four all-optical logic gates of NOT, OR, AND and XOR on the insulating substrate silicon wafer through a direct binary search algorithm (DBS), and simulation results show that the designed device has good logic contrast; the reconfigurable ultra-compact logic gate will become a potential advantage of nanophotonic integrated circuit application.

The present invention belongs to the field of optical devices, and specifically relates to a power beam splitter based on phase change material, a design method, and an image recognizer. The power beam splitter comprises an input waveguide, a coupling region, and two output waveguides connected in sequence. The coupling region comprises a phase change material array region and an optimization region. The two output waveguides are respectively connected to the phase change material array region and the optimization region. The optimization region is divided into a plurality of units, each unit having two states, and the state of each unit is determined according to a direct binary search algorithm. The present invention significantly reduces device size, reduces loss and crosstalk, and achieves high-precision and wide power distribution.

The application discloses a code testing method and device, a storage medium and a program product, relates to the technical field of code testing, and comprises the following steps: determining the record range of a current to-be-tested submission record on a first record branch, obtaining a target record to be subjected to regression testing based on a dichotomy search algorithm, and constructing a test message based on the target record and a regression test case and sending the test message to a client; updating the current to-be-tested submission record according to a returned test result; when there are only two code submission records in the current to-be-tested submission record and any one is a record obtained after merging code submission records on a second record branch, taking the second record branch as a new first record branch, determining a new record range, and determining an error submission record until an error submission record is determined. The application does not need manual intervention, and can test the submission record subjected to the merging operation as a new to-be-tested submission record based on the dichotomy search algorithm, thereby effectively improving the positioning efficiency and accuracy of the error submission record.

The embodiment of the invention provides a Gantt chart display method, a computer readable storage medium and electronic equipment, relates to the technical field of aviation, and is used for optimizing an aviation task plan data display link and accelerating the processing speed during Gantt chart adjustment. The Gantt chart display method comprises the following steps: displaying a Gantt chart display interface; the Gantt chart display interface is used for displaying a Gantt chart of partial data in the aviation mission plan data; in response to a display data adjustment operation, determining to-be-displayed target data in the aviation mission plan data by using a binary search algorithm based on an operation intention of the display data adjustment operation; and displaying the target data through the Gantt chart display interface.

According to at least one embodiment, a multi-angle multi-time-point method authenticates 2D objects with high confidence by sampling the object through space and time while being capable of automatically authenticating and inputting object information. Some embodiments further enhance authentication confidence by utilizing unique characteristics of hologram and / or personal photo. While this method possesses artificial intelligence comparable to human's in term of authenticating and extracting information from 2D objects, it's also highly efficient and can achieve real-time performance (e.g., processing 5 frames per second) on ordinary personal computers. Structural information is first extracted from a 2D image to reduce processing time for subsequent steps as more operations on the 2D images are avoided. By employing similar divide-and-conquer strategy according to a binary search algorithm for 1D data array, a Visual Binary Edge Search Algorithm is applied to a 2D image application.

Disclosed are a media scanning task execution method and apparatus, and a device and a medium. The media scanning task execution method comprises: triggering a media scanning service on the basis of a connection operation of an external storage device, and traversing and scanning subdirectories in a target directory of the external storage device by using a binary search algorithm, so as to obtain a target subdirectory; acquiring first file information of each media file in the target subdirectory, performing screening on the first file information to obtain file information to be analyzed that does not match file information currently stored in a media database, and storing the file information to be analyzed in a first queue; acquiring the file information to be analyzed in the first queue, storing the file information to be analyzed in an analysis thread pool, such that the analysis thread pool analyzes the file information to be analyzed to obtain analyzed file information, then generating database operation objects from the analyzed file information by using a storage thread, and storing the database operation objects in a second queue, wherein the execution modes of the analysis thread pool and the storage thread are concurrent execution modes; sequentially storing, in an operation array, copies of the database operation objects in the second queue, processing the copies in the operation array in batches, so as to generate target identifiers corresponding to the copies, and then storing the target identifiers in a third queue; and updating the media file information in the media database on the basis of the target identifiers in the third queue, so as to complete a media scanning task.

The invention relates to the technical field of high-speed network communication and testing, in particular to an FPGA message flow scheduling method and system based on a low-difference sequence, and the method comprises the steps: mapping the expected sending frame rate proportion of each message flow to an unsigned integer space, and distributing a continuous numerical interval; constructing a configuration tuple consisting of an interval right boundary and a flow identifier, generating sequence values uniformly distributed in an integer space by utilizing a low-difference sequence generator realized in the FPGA, performing interval matching with the configuration tuple through a binary search algorithm by taking the sequence values as an index, determining a message flow identifier to be sent currently, and sending the message flow identifier to the FPGA. And generating a specific message based on the identifier and sending the specific message. On the premise of not depending on an external high-speed memory, high-uniformity and low-delay dynamic proportional scheduling is carried out on multiple message flows, and meanwhile, the limitation of an external storage bandwidth bottleneck on the high-speed network test performance is eliminated.

A system for efficient boot logging in embedded systems that records boot event logs and failure operation logs in flash storage and optimizing write operations for longevity. Defined regions in flash reserve space for data blocks organized into fixed sizes. Logs are appended by locating free blocks without erase operations. A state machine limits logging duplicate failure events. The system comprises a boot loader, flash memory, and logic to manipulate data regions. The method manages defined flash regions, locates free blocks, writes record headers and log payloads, and updates record states when logging repetitive failures. Binary search algorithms efficiently find last written blocks. Embodiments can be used for embedded systems that use boot loaders to initialize system hardware and load operating systems.

The invention relates to clock synchronization, in particular to a low-complexity clock offset synchronization method for quantum key distribution, which comprises the following steps: Alice and Bob agree in advance to determine the maximum level of maximum recoverable offset and interleaving degree; the Alice sends a starting signal to the Bob through the data channel; alice generates a synchronization mode and sends the synchronization mode to Bob through a quantum channel; after Bob receives the starting signal, single photon events are collected, and clock skew is recovered by adopting a binary search algorithm; according to the technical scheme provided by the invention, the defects of high calculation complexity, high resource consumption and need of a large amount of information interaction in the prior art can be effectively overcome.

This invention discloses a file organization and indexing method for UAV flight data. The method comprises the following steps: S1: Write the received flight data into a data file and generate an index file record and an event log file; S2: Read and cache the index file, select a playback file, and enter playback mode; S3: Read the first data record and calculate the time interval for the next data record; S4: Use binary search based on the index file to locate the time; S5: Set the data file read position according to the result of the binary search and perform local parsing; S6: Parse the event log file and locate the time using event parameters; S7: Locate the data position using the index file based on the timestamp. This method employs a dual-file structure of data file and index file, and uses a binary search algorithm for time location, thus eliminating the need for sequential scanning from the file header. It can determine the position near the target time within logarithmic time complexity, significantly reducing I / O and parsing overhead, and is suitable for long-duration flight recordings.

The invention provides a data query method and equipment, and belongs to the technical field of communication, and the method comprises the steps: inputting first data into a model selector, and determining a first learning index model selected by the model selector and matched with the first data; inputting the first data into the first learning index model, and obtaining a maximum prediction error range of the first data predicted by the first learning index model; and determining a target storage position of the first data in the maximum prediction error range through a binary search algorithm. According to the embodiment of the invention, the learning index model matched with the first data is selected through the model selector, the maximum prediction error range of the first data is predicted through the learning index model, and the actual storage position is found through the binary search algorithm, so that the query data can be accurately searched in the dynamic real-time change process of the data characteristics; and when query operation with high accuracy and strong robustness is carried out on mass data, the query time overhead is reduced.

The invention discloses a code testing method and device, a storage medium and a program product, and relates to the technical field of code testing, and the method comprises the steps: determining a record range of a current to-be-tested submission record on a first record branch, and obtaining a target record to be subjected to regression testing based on a binary search algorithm, constructing a test message based on the target record and the regression test case, and sending the test message to the client; and updating the current to-be-tested submission record according to the returned test result, when only two code submission records exist in the current to-be-tested submission record and any one is a record obtained by combining the code submission records on a second record branch, taking the second record branch as a new first record branch, determining a new record range, and sending the new record range to the current to-be-tested submission record. And the error submission record is determined. According to the method, manual intervention is not needed, the submission records subjected to merging operation can be used as new submission records to be tested to be tested based on the binary search algorithm, and the positioning efficiency and accuracy of wrong submission records are effectively improved.

The invention discloses a dynamic erasing balance method and a dynamic erasing balance system for an embedded Flash memory, which are used for realizing efficient and balanced use of Flash memory through virtual address mapping, a binary search algorithm and a CRC7 (Cyclic Redundancy Check 7) verification technology. The system comprises a storage management module, an initialization module, a write-in control module and an erasure management module, has the advantages of prolonging the service life of Flash, improving data reliability, optimizing storage performance and the like, and is particularly suitable for embedded application scenes needing to frequently update small data volume.

This application provides an end-to-end design method and apparatus for a broadband low-noise amplifier. The method includes: matching the topology of the broadband low-noise amplifier based on a lookup table; optimizing the first parameters of active components in the broadband low-noise amplifier based on the topology; matching the range of second parameters of passive components in the broadband low-noise amplifier based on the first parameters of the active components; optimizing the physical parameters of the transformer using an adaptive weighted binary search algorithm, with the range of second parameters of the passive components as a pre-layout reference value; and assembling the active and passive components by interconnecting and wiring according to the first parameters, second parameters, and physical parameters and based on layout rules, to obtain the broadband low-noise amplifier layout. The end-to-end design method and apparatus for broadband low-noise amplifiers provided in this application address the problems of low efficiency, narrow applicability, and susceptibility to local optima in existing design methods, significantly improving design efficiency and optimization quality, and achieving globally optimal performance.

This invention discloses an adaptive MLP pruning method for large-scale vision Transformers, addressing the practical deployment requirements of real-time visual perception, low power consumption, low latency, and high throughput in scenarios such as robots, drones, and mobile terminals. It solves the technical problems of existing large-scale vision Transformers, including redundant parameters, high computational and memory overhead, slow inference speed, and difficulty in edge deployment. The core method first accurately evaluates the importance of hidden neurons in the MLP based on Taylor expansion combined with the information entropy criterion. Then, it adaptively prunes and sorts the neurons according to the redundancy of different MLP modules using a binary search algorithm. Combined with knowledge distillation, it restores the performance of the pruned model, ultimately achieving a reduction of approximately 40% in parameters and computational load, and increasing the inference speed to about 1.5 times the original. This method not only demonstrates near-consistent performance with the original model in multiple benchmark tests such as zero-shot image classification, retrieval, and kNN evaluation, but also slightly surpasses it in some scenarios. Furthermore, it has the advantages of not relying on the original model's loss function and additional modules, and being compatible with word reduction methods. Ultimately, this invention provides a lightweight, high-performance, and easily adaptable practical solution for various application scenarios in the field of computer vision that require efficient model inference, and powerfully promotes the low-cost engineering deployment and commercialization of large-vision Transformer models.

The invention discloses a single-particle soft error simulation method, a single-particle soft error simulation system and single-particle soft error simulation equipment, belongs to the technical field of integrated circuits, and is used for solving the problems of low fault injection simulation efficiency and poor accuracy of a single-particle soft error simulation method in the prior art. Comprising the steps of receiving system design parameters of a to-be-tested system; on the basis of the parameters, compiling design codes through a simulation tool, executing segmented storage operation, and establishing a plurality of simulation state snapshots; calculating the sampling weight according to the relative proportion of the overturning cross section of the time sequence unit, carrying out the random sampling of the position and time dimensions, and generating an overturning sample for fault injection; based on a plurality of simulation state snapshots, starting simulation from the initialized snapshot, injecting a flipping sample according to a predetermined sequence, integrating an error detection mechanism, and when an output error is detected, gradually reducing the range in a flipping injection sequence by adopting a binary search algorithm, and determining a flipping event causing the error; and calculating the whole single-particle soft error section of the chip and generating a sensitive unit list.