4results about How to "Reduce design requirements" patented technology

The utility model relates to the technical field of mobile power supply, concretely relates to a mobile power supply. Mobile power supply includes the casing, control circuit board, charging wire and handle plug connector, control circuit board installs in the casing, and one end of charging wire is connected with control circuit board electricity, and charging wire leads out from the casing, and handle plug connector fixed mounting is installed on charging wire, and the handle plug connector is equipped with the plug -in groove, and the charging head of charging wire can be detachably inserted in the plug -in groove to form the handle structure. The casing does not need to set up the storage groove to store the fixed charging head to form the handle structure, avoids the high requirement of the casing design and mobile power supply internal component design layout, improves the problem of mobile power supply overall structure design difficulty. And the handle plug connector is as the independent part, does not influence each other with the casing or internal component of mobile power supply itself, and the design freedom is also bigger, and the design requirement is also lower.

A kind of dual-phase variable loop order increment high-resolution analog-digital converter circuit based on multi-bit quantization, containing analog loop filter (hereinafter referred to as ΔΣ loop) and downsampling digital filter, there is phase switching switch, the phase switching switch includes L-1 phase switching switch in loop filter and L-1 phase switching switch in downsampling digital filter.The present application uses the architecture of first order and high order IADC mixedly, signal weight is made uniform by distributing the period number of phase 1 larger in total clock cycle, while fast accumulation is obtained by high order accumulation in a small part of total clock cycle to effectively improve the accuracy of system.Guarantee the weight of part input signal uniform in a sampling conversion period, to improve the effectiveness of DWA to suppress multi-bit DAC nonlinearity.

This invention discloses a method for parallelizing and pipelining a nested multiplier, relating to the field of intelligent warehousing technology. Based on the nested multiplication concept, the multiplication operation is decomposed into a formula to obtain the squaring operation of the high-bit part and the difference of squares plus shift operation of the low-bit part. Based on the characteristic of 2ab in the multiplication formula, the intermediate values ​​required for high-bit calculation are obtained by querying a preset low-bit square value table through the low-bit results. For batch data, multiple sets of data are processed simultaneously through a parallel architecture. The overall calculation process is divided into multiple pipeline stages, and continuous calculation is achieved through stage cascading. The pipeline output results of each parallel computing unit are collected, verified, and integrated to output a complete set of multiplication results. This invention achieves breakthroughs in hardware resources, computational latency, and batch throughput through the collaborative design of nested recursive simplification, pipeline reuse, and parallel architecture, providing an efficient solution for high real-time and high-parallelism digital computing scenarios.

The application provides a display panel and a display device, and relates to the display field, and is used for preventing peep display performance. The display panel comprises a display area and a non-display area surrounding the display area, a substrate, a display layer located on one side of the substrate and comprising a pixel area and a non-pixel area, wherein the pixel area comprises a sub-pixel, an encapsulation layer located on the side, away from the substrate, of the display layer, a filter layer located on the side, away from the substrate, of the encapsulation layer and comprising a filter part and a light shielding part, wherein the filter part overlaps the pixel area in the direction perpendicular to the plane where the substrate is located, and the light shielding part overlaps the non-pixel area, at least one blocking layer located on the side, away from the substrate, of the filter layer, wherein the blocking layer has an opening, the opening overlaps the pixel area in the direction perpendicular to the plane where the substrate is located, and the blocking layer overlaps the non-pixel area, and a first planar layer located between the display layer and the blocking layer and covering the display area.