157 results about "Blocking oscillator" patented technology

Local oscillator circuitry for an antenna array is disclosed. The circuitry includes an array of rotary traveling wave oscillators which are arranged in a pattern over an area and coupled so as to make them coherent. This provides for a set of phase synchronous local oscillators distributed over a large area. The array also includes a plurality of phase shifters each of which is connected to one of the rotary oscillators to provide a phase shifted local oscillator for the array. The phase shifter optionally includes a cycle counter that is configured to count cycles of the rotary oscillator to which it is connected and control circuitry that is then operative to provide a shifted rotary oscillator output based on the count from the cycle counter. A system and method for operating a true-time delay phased array antenna system. The system includes a plurality of antenna element circuits for driving or receiving an rf signal from the elements of the array. Each element circuit has a transmit and a receive path and a local multiphase oscillator, such as a rotary traveling wave oscillator. Each path has an analog delay line for providing a true-time delay for the antenna element. Preferably, the analog delay line is a charge coupled device whose control nodes are connected to phases of the local multiphase oscillator to implement a delay that is an integer number local multiphase oscillator periods. A fractional delay is also included in the path by using a sample and hold circuit connected to a particular phase of the oscillator. By delaying each antenna element by a true time delay, broadband operation of the array is possible.

A passive harmonic switch mixer is shown that is immune to self mixing of the local oscillator greatly reducing leakage noise, pulling noise, and flicker noise when used in a direct conversion receiver or direct conversion transmitter circuit. The passive harmonic switch mixermixes an input signal received on an input port with an in-phase oscillator signal and a quadrature-phase oscillator signal and outputs an output signal on an output port. Because the quadrature-phase oscillator signal is the in-phase oscillator signal phase shifted by 90 °, the passive harmonic switch mixer operates with a local oscillator running at half the frequency of the carrier frequency of an RF signal. Additionally, because the passive harmonic switch mixer has no active components, the DC current passing through each switch device is reduced and the associated flicker noise of the mixer is also greatly reduced.

A method of measuring the transistor leakage current. In one embodiment, the method involves driving a ring oscillator with a dynamic node driver having a leakage test device biased to an off state to produce a test signal. The test signal is extracted and the frequency is measured. The leakage current is estimated from the measured frequency.

A direct conversion quadrature receiver and method are provided according to the invention. The receiver according to one embodiment includes a primary local oscillator (LO) that down-converts a received RF signal to a quadrature intermediate frequency (IF) signal. The receiver further includes a dithering controller responsive to the quadrature IF signal generated by the primary LO. The dithering controller communicates a feedback signal back to the primary LO. The feedback signal controls the primary LO in order to offset down-conversion of the RF signal by the quadrature IF signal. The dithering controller offsets the primary LO from a zero-IF signal in order to reduce a phase and gain error of the quadrature IF signal.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

A heterodyne communication system uses coherent data modulation that is resistant to phase noise. In particular, a pilot tone and reference clock signal are transmitted along with the modulated data to form the basis of an electrical demodulation local oscillator at the receiver. The pilot tone and / or reference clock signal carry phase noise which is correlated with the phase noise in the data signal. At the receiver, the local oscillator is generated from the pilot tone and reference clock signal in a manner so that the local oscillator also has phase noise which is correlated with the phase noise in the data signal. Thus, the two noise components can be used to cancel each other during demodulation of the data signal using the local oscillator.

A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L / N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q) fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

A state of a programmable mixer is set during a calibration phase to minimize local oscillator feedthrough. During a calibration phase, inputs to the programmable mixer are set to zero, or to a known state and the local oscillator is set to a calibration frequency. Then, one of a plurality of known calibration states of the programmable mixer is entered and the local oscillator feedthrough is measured. For each of a plurality of operating states an amplified output of the programmable mixer is measured. In one operation, the state of the programmable mixer in which the programmable mixer operates during a next operation phase is the state that produces minimal local oscillator feedthrough. In another operation, operation continues until a state is found that produces a local oscillation feedthrough that meets an operating criteria and that state is used during the next operation phase. After these operations are complete, programmable mixer calibration operations are completed until the next calibration phase commences.

A clock generator for providing a desired system clock signal in accordance with an embodiment of the present application includes a ring oscillator operable to provide an oscillator output signal having a first frequency, a divider operable to divide the oscillator output signal by a predetermined divisor and to output the divided signal as the desired system clock signal, a reference device operable to provide a reference signal with a known second frequency and a ratio device operable to provide a ratio value indicative of a relationship between the oscillator output signal and the reference signal, wherein the predetermined divisor of the divider is determined based on the ratio value such that the desired system clock signal has a desired frequency.

A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L / N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q)fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

A method of measuring the transistor leakage current. In one embodiment, the method involves driving a ring oscillator with a dynamic node driver having a leakage test device biased to an off state to produce a test signal. The test signal is extracted and the frequency is measured. The leakage current is estimated from the measured frequency.

A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. An input baseband signal is interpolated and upconverted in the digital domain to an IF. The LO operates at a frequency which is a n / m division of the target RF frequency fRF. The IF frequency is configured to ½ of the LO frequency. The upconverted IF signal is then converted to the analog domain via digital power amplifiers followed by voltage combiners. The output of the combiners is band pass filtered to extract the desired replica.

A local oscillator (LO) module comprises a local oscillator and a feedback circuit. The local oscillator, biased at a supply voltage, generates a local oscillator signal having a duty cycle. The feedback circuit makes an absolute adjustment of the duty cycle of the local oscillator signal in response to a difference between a first voltage signal, representing a voltage level of the local oscillator signal, and a second voltage signal, representing a voltage level of a portion of the supply voltage corresponding to a desired duty cycle for the local oscillator signal.

An oscillating signal of relatively precise frequency is generated by tuning an oscillator using an external stable oscillating source as a reference. Calibration logic is included to compare a signal from the local oscillator to the reference signal and vary the local signal to a desired frequency. In one embodiment, a binary search algorithm is used to tune the local oscillator. The local oscillating signal can be sent to one or more circuits including at least one sensor of a touch sensitive panel for detecting touch events.

An oscillating signal of relatively precise frequency is generated by tuning an oscillator using an external stable oscillating source as a reference. Calibration logic is included to compare a signal from the local oscillator to the reference signal and vary the local signal to a desired frequency. In one embodiment, a binary search algorithm is used to tune the local oscillator. The local oscillating signal can be sent to one or more circuits including at least one sensor of a touch sensitive panel for detecting touch events.

This invention relates to a local oscillator using a correction circuit for correcting I / Q mismatch through LO path and a receiver using the same. The local oscillator provides in-phase local oscillating signal and quadrature-phase signal to first and second mixers outputting input signal with mixing in-phase local oscillating signal and quadrature-phase local oscillating signal, respectively. The oscillator comprises a local oscillator having first and second delay cells and outputting said in-phase local oscillating signal and said quadrature-phase local oscillating signal; and a correction circuit for controlling phase matching characteristic between said in-phase local oscillating signal and said quadrature-phase local oscillating signal outputted from said local oscillator, said correction circuit setting bias current flowing in said first and second delay cells of said local oscillator as being different. In another embodiments, the phase matching characteristic is controlled by setting bias voltage applied to the first and second delay cells as being different, by setting width of active device included in the first and second delay dells as being different, or by setting impedance of passive device as being different.

A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T / 12 or zero based on the state of the controlled oscillator down-divided clock.

A circuitry for measuring a time interval with ring oscillator has a ring oscillator formed by a plurality of delay switching units, a counter and an encoder. Wherein, the ring oscillator generates a plurality of oscillating signals when receives a pulse signal used to turn on or turn off the ring oscillator. The counter can count the numbers of the oscillating signal during an active period of the pulse signal to generate a counting value. In addition, the encoder encodes the oscillation signals generated by a plurality of delay switching unit with a certain interval of delay time. Therefore, when the pulse signal is disabled to lead to turn off the ring oscillator, one can obtain the time interval of the pulse signal based on the encode data and the counting value.

A plurality of inverters are arranged serially to form a ring oscillator and coupled to receive a reference clock signal. The reference clock signal is used to switch the inverters on and off so that not all of the inverters are on at a same time. The ring oscillator circuit is used as a divider circuit to divide the frequency of the reference clock signal to produce a local oscillator signal at a second frequency.

A ring oscillator that uses active negative capacitance at one or more stages of the ring oscillator to adjust the frequency of oscillation. By using a negative capacitance generator, negative capacitance may be placed in shunt with each stage of the ring, thereby reducing the effective input capacitance. Tuning of the ring oscillation frequency is accomplished without changing the bias point of each stage. The ring oscillation frequency may be increased, rather than reduced as in current approaches.

A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.

Integrated multiple tuner architectures and associated methods are disclosed that utilize frequency isolated local oscillators (LO). These architectures utilize dividers and multipliers within the signal paths for the local oscillator mixing signals to reduce interference among the multiple local oscillators operating on a single integrated circuit. A multiple tuner direct-down-conversion (DDC) receiver and a multiple tuner intermediate frequency (IF) receiver are provided as example embodiments. And an example integrated multi-tuner satellite receiver is also described.

A method of accessing electronic memory is provided in electronic circuits where it is desired to lower power consumption and hence there is no active oscillator at the time when access to data within the electronic memory is required. The invention provides a method therefore for accessing the electronic memory from a controller, which generates its own clock signals from a data, communications bus electrically coupled to the controller. Advantageously the method allows for memory access to be continued in integrated circuits where a subset of circuits are powered down to reduce power consumption, and one of the subset of circuits is an oscillator.

A synchronous mirror delay (300) includes a ring oscillator that generates a plurality of tap clock signals (T1-T7) with one tap clock signal being designated an oscillator clock signal. In response to an input clock signal, a model delay line generates a model delayed clock signal having a model delay relative to the input clock signal. A coarse delay circuit generates a coarse delay count (316) responsive to the oscillator, input, and model delayed clock signals, and activates a coarse delay enable signal responsive to the delay count being equal to a reference count value. A fine delay circuit latches the tap clock signals and develops a fine delay from the latched signals, and activates a fine delay enable signal having the fine delay in response to the coarse delay enable signal. An output circuit generates a delayed clock signal responsive to the coarse and fine delay enable signals going active.