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664 results about "Electronic memory" patented technology

Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory

A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3~5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density. Key elements used in this process are: 1) Disposable side wall process to fabricate the ultra short channel and the side wall control gate with or without a step structure, and 2) Self-aligned definition of the control gate over the storage nitride and the bit line diffusion, which also runs in the same direction as the control gate. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.
Owner:HALO LSI INC

Method and apparatus for providing status information from a security and automation system to an emergency responder

An access portal is provided for establishing communication between an environmental management system used on a premises and an authorized responder equipped with an external access device. In some cases a remote host server is provided for obtaining information from the environmental management system, which in turn can transmit the information to the external access device. The access portal includes a first electronic memory segment configured to store access information associated with at least one authorized responder and a second electronic memory segment configured to store information pertaining to the premises and/or at least one occupant residing in the premises. The access portal also includes a processor for identifying a responder as an authorized responder by comparing identifying information received from the responder through the external access device with the access information stored in the first electronic memory segment. A wireless transceiver is provided for (i) receiving the identifying information and requests from the responder and, (ii) in response to a request, transmitting the premises information stored in the second electronic memory segment and status information obtained from at least one sensor in the environmental management system to an authorized responder.
Owner:GENERAL INSTR CORP
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