912 results about "Phase synchronization" patented technology

A frequency determination circuit generating a clock signal phase-locking with an external clock signal at a coarse precision and a fine adjust circuit generating an internal synchronizing signal phase-locking with the external clock signal at a fine precision are provided. The fine adjust circuit has a function of adjusting the phase of the frequency determination circuit when phase synchronization is to be carried out exceeding the adjust range thereof. The frequency determination circuit and the fine adjust circuit receive a clock power supply voltage. A clock reproduction circuit is provided which generates an internal clock signal phase-locking with an external clock signal or a reference clock signal stably even when the operating environment changes.

Local oscillator circuitry for an antenna array is disclosed. The circuitry includes an array of rotary traveling wave oscillators which are arranged in a pattern over an area and coupled so as to make them coherent. This provides for a set of phase synchronous local oscillators distributed over a large area. The array also includes a plurality of phase shifters each of which is connected to one of the rotary oscillators to provide a phase shifted local oscillator for the array. The phase shifter optionally includes a cycle counter that is configured to count cycles of the rotary oscillator to which it is connected and control circuitry that is then operative to provide a shifted rotary oscillator output based on the count from the cycle counter. A system and method for operating a true-time delay phased array antenna system. The system includes a plurality of antenna element circuits for driving or receiving an rf signal from the elements of the array. Each element circuit has a transmit and a receive path and a local multiphase oscillator, such as a rotary traveling wave oscillator. Each path has an analog delay line for providing a true-time delay for the antenna element. Preferably, the analog delay line is a charge coupled device whose control nodes are connected to phases of the local multiphase oscillator to implement a delay that is an integer number local multiphase oscillator periods. A fractional delay is also included in the path by using a sample and hold circuit connected to a particular phase of the oscillator. By delaying each antenna element by a true time delay, broadband operation of the array is possible.

A transmitter system including: a bidirectional signaling (BDS) network having first and second networks for carrying first and second carrier signals, and having a set of n phase synchronous location pairs (a_i, b_i),; and also including tunable transmitter circuits for driving an antenna array, each tunable transmitter circuit having an output line for carrying an output signal and first and second input lines electrically connected to the first and second networks of the BDS network at locations of a corresponding one of the set of phase synchronous location pairs, and including a multiplier having a first input electrically connected to the first input line of that tunable transmitter circuit; a phase setting circuit electrically connected to the multiplier for controlling the phase of the output signal of that tunable transmitter circuit; and an amplitude setting circuit for controlling the amplitude of the output signal of that tunable transmitter circuit.

Methods for generating a design for logic circuitry using rotary traveling wave oscillators (RTWOs) are described. A plurality of RTWOs are is arranged into an array of rows and columns. Adjacent elements in the array are interconnected so that the clocks in adjacent element are phase synchronous. Clocked devices are placed along the signal path of each array element and each is connected to one of the multiple phases provided by the RTWO element. The logic circuitry, described by a netlist, is divided into a number of partitions and each of these partitions is mapped to one of the array elements. The logic circuitry of the partition is then placed within or about the element of the array to which the partition is mapped and the circuitry in the partition is connected between the clocked devices in the element of the array, according to the net list.

A clock generator has a clock generating circuit, a phase difference detection circuit, and a control signal generating circuit. The clock generating circuit has a function for varying a clock phase in accordance with a control signal, the phase difference detection circuit compars the clock phase output from the clock generating circuit with a phase of a reference waveform, and detecting a phase difference therebetween, and the control signal generating circuit generates a control signal for controlling the clock phase of the clock generating circuit, based on phase difference information obtained from the phase difference detection circuit. The phase difference detection circuit has a plurality of phase detection units, at least one of the plurality of phase detection units carries out a direct phase detection in which a phase of the clock is directly compared with the phase of the reference waveform, and at least the other one of the plurality of phase detection units carries out an indirect phase detection using a phase-synchronized waveform generating circuit generating a waveform synchronized in phase with the reference waveform or an output of the clock generating circuit and a phase information extracting circuit extracting phase information from the phase-synchronized waveform.

An object of this invention is to provide a phase synchronizing circuit capable of automatically adjusting a VCO such that the VCO satisfies a predetermined frequency range even in a frequency range in which the VCO oscillates by a leak current generated if a low threshold process is applied. The phase synchronizing circuit is composed of a PLL consisting of a phase comparator, a charge pump, a loop filter, a VCO, and a divider, and a calibration circuit for automatically adjusting a frequency range of the VCO. Before a convergence operation is started, a switch is closed in response to a signal Rst of the calibration circuit such that an output of the loop filter is leveled to the ground and the PLL is set to be an open loop. A VCO output Fo is set at an upper limit frequency or a lower limit frequency in response to a Vcal signal, and its frequency is measured by comparing its period with a period of a reference signal Fr, and signals Hb, Lb used for adjusting the frequency of the VCO are updated. The signals Hb, Lb are updated until the VCO satisfies the predetermined frequency range, and subsequently their values are maintained. The switch opens in response to the signal Rst, and the PLL is changed over to a close loop to start phase synchronization.

An oversampling clock recovery method according to this invention generates non-uniform three-phase clock signals CLKa, CLKb, and CLKc having non-uniform intervals for one bit of an input data i and controls phases of the clock signals so that either phase of two edges of two-phase clock signals CLKb and CLKc having a relatively narrower interval of 57 ps synchronizes with a phase of a transition point of the input data i. By changing clock signals to be phase-locked in three delay locked loops (DLLs), a phase interval of 57 ps is formed.

A phase synchronization circuit includes a controlled oscillator configured to generate a first oscillation signal and a second oscillation signal that have a common frequency but different phase controlled by a combination of a first control signal and a second control signal, a digital phase frequency detector configured to detect a frequency difference and a first phase difference between a reference signal and the first oscillation signal to generate the first control signal, an analog phase detector configured to detect a second phase difference between the second oscillation signal and the reference signal to generate the second control signal, and a lock detection unit configured to detect a lock of the first oscillation signal with the reference signal in terms of frequency and phase, in order to set the analog phase detector in an active state.

Timing phase information is extracted from a power spectrum of a received signal whose amplitude is modulated per frame or sub-frame, and timing phase synchronization of the received signal is performed with the timing phase information. Also, a vector signal of the power spectrum is generated, the vector signal is multiplied by another vector signal to be rotated, a sign decision of the rotated vector signal is performed, a result of the sign decision is integrated to be outputted as the timing phase information, and a vector conversion is performed to the integrated value to be fed back as the other vector signal.

The invention relates to a multi-class motor imagery brain electrical signal classification method based on phase synchronization. According to the method, firstly, phase synchronization features of a training sample and a test sample are calculated respectively through a phase locking value; secondly, correlation coefficients of the training sample and the test sample are calculated and arrayed from large to small after an average value is removed and an absolute value is obtained; thirdly, brain electrical signals are roughly classified according to the arrayed correlation coefficients, and then disaggregated classification is conducted according to the brain electrical signals which are roughly classified, wherein the process is involved in a shared airspace mode feature extraction method and a linear discriminant analysis and classification method. The method comprises the steps of brain electrical signal collection, data pre-processing, filtering, calculation of the correlation coefficients of the phase synchronization features, feature extraction and classification and classification accuracy calculation. Classification results show that by the adoption of the brain electrical signal classification method based on phase synchronization, the classification results are good, the rough class where the test sample belongs can be efficiently and accurately determined through brain electrical signal rough classification based on phase synchronization, and the calculated amount is reduced.

The invention relates to a non coherent demodulation method, which belongs to the signal processing field, is used in Chirp spread spectrum technology demodulation, can reduce phase shift error, multipath time delay error and Doppler shift effect, and achieves better performance over multipath fading channels and IEEE802.15.4a S-V standard channels. The fundamental principle of the invention is: utilizing a Chirp signal as an impulse function in a proper fractional Fourier domain, i.e. fractional Fourier transformation achieves an excellent focusing ability to the Chirp signal sent by the CCS system. For the advantage of Chirp signal processing in fractional Fourier transformation, the fractional Fourier transformation can be used in CSS spread spectrum technology to demodulate Chirp signals with different modulation frequencies. The demodulation to CCS system is realized by implementing fractional Fourier transformation to the received base band data, and judging the code element by detecting the peak value of the focusing order. The method reduces the demand to frequency synchronization, needs no phase synchronization, and achieves better performance over multipath frequency selectively fading channels.

The invention discloses a general multi-channel data collection system. The general multi-channel data collection system comprises a collection card and a master control card. The collection card collects analog signals transmitted from a collection sensor, and the analog signals are collected and converted into digital signals. The master control card carries out denoising and filtering on data in the digital signals, so that real-time correction of the data is achieved, an upper computer is connected with the master control card, and configuration information is written from the master control card, so that control over the work of a whole system is achieved. An analog-digital conversion module of the collection card converts the analog signals into the digital signals, and a photoelectric isolation module of the collection card isolates the analog portion from the digital portion of the whole data collection system completely, so that the transmission of the analog signals is not interfered by noise of a digital circuit. The photoelectric isolation module is used for reducing the influence of the noise of the analog portion on the digital portion, a precision power module of the collection card reduces the influence of power supply noise, and a phase-locked loop of the collection card guarantees phase synchronization of clock signals among the collection cards.

The invention discloses a burst direct sequence spread spectrum system and a pseudo code synchronization method of a burst direct sequence spread spectrum waveform thereof. By adoption of the burst direct sequence spread spectrum system disclosed by the invention, the capturing, tracking and convergence times of a burst direct sequence spread spectrum signal can be greatly shortened, and the frequency offset estimation precision is relatively high. The burst direct sequence spread spectrum system disclosed by the invention is realized by the following technical scheme: in a signal modulation system, a specific segment of lead data is added in front of user data after scrambling and channel encoding are carried out on the user data for accomplishing signal capture and synchronization; and in a signal demodulation system, pseudo code phase capture and carrier frequency offset capture are carried out on a digital baseband signal to accomplish signal capture, coarse pseudo code phase synchronization and coarse frequency offset compensation with a coarse synchronizer, precise signal synchronization of a coarse synchronization signal is separately accomplished by pseudo code phase and carrier phase synchronization loops, identification information and a starting position of a user data segment are determined from a precise synchronization signal by a frame synchronizer, and the user data are restored by channel decoding and descrambling.

The invention discloses a delay-locked-loop-based remote microwave signal phase-stabilized optical fiber transmission device, which realizes the phase synchronization of a local microwave signal and a remote microwave signal by utilizing a delay-locked loop. The device realizes optoelectronic heterodyne mixing by utilizing the nonlinear effects of an optoelectronic modulator for phase detection, drives and controls a microwave delayer by feeding a phase difference signal back, performs phase change on the microwave signals, compensates microwave signal phase disturbance caused by the delay change of a transmission link, keeps a phase synchronism relationship between the local microwave signal and the remote microwave signal, solves the problem of phase asynchronism between the local microwave signal and the remote microwave signal, fulfills the aim of phase-stabilized transmission of the microwave signals, adopts noncoherent correction, and has the advantages of wide dynamic range, high stability and the like, besides a long phase-stabilized transmission distance.

Provided are a clock signal selecting apparatus and method that can guarantee the continuity of an output clock signal. The clock signal selecting apparatus and method can synchronize the phases of at least two clock signals by continuously controlling the phases of the clock signals. Accordingly, even when an active clock signal and a standby clock signal have different frequencies, it is possible to guarantee the continuity of the output clock signal regardless of whether the clock signals are switched from one to another. In addition, it is possible to guarantee the stability of the output clock signal.

A digital phase lock loop (PLL) for maintaining synchronization with the phase of a received data signal including a preamble and an information-containing data frame, by incrementing a state machine through an internal cyclic count, each cycle thereof including a center count tending to coincide with center regions of the successive pulses and an edge count tending to coincide with edges of the successive pulses. The PLL selects a current sample of the signal whenever the internal count reaches the predetermined center count value. The state machine internal count is updated in accordance with a cumulative phase error obtained by summing the phase errors detected over successive edges between each edge and the corresponding center count. The interval over which the cumulative phase error is computed depends upon the number of received edges during the preamble and depends upon elapsed time during the data frame.

This invention provides a system and method for synchronization of vision system inspection results produced by each of a plurality of processors that includes a first bank (that can be a “master” bank) containing a master vision system processor and at least one slave vision system processor. At least a second bank (that can be one of a plurality of “slave” banks) contains a master vision system processor and at least one slave vision system processor. Each vision system processor in each bank generates results from an image acquired and processed in a given inspection cycle. The inspection cycle can be based on an external trigger or other trigger signal, and it can enable some or all of the processors/banks to acquire and process images at a given time/cycle. In a given cycle. each of the multiple banks can be positioned to acquire an image of a respective region of a plurality of succeeding regions on a moving line. A synchronization process (a) generates a unique identifier and that passes a trigger signal with the unique identifier associated with the master processor in the first bank to each of the slave processor in the master bank and each of the master and slave processor and (b) receives consolidated results via the master processor of the second bank, having the unique identifier and consolidated results from the results from the first bank. The process then (c) consolidates the results for transmission to a destination if the results are complete and the unique identifier of each of the results is the same.

An wireless terminal includes a demodulating unit which comprises an FV (fading vector) estimating unit for receiving a CPICH spread/demodulated signal to output an FV signal with a reduced noise ratio; a phase synchronization unit for multiplying a PDSCH spread/demodulated signal with a complex conjugate of the FV signal to correct the phase offset of the PDSCH I and Q signals to send the resulting PDSCH I and Q signals to a multi-level QAM amplitude synchronization detection unit and to an amplitude demodulating unit; a first-quadrant transformation unit for collecting the second to fourth quadrant signals of the phase-synchronized PDSCH I and Q signals; and a threshold value detecting unit for calculating a multi-level QAM threshold value from the first quadrant signals and the FV signals to send the threshold signal to an amplitude demodulating unit. The amplitude demodulating unit effects amplitude demodulation to output multi-level QAM demodulated signals. The threshold value detecting unit previously assumes a plural number of probabilities as to which of the levels received data belongs to and, using a plural number of the data, raises the precision of the assumed data. The threshold value is estimated, using the frequencies and differences of the respective levels, from the assumed plural threshold values.

A demodulator is made compact, and with a simple circuit arrangement, and also having a better bit error rate characteristic. A timing phase synchronization detecting circuit 219 judges any one of the following two conditions based upon baseband phase data 202, i.e., an UNLOCK (timing phase asynchronous) condition, and a LOCK (timing phase synchronous) condition. Based upon the judgement result of the timing phase synchronization detecting circuit 219, in a timing recovering means 221, a frequency range of a PLL (phase synchronization loop) is variable, whereas the number of data entered within 1 symbol time is variable in a frequency synchronizing means 222 and a carrier recovering means 223. A data demodulating means 224 outputs demodulation data 206 in response to baseband phase data 202 and a recovery carrier signal 205.