383 results about "Pulse delay" patented technology

A digital transmit beamformer system with multiple beam transmit capability has a plurality of multi-channel transmitters, each channel with a source of sampled, complex-valued initial waveform information representative of the ultimate desired waveform to be applied to one or more corresponding transducer elements for each beam. Each multi-channel transmitter applies beamformation delays and apodization to each channel's respective initial waveform information digitally, digitally modulates the information by a carrier frequency, and interpolates the information to the DAC sample rate for conversion to an analog signal and application to the associated transducer element(s). The beamformer transmitters can be programmed per channel and per beam with carrier frequency, delay, apodization and calibration values. For pulsed wave operation, pulse waveform parameters can be specified to the beamformer transmitters on a per firing basis, without degrading the scan frame rate to non-useful diagnostic levels. Waveform parameters can be specified to the transmitters by an external central control system which is responsible for higher level flexibility, such as scan formats, focusing depths and fields of view. The transmit pulse delay specified per-channel to each transmitter is applied in at least two components: a focusing time delay component and a focusing phase component. The carrier frequency can be specified for each transmit beam, to any desired frequency within a substantially continuous predefined range of frequencies, and a beam-interleaved signal processing path permits operation in any of several predefined processing modes, which define different parameter sets in a trade-off among (1) the number of beams produced; (2) per-beam initial waveform sample interval; and (3) transmit frequency.

In a device for analog-to-digital converting an input signal, the input signal is applied to a plurality of delay units constituting a pulse delay circuit in order to change a delay time to be given by the delay units. The number of delay units through which a pulse signal has passed during one period of sampling clocks is numerically expressed. The A / D conversion device has a plurality of pulse position numerizing units that is used for A / D conversion. Sampling clocks of which the phases are different from one another are applied to the respective pulse position numerizing units. An adder summates numerical data items produced by the respective pulse position numerizing units so as to generate final numerical data representing a result of A / D conversion.

An A / D converter has a pulse delay circuit including a plurality of inverting circuits to each of which an analog voltage signal is inputted through a first pair of power supply lines. Each of the inverting circuits has a first logic gate. The A / D converter has a logic circuit having a second logic gate and a second pair of power supply lines, the logic circuit operating based on a power supply voltage. At least one of a first range of a level of the voltage signal and a second range of the power supply voltage is set to prevent a tunneling current from flowing at least one of between the first paired power supply lines and between the second paired power supply lines when at least one of first and second logic gates operates.

A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

In an A / D conversion device, each delay unit in a pulse delay circuit has inverters INV of m×n stages (m, n are positive integers), a clock generator has m-delay lines, and each delay line has inverters INV of i×n stages (i=1, 2, . . . , and m). Those delay lines DL1 to DLm output sampling clocks CK1 to CKm. Each of those inverters INV has a same characteristic. In the A / D conversion device, the delay time in each of the delay lines DL1 to DLm is adjusted by the number of the inverters INV. It is thereby possible to provide the m-sampling clocks CK1 to CKm of a different phase ΔT with one another, namely whose phases are preciously shifted by ΔT with one another.