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36 results about "Tunneling current" patented technology

The tunneling current to the tip measures the density of electrons at the surface of the sample, and this information is displayed in the image. In semiconductors, such as silicon, the electron density reaches a maximum near the atomic sites.

Probability bit device based on polyfluoroaryl methyl free radicals and preparation method thereof

The invention relates to the technical field of quantum computing and molecular electronic devices, in particular to a probabilistic bit device based on polyfluoroaryl methyl free radicals and a preparation method of the probabilistic bit device. According to the probabilistic bit device, the coupling efficiency of molecules and electrodes is improved by virtue of the characteristic that the paramagnetic unpaired electron spin state of tri (polyfluoroaryl) methyl free radical molecules can be used as a random expansion physical entropy source and high electronegativity and stability formed by modification of a plurality of strong electron-withdrawing fluorine atoms in the molecules. During the operation period of the device, the spin fluctuation can efficiently regulate and control tunneling current passing through molecules, promote random conversion between output high and low current states, show excellent random binary fluctuation characteristics, and simultaneously have high sensitivity and long coherence time. Compared with the prior art, the device has remarkable advantages in the aspects of device stability, energy efficiency ratio and external field controllability. The preparation method is simple and convenient to operate, mild in reaction condition and beneficial to large-scale production.
Owner:NANKAI UNIV

Atomic-scale construction method for manufacturing semiconductor substrate quantum simulator

ActiveCN121619916AIndividual molecule manipulationScanning tunneling microscopeParticle physics
The invention discloses an atomic-scale construction method for manufacturing a semiconductor substrate quantum simulator, which comprises the following steps: firstly, depositing singly distributed metal atoms on a semiconductor substrate at a controllable deposition rate by adopting a vacuum thermal evaporation method, and then depositing metal atoms on the semiconductor substrate at a controllable deposition rate by utilizing a longitudinal control method of a scanning tunneling microscope (STM). The metal atoms adsorbed on the surface of the substrate are carried at a target position by accurately regulating and controlling the dragging speed of the needle tip, the tunnel junction bias voltage and the tunneling current, so that lifting, placing and moving of a single atom are realized. The construction of artificial quantum dots and quantum dot molecules is realized by regulating and controlling the distance between metal atoms. A source electrode, a drain electrode and a grid electrode of quantum dot molecules are controlled in an integrated mode through vacuum evaporation, and the quantum simulator capable of simulating quantum behaviors of a specific molecular structure is formed. According to the invention, the coupling strength of the artificial quantum dot molecules is accurately regulated and controlled through the external grid voltage, and the quantum characteristics of molecule front track filling and electron transport kinematics thereof can be accurately simulated.
Owner:XI AN JIAOTONG UNIV

Simulation test device and method for fluid channeling ratio of adjacent tunnels in combination with boundary conditions

The invention discloses an adjacent tunnel fluid channeling ratio simulation test device and method combined with boundary conditions, the adjacent tunnel fluid channeling ratio simulation test device combined with the boundary conditions comprises an upstream tunnel model, a downstream tunnel model and a middle section road surface, and the side surface of the middle section road surface is provided with a crosswind simulation mechanism. And a full-spectrum lamp is arranged above the middle section of the road surface. The invention further relates to an adjacent tunnel fluid channeling ratio simulation test method in combination with the boundary conditions. According to the method, the sulfur hexafluoride (SF6) concentration is used as a basis for quantitatively calculating the fluid channeling ratio, fluid channeling analysis of traffic pollutants and high-temperature fire smoke can be combined, and a more accurate adjacent tunnel pollutant fluid channeling ratio is obtained by combining terrain wind environment boundary conditions and pavement thermal environment boundary conditions; and more reliable experimental data is provided for the design of adjacent tunnels and the type selection of ventilation and fire fighting equipment.
Owner:CHIFENG UNIV

P-on-n type hgi-cdte in-situ growth embedded planar heterojunction detector and preparation method thereof

The application provides a P-on-n type tellurium cadmium mercury in-situ growth embedded planar heterojunction detector, characterized by comprising, from bottom to top, a substrate material layer, an n-type absorption layer, an n-type isolation grid layer for isolating pixels, an array P-type cap region located in the isolation grid of the n-type isolation grid layer, a passivation layer covering the n-type isolation grid layer and the array p-type cap region, an electrode contact hole arranged in the array P-type cap region and not covered by the passivation layer, and a contact electrode layer arranged in the electrode contact hole. The n-type isolation grid layer is used for isolating tellurium cadmium mercury heterojunction materials into independent pixels, the array P-type Cap region is used for growing and forming a pixel structure, a tellurium cadmium mercury p-on-n heterojunction detector is obtained, damage to the tellurium cadmium mercury material is effectively avoided, leakage caused by poor coverage and interface compactness of the passivation layer is avoided through planar passivation, interface defects are reduced, tunneling current is inhibited, and the performance of the detector is improved.
Owner:KUNMING INST OF PHYSICS

Van der waals contact vertical p-n junction diode and preparation method thereof, semiconductor device

The application discloses a kind of based on van der waals contact vertical p-n junction diode and preparation method, semiconductor device.The two-dimensional material vertical p-n junction diode includes metal top electrode, p-type two-dimensional material, n-type two-dimensional material and bottom electrode from top to bottom vertically stacked, wherein, the material between adjacent two layers is formed by van der waals force van der waals contact, so that the material of adjacent two layers mutually adhere and do not fall off.Based on the interface of vertical p-n junction diode of van der waals contact is flat and has no defect and lattice damage, avoid the damage of traditional evaporation method to two-dimensional material lattice, make that the schottky barrier and tunneling current caused by fermi pinning in device significantly reduce, to greatly improve the rectification performance of the device.The application solves the technical problem that existing two-dimensional material vertical p-n junction device has schottky barrier and larger tunneling current.
Owner:HUAZHONG UNIV OF SCI & TECH

Simulation method for semiconductor device, electronic device, and storage medium

Example embodiments of the present disclosure relate to a simulation method for a semiconductor device, an electronic device and a storage medium. The method comprises: discretizing a barrier-related parameter based on a predetermined range and a step length of the predetermined barrier-related parameter to generate a plurality of first data points; and determining a transmission coefficient corresponding to each of the plurality of first data points, wherein the transmission coefficient comprises a first transmission coefficient corresponding to a first barrier unit having a constant barrier height and a second transmission coefficient corresponding to a second barrier unit having a linearly varying barrier height. Embodiments of the present disclosure can efficiently and accurately calculate the barrier transmission coefficient for any shape barrier, improve the calculation efficiency of the tunneling current, and thus reduce the calculation amount and save costs.
Owner:QUANZHIXIN (SHANGHAI) TECH CO LTD

A base sequencing verification method and system based on ion current and tunneling current characteristics

The application relates to a base sequencing verification method based on ion current and tunneling current characteristics, which comprises the following steps: measuring ion current and tunneling current; comparing the drop of the ion current with a standard ion current drop to obtain the classification probability of the base corresponding to the ion current belonging to the base corresponding to the standard ion current drop; comparing the tunneling current with a standard tunneling current to obtain the classification probability of the base corresponding to the tunneling current belonging to the base corresponding to the standard tunneling current; distributing a time weight to the classification probability of the ion current according to the time of measuring the ion current relative to the time of measuring the tunneling current; inputting the classification probability of the ion current, the time weight of the classification probability of the ion current and the classification probability of the tunneling current into a neural network model to obtain a probability; and taking the base type corresponding to the maximum probability as the type of a base to be identified. The application can improve the accuracy and reliability of base identification and reduce the error rate of base identification.
Owner:SHANGHAI BAICE TECH CO LTD

Light-emitting diode, light-emitting device and light-emitting device

The invention provides a light-emitting diode, a light-emitting device and a light-emitting device. According to the invention, the P-type doped first ohmic contact layer is formed on one side of the N-type semiconductor layer, and the first electrode formed by the transparent conductive material is formed above the first ohmic contact layer. The first electrode and the P-type first ohmic contact layer can form forward current conduction from the first ohmic contact layer to the first electrode, and on the other hand, a strong built-in electric field is formed between the heavily-doped P-type first ohmic contact layer and the N-type semiconductor layer, so that the valence band top electron energy level of the P side is higher than the conduction band bottom electron energy level of the N side; therefore, a forward tunneling current from the N-type semiconductor layer to the P-type first ohmic contact layer can be generated under the action of an external electric field, so that the light-emitting diode has good electrical performance; a metal material layer is not formed between the first electrode and the first ohmic contact layer any more, so that light absorption and shielding are reduced, and the light emitting effect of the light emitting diode is improved.
Owner:QUANZHOU SANAN SEMICON TECH CO LTD

Memory device and manufacturing method thereof

ActiveUS12701711B2Bit lineEmbedded system
A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source / drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source / drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

In-situ transmission electron microscope sample rod integrated with scanning tunneling microscope and detection method

PendingCN122158433AElectric discharge tubesMaterial analysis by transmitting radiationIn situ transmission electron microscopyParticle physics
The application discloses an in-situ transmission electron microscope sample rod integrated with a scanning tunneling microscope and a detection method, and belongs to the technical field of electron microscopes. The sample rod comprises a sample rod body, an axial STM probe assembly integrated with the sample rod head, a front-end rotatable sample support and a linear-rotation conversion driving mechanism. The linear-rotation conversion driving mechanism converts axial linear motion into angular displacement, and drives the rotatable sample support to be in-situ flipped by 90 DEG between a horizontal TEM mode and a vertical STM mode. In the STM mode, the sample surface is parallel to the electron beam and opposite to the STM probe tip, and at the same time, an automatic electrical contact assembly is closed to realize reliable grounding of the sample. The application effectively solves the problems of geometric visual angle conflict, electron beam scattering interference and unstable grounding existing in the traditional combined technology, and realizes lossless, high signal-to-noise ratio in-situ switching of transmission imaging and tunneling current analysis in a vacuum environment.
Owner:YUNNAN UNIV

A schottky transistor implementing a metal-semiconductor tunneling schottky junction and a method of fabricating the same

ActiveCN121310605Bachieve tunneling effectReduce contact resistanceSemiconductor materialsOhmic contact
The application discloses a Schottky transistor realizing a metal-semiconductor tunneling Schottky junction and a preparation method thereof, and belongs to the technical field of semiconductor electronic devices. The application utilizes the characteristic that the width of a depletion layer is inversely proportional to the tunneling strength, constructs a Schottky contact and an ohmic contact between a metal and a semiconductor, limits the width of the depletion layer by using an external physical means to obtain a semiconductor material with an extremely thin physical thickness, and applies a gate voltage to modulate the width of a Schottky barrier of a metal-semiconductor Schottky junction generated by the Schottky contact, so as to realize the tunneling effect of electrons from the semiconductor material to the metal material. The width of the barrier of the metal-semiconductor interface is dynamically modulated by the gate voltage, so that the tunneling current is accurately controlled.
Owner:GUANGDONG UNIV OF TECH

Preparation method of laminated PbS quantum dot detector

PendingCN121941186Alow densityRaise the barrierHole transport layerDark current
The invention discloses a preparation method of a laminated PbS quantum dot detector, and belongs to the technical field of infrared detectors. The method comprises the following steps: preparing a ligand and a dispersing agent; providing a substrate; preparing a bottom electrode on the substrate; preparing a hole transport layer on the bottom electrode, wherein the hole transport layer comprises a NiOx thin film and a PbS-EDT thin film; preparing a long-wave light absorption layer on the hole transport layer, wherein the long-wave light absorption layer comprises 2000nm PbS CQD; preparing a short-wave light absorption layer on the long-wave light absorption layer, wherein the short-wave light absorption layer comprises 1550nm PbS CQD; preparing an electron transport layer on the short-wave light absorption layer, wherein the electron transport layer comprises a C60 thin film and a thin film; and preparing a top electrode on the electron transport layer. According to the method, the short-wave light absorption layer and the electron transmission layer are in direct contact to form a main junction, the electron tunneling potential barrier is increased by utilizing the wide-band gap characteristic of the short-wave light absorption layer, meanwhile, the defects are low, trap auxiliary tunneling current is reduced, dark current is reduced, and full coverage of 1550-2000 nm can be achieved through the design of stacking the long-wave light absorption layer and the short-wave light absorption layer.
Owner:HUAZHONG UNIV OF SCI & TECH +1

Simulation method for semiconductor device, electronic equipment and storage medium

The embodiment of the invention relates to a simulation method for a semiconductor device, electronic equipment and a storage medium. The method comprises the following steps: discretizing barrier-related parameters based on a predetermined range and step length of the predetermined barrier-related parameters to generate a plurality of first data points; and determining a transmission coefficient corresponding to each of the plurality of first data points, where the transmission coefficients include a first transmission coefficient corresponding to a first barrier cell having a constant barrier height and a second transmission coefficient corresponding to a second barrier cell having a linearly varying barrier height. According to the embodiment of the invention, the barrier transmission coefficient can be efficiently and accurately calculated for barriers in any shape, the calculation efficiency of the tunneling current is improved, the calculation amount is further reduced, and the cost is saved.
Owner:QUANZHIXIN (SHANGHAI) TECH CO LTD

Gate tunneling current model and extraction method thereof

ActiveCN115526143BDevice materialEngineering
The application discloses a gate tunneling current model for simulating a gate tunneling current of a semiconductor device; the gate tunneling current of the gate tunneling current model is formed by multiplying a main function by a first function; the first function is a function formed by active region environment parameters of the semiconductor device and used for simulating the influence of the active region environment on the gate tunneling current. The application further discloses an extraction method of the gate tunneling current model. The application can simulate the influence of the active region environment on the gate tunneling current of the device, thereby improving the model fitting precision and being beneficial to designing a more reasonable layout.
Owner:SHANGHAI HUALI INTEGRATED CIRCUIT CORP

Hybrid access mechanism surround gate transistor and method of making the same

ActiveCN116247099BMOSFETField effect
The application provides a hybrid conduction mechanism surrounding gate transistor, which comprises a surrounding gate MOSFET device, a second source region and a second drain region; the surrounding gate MOSFET device comprises a substrate, a first source region and a first drain region; the first source region and the first drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, and the height of the second source region and the second drain region is not lower than the height of the substrate between the first source region and the first drain region; the second drain region is doped with the first ions, and the second source region is doped with second ions. The technical scheme solves the problem of bottom parasitic channel current leakage of the surrounding gate MOSFET device, and by additionally arranging the second source region and the second drain region, a tunneling field effect transistor (TFET) device structure is connected in parallel at the bottom of the traditional surrounding gate MOSFET device, so that the surrounding gate channel diffusion drift current and the bottom channel band-to-band tunneling current are hybridly conducted, and better super-steep switching characteristics are obtained.
Owner:FUDAN UNIVERSITY +1

A non-scanning single-photon polarization three-dimensional imaging method

The present application relates to a kind of non-scanning single-photon polarization three-dimensional imaging method, comprising: constructing pulse laser echo photon number calculation model: pulse laser emits laser pulse, after each light pulse is irradiated to target, the photon number of return to single-photon avalanche photodetector each pixel is related to detection distance;Construct single-photon detector signal and noise model: signal photon and background photon are incident on the photosensitive surface of detector to complete photon injection, based on the quantum efficiency of detector, photoelectric conversion is generated echo electron and canister noise electron, noise electron is generated by thermal current, tunneling current, then carries out electric injection, then based on avalanche probability, avalanche multiplication is completed, and finally, the signal is read out through avalanche signal detection;Construct polarization modulation laser radar ranging model, improve target polarization three-dimensional imaging distance.
Owner:BEIJING RES INST OF SPATIAL MECHANICAL & ELECTRICAL TECH

Fin field-effect transistor device with hybrid conduction mechanism

A fin field-effect transistor device with hybrid conduction mechanism, including a fin field-effect transistor, a second source region, and a second drain region; the fin field-effect transistor includes a substrate, a fin channel region, a first source region, and a first drain region; the height of the second source region is not lower than the height of the substrate between the first source region and the first drain region; the first source region the first drain region and the second drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, the second source region is doped with second ions. This scheme can realize hybrid conduction of fin channel diffusion drift current and bottom channel band-to-band tunneling current, thus obtaining better ultra-steep switching characteristics.
Owner:FUDAN UNIVERSITY +1

DNA modification and positioning method based on quantum dots

The invention discloses a DNA modification and positioning method based on quantum dots, and relates to the technical field of DNA sequencing, and the method comprises the following steps: S1, combining CdSe quantum dots at the tail end of DNA to form a DNA and quantum dot compound; s2, enabling the DNA and quantum dot compound to pass through a nanopore of a nanopore detection system under the driving of an electric field, and collecting a tunneling current signal in real time by utilizing a current amplifier of the nanopore detection system; s3, performing filtering and noise reduction processing on the acquired tunneling current signal to obtain a processed current signal; s4, the processed current signals are subjected to feature recognition, the current base type and a recognition result are obtained, and the recognition result is recognition accuracy or recognition inaccuracy. According to the invention, the signal-to-noise ratio of single-base identification is improved, and the accuracy and stability of base identification are improved.
Owner:SHANGHAI BAICE TECH CO LTD

Ferroelectric transistor read-write method with high durability and high current reliability

The invention discloses a ferroelectric transistor read-write method with high durability and high current reliability. A used ferroelectric transistor comprises a P-type doped semiconductor substrate, an N-type doped source electrode, a P-type doped drain electrode, a ferroelectric gate stack and a control gate. Corresponding level or floating operation is applied to the source electrode, the drain electrode and the control gate respectively in the write-in and read-out operation processes. The source electrode is floated in the writing process, so that excessive electron trapping is avoided, electrons required by ferroelectric flipping are provided by utilizing a band-to-band tunneling mechanism at the drain electrode, the increase of interface traps is reduced, and the durability is improved. In the read-out stage, the band-to-band tunneling current at the source electrode is used for reading out, and the current is not influenced by an interface state generated at the drain electrode in the writing process, so that excellent current reliability is obtained. The method does not involve the change of the gate stack material and structure of the ferroelectric transistor, does not need to introduce additional recovery cycle and corresponding area and delay cost, and is high in practical value.
Owner:PEKING UNIV

A scanning tunneling microscope device for electron spin resonance detection

The application discloses a scanning tunnel microscope device for realizing electron spin resonance detection and relates to the technical field of microscopes. The scanning tunnel microscope device for realizing electron spin resonance detection comprises a base, a needle tip arranged on the base, the needle tip being configured to run and generate a tunneling current with a sample on the base, a microwave excitation component, the microwave excitation component comprising an antenna and a microwave signal generation and modulation structure, the antenna being arranged on the base, and the microwave signal generation and modulation structure being configured to transmit microwave signals to the antenna and / or the needle tip, and a magnet component arranged on the side of the base away from the needle tip. The microwave radiation direction of the antenna is towards the needle tip. The technical scheme of the application is characterized in that the antenna is arranged on one side of the base, and the microwave signal generation and modulation structure is configured to inject microwave signals to the antenna and / or the needle tip, so as to improve the microwave excitation efficiency and frequency coverage capability and significantly improve the stability of the spin resonance signal and the system adaptability.
Owner:PEKING UNIV

Nanoscale plane parallel calibration and adjustment method

The invention discloses a nanoscale plane parallel calibration and adjustment method, and relates to the technical field of micro-nano manufacturing. The method comprises the following steps: step 1, initializing a plane parallel calibration sensor and a plane distance measurement adjustment sensor; 2, carrying out plane distance measurement adjustment by using a plane distance measurement adjustment sensor; step 3, performing plane parallel calibration by using a plane parallel calibration sensor; and 4, replacing the sample, and performing plane scanning / etching after real-time adjustment. Measurement modes required by calibration and adjustment are isolated, plane parallel calibration is performed by using tunneling current measurement, plane distance measurement and adjustment are performed by using a superposed laser interferometer, and the method has the advantages of high stability, high scene adaptability, usability and low cost.
Owner:SHANGHAI JIAOTONG UNIV

HgCdTe double-layer component hetero-plane junction infrared detector and preparation method

This invention discloses a mercury cadmium telluride (HCDT) bilayer heterojunction detector, comprising a substrate material layer, an n-type absorber layer, a surface n-type wide bandgap heterojunction layer, a passivation layer, and a contact electrode layer stacked together. The surface n-type wide bandgap heterojunction layer is a wide bandgap heterojunction layer prepared on the surface of the n-type absorber layer using mercury-rich vertical liquid phase epitaxy, with the remaining impurities being n-type. The passivation layer covers at least a portion of the area of ​​the isolation region and the p-type implantation region in the orthographic projection direction, and the portion of the passivation layer not covering the p-type implantation region forms a contact hole. The contact electrode layer contacts the p-type implantation region, and the orthographic projection area of ​​the contact electrode is larger than and covers the contact hole. This invention utilizes the n-type wide bandgap heterojunction layer growth process to achieve interfacial interdiffusion, and realizes a HCDT p-on-n planar heterojunction device through As ion implantation. This invention can effectively suppress tunneling current and surface leakage current, reduce dark current, and improve device performance.
Owner:KUNMING INST OF PHYSICS

A P + -vN + Mercury cadmium telluride mesa heterojunction infrared detector and its fabrication method

This invention discloses a P + -v-N + A novel mercury cadmium telluride mesa heterojunction infrared detector and its fabrication method, utilizing liquid-phase epitaxy to achieve P + -v material structure fabrication: N is prepared on the surface of the v-shaped layer using a back-implantation method. + After annealing, a three-layer hetero-doped material structure was fabricated, and P was then fabricated using device fabrication technology. + -v-N + This invention relates to a P-type mercury cadmium telluride mesa heterojunction detector. It utilizes the P-type wide-bandgap heterolayer growth process to achieve interfacial interdiffusion, reducing interface defect density and improving interface quality. Based on the ability to control raw material impurities above 7N and the self-purification characteristics of the growth process, it achieves stable control of low-concentration V-type layer impurities. Furthermore, it utilizes a high-resistivity transition layer formed by epitaxy and N-type metallurgical layer formed by boron ion implantation. + Layer; RTP fast annealing is used to repair injection damage. This invention can effectively suppress recombination current. Its surface heteromaterial forms a band modulation structure that suppresses tunneling current and surface leakage current. Compared with P-on-n devices, it can theoretically reduce dark current by two orders of magnitude and improve device performance.
Owner:KUNMING INST OF PHYSICS

Base sequencing verification method and system based on ionic current and tunneling current characteristics

The invention relates to a base sequencing verification method based on ionic current and tunneling current characteristics. The method comprises the following steps: measuring ionic current and tunneling current; comparing the decreasing amplitude of the ionic current with a standard decreasing amplitude of the ionic current to obtain a classification probability that the basic group corresponding to the ionic current belongs to the basic group corresponding to the standard decreasing amplitude of the ionic current; comparing the tunneling current with a standard tunneling current to obtain a classification probability that the basic group corresponding to the tunneling current belongs to the basic group corresponding to the standard tunneling current; distributing a time weight for the classification probability corresponding to the ion current according to the moment when the ion current is measured relative to the moment when the tunneling current is measured; inputting the classification probability corresponding to the ion current, the time weight of the classification probability corresponding to the ion current and the classification probability corresponding to the tunneling current into a neural network model to obtain a probability; and taking the base type corresponding to the maximum probability as the type of the base to be identified. According to the invention, the accuracy and reliability of base identification can be improved, and the error rate of base identification is reduced.
Owner:SHANGHAI BAICE TECH CO LTD

Solar cell and preparation method thereof

PendingCN121398259AElectrical batterySolar cell
The invention relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof.The solar cell comprises a substrate, a front passivation layer, a back passivation layer, an N-type doping layer and a P-type doping layer; the front passivation layer is formed on the front surface of the substrate; the back passivation layer is formed on the back; the N-type doping layer is formed on the front passivation layer; the P-type doping layer comprises an in-situ doping layer and a gradient doping layer, the in-situ doping layer is formed on the back passivation layer, and the gradient doping layer is formed on the in-situ doping layer; the doping concentration of the in-situ doping layer is smaller than the doping concentration of the gradient doping layer. According to the solar cell, unexpected tunneling current or interface recombination current can be weakened, the problem of reverse breakdown risk of a PN junction under a high electric field is solved, the problem of damage to a passivation layer of the cell is further solved, the performance of the passivation layer and a doping layer of a cell piece is improved, the reliability of the solar cell is improved, and the yield of the solar cell is increased.
Owner:TONGWEI SOLAR ENERGY (CHENGDU) CO LID

Polyfluoroarylmethyl radical-based probabilistic bit device and method of making same

The present application relates to the technical field of quantum computing and molecular electronic devices, and particularly relates to a probability bit device based on a polyfluoro aryl methyl radical and a preparation method thereof. The probability bit device can be used as a random fluctuation physical entropy source by virtue of the characteristic that the unpaired electron spin state of the paramagnetic three (polyfluoro aryl) methyl radical molecule can be used as a random fluctuation physical entropy source, and the high electronegativity and stability formed by the modification of multiple strong electron-withdrawing fluorine atoms in the molecule improve the coupling efficiency of the molecule and the electrode. During the operation of the device, the spin fluctuation can efficiently regulate the tunneling current through the molecule, promote the random transition between the high and low current states of the output, and exhibit excellent random binary fluctuation characteristics, while having high sensitivity and long coherence time. Compared with the prior art, the present application has significant advantages in device stability, energy efficiency ratio and external field controllability. The preparation method is simple in operation and mild in reaction conditions, and is conducive to large-scale production.
Owner:NANKAI UNIV

Preparation method of fin type tunneling field effect transistor

PendingCN121908567AField effectPhotolithography
The invention provides a preparation method of a fin type tunneling field effect transistor, and belongs to the technical field of micro-nano electronics. A traditional planar TFET device and a FinFET structure are combined, the advantage of low off-state current can be kept while on-state current can be improved, bipolar current is restrained, namely, an expansion region is prepared in a source region in a self-alignment mode, so that a tunneling junction is formed at the gate-source overlapping position, tunneling current is improved, and meanwhile, through a thick side wall prepared before source-drain epitaxy, the tunneling efficiency is improved. An under-coverage area structure is formed at the drain terminal to suppress bipolar current; meanwhile, the main body of the substrate region of the device is still lightly doped high-resistance silicon, so that the advantage of low off-state current of the tunneling field effect transistor is maintained. Besides, the preparation method is based on a standard fin type tunneling field effect transistor process flow of an advanced node, only one photoetching plate is additionally arranged on the premise of not changing a basic process flow, and the potential of realizing large-scale production is maintained.
Owner:PEKING UNIV

Semiconductor structure, self-supporting gallium nitride layer and method for producing same

The application relates to a semiconductor structure, a self-supporting gallium nitride layer and a preparation method thereof. The method comprises the following steps: providing a substrate, forming a patterned mask layer on the surface of the substrate; placing the substrate provided with the patterned mask layer into a substrate area; providing a first reaction gas containing hydrogen chloride to a gallium boat area through a first gas supply pipeline and providing a second reaction gas containing ammonia to the substrate area through a second gas supply pipeline to form a gallium nitride seed layer; stopping providing the first reaction gas and the second reaction gas and providing a third reaction gas containing hydrogen chloride to the substrate area through a third gas supply pipeline to completely remove the gallium nitride seed layer in a first area or make the thickness of the gallium nitride seed layer in the first area smaller than the thickness of the gallium nitride seed layer in a second area; and forming a doped thick film gallium nitride layer. The application can improve the quality of the doped thick film gallium nitride layer, help automatic peeling of the doped thick film gallium nitride layer, reduce the series resistance of a device, and increase the tunneling current.
Owner:ETA RES

Full-plane octagonal six-dimensional force sensor for robot knuckle

The invention provides a full-plane octagonal six-dimensional force sensor for robot knuckles, and relates to the technical field of mechanical sensors, the full-plane octagonal six-dimensional force sensor comprises an elastic body, the elastic body comprises a fixed table and a central loading table, and an octagonal beam is fixedly arranged between the fixed table and the central loading table; six groups of Wheatstone bridges are formed by using 24 strain gauges, tensile stress and pressure stress during elastic deformation are analyzed, bridge arm voltages of the four strain gauges in a bridge circuit in the coupling direction are mutually offset, and inter-dimensional coupling is directly eliminated from the aspect of structural design; the silicon strain gauges are mounted by adopting a full-plane process, so that the lead bonding difficulty is low, the patch size is relatively small, and the mechanical assembly difficulty is reduced; by introducing a quantum tunneling effect enhancement structure, high-sensitivity detection on tiny deformation of the knuckle is realized; and the sum of output six-dimensional force signals is realized for the deformation values of the quantum tunneling current and the strain gauges through a nonlinear coupling model.
Owner:SHENZHEN AMPRON TECH CORP