396 results about "Tunneling current" patented technology

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F<2 >memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.

A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques. The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that. A polysilicon control gate is formed on the top gate insulator.

A sensor for contactlessly detecting currents, has a sensor element having a magnetic tunnel junction (MTJ), and detection circuitry, the sensor element having a resistance which varies with the magnetic field, and the detection circuitry is arranged to detect a tunnel current flowing through the tunnel junction. The sensor element may share an MTJ stack with memory elements. Also it can provide easy integration with next generation CMOS processes, including MRAM technology, be more compact, and use less power. Solutions for increasing sensitivity of the sensor, such as providing a flux concentrator, and for generating higher magnetic fields with a same current, such as forming L-shaped conductor elements, are given. The greater sensitivity enables less post processing to be used, to save power for applications such as mobile devices. Applications include current sensors, built-in current sensors, and IDDQ and IDDT testing, even for next generation CMOS processes.

An apparatus and method for performing nucleic acid (DNA and/or RNA) sequencing on a single molecule. The genetic sequence information is obtained by probing through a DNA or RNA molecule base by base at nanometer scale as though looking through a strip of movie film. This DNA sequencing nanotechnology has the theoretical capability of performing DNA sequencing at a maximal rate of about 1,000,000 bases per second. This enhanced performance is made possible by a series of innovations including: novel applications of a fine-tuned nanometer gap for passage of a single DNA or RNA molecule; thin layer microfluidics for sample loading and delivery; and programmable electric fields for precise control of DNA or RNA movement. Detection methods include nanoelectrode-gated tunneling current measurements, dielectric molecular characterization, and atomic force microscopy/electrostatic force microscopy (AFM/EFM) probing for nanoscale reading of the nucleic acid sequences.

Systems and methods of identifying molecules of polymers such as, for example, a nucleic acid, are described. The method involves centering a bias voltage across a pair of nano-electrodes separated by a channel that corresponds to one of any of the energy differences between any two internal energy levels of a molecule of interest, and modulating the bias voltage with a modulation waveform while the molecule of interest is in the channel. An electrical signal characteristic of the molecule of interest is derived from the tunneling current between the nano-electrodes, and the characteristic electrical signal is compared with known values of the signal for chemically-known molecules in order to identify the molecule of interest. Multiple pairs of nano-electrodes may be employed to identify more reliably a single molecule or multiple molecules.

A method for controlling a gap in an electrically conducting solid state structure provided with a gap. The structure is exposed to a fabrication process environment conditions of which are selected to alter an extent of the gap. During exposure of the structure to the process environment, a voltage bias is applied across the gap. Electron tunneling current across the gap is measured during the process environment exposure and the process environment is controlled during process environment exposure based on tunneling current measurement. A method for controlling the gap between electrically conducting electrodes provided on a support structure. Each electrode has an electrode tip separated from other electrode tips by a gap. The electrodes are exposed to a flux of ions causing transport of material of the electrodes to corresponding electrode tips, locally adding material of the electrodes to electrode tips in the gap.

A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

A method of making thermodynamically stable, diffusion-impeded barrier layers within, for example, a photovoltaic cell with a metal-containing electrical contact using exposure to fluorine. Exposing the cadmium telluride surface to fluorine creates a Te-poor barrier layer of cadmium fluoride. Once that barrier layer is formed, the metal-containing electrical contact may be applied or formed. The barrier layer allows tunneling current to occur between the p-type layer and the metal-containing electrical contact establishing a low-resistance, highly uniform, and thermally stable electrical contact.

A disc drive that includes a slider with a field emission sensor that senses fly height. The sensor has an electrode tip disposed on the slider. The electrode tip faces a media surface across a gap. The sensor conducts a tunneling current through the gap and provides an output representing the length of the gap. An actuator adjusts the fly height spacing. A feedback circuit provides an actuator electrical input as a feedback function of the sensor output to control the fly height spacing.

A MONOS type nonvolatile memory cell is structured such that a laminated insulating film which is formed by sequentially laminating a tunnel insulating layer, a charge storage insulating layer, and a charge block insulating layer is provided on a convex curved surface portion of a semiconductor substrate, and a control gate electrode is further formed thereon. A thickness of the tunnel insulating layer is set to be 4 to 10 nm, and data writing/data erasing operations are carried out by making an F-N tunneling current flow in the tunnel insulating layer.

The invention discloses a resonance-equilibrium tunnel current type three-axis acceleration transducer and a manufacturing method thereof, which belong to the field of microelectronic mechanical systems. The resonance-equilibrium tunnel current type three-axis acceleration transducer is structurally characterized in that the three-axis transducer comprises an intermediate silicon wafer (1), a top cover plate (2) and a bottom plate (3), and double-end fixing beam resonators (4), a mass block (6) and supporting beams (5) are manufactured on the intermediate silicon wafer (1). Besides, in the aspect of the detection principle, acceleration signals of the X-axis and the Y-axis in the plane of the chip are detected by the double-end fixing beam resonators (4), variation of resonant frequency of the double-end fixing beam resonators (4) reflects acceleration and direction thereof, a tunnel tip (9), a control electrode (10) and a biased electrode (7) form a portion for detecting acceleration signal of the Z-axis, detection is realized according to the tunnel current type sensitive principle, and the transducer works in a closed-loop equilibrium mode. Besides, the normal displacement of the mass block (6) on the chip is small, and the cross interference introduced by the acceleration signals of the Z-axis to detection of X-axis acceleration and Y-axis acceleration is low.

In a miniaturized transistor, a gate insulating layer is required to reduce its thickness; however, in the case where the gate insulating layer is a single layer of a silicon oxide film, a physical limit on thinning of the gate insulating layer might occur due to an increase in tunneling current, i.e. gate leakage current. With the use of a high-k film whose relative permittivity is higher than or equal to 10 is used for the gate insulating layer, gate leakage current of the miniaturized transistor is reduced. With the use of the high-k film as a first insulating layer whose relative permittivity is higher than that of a second insulating layer in contact with an oxide semiconductor layer, the thickness of the gate insulating layer can be thinner than a thickness of a gate insulating layer considered in terms of a silicon oxide film.

A floating gate pixel is described which is formed by forming an N well in a P type silicon substrate. A P well is formed in the N well A gate is formed over a thin gate oxide, about 25 Angstroms thickness, such that the gate is directly over part of the P well and part of the N well. A P⁺ contact in the P well allows connection to a reset voltage source, usually through a reset transistor, to reset the pixel. The pixel is reset by setting the potential between the P well and the substrate, which is usually held at ground potential. When the pixel is reset tunneling current through the thin gate oxide sets the voltage of the floating gate. During the charge integration cycle an input signal to the pixel, such as a light signal, changes the potential of the pixel. After the charge integration cycle the tunneling current through the gate oxide changes the potential of the floating gate by an amount related to the input signal to the pixel. The potential of the floating gate can then be read out to determine the input signal to the pixel. The pixel can also be embodied using a P well formed in an N type substrate, an N well formed in the P well, and an N⁺ contact formed in the N well.

A non-volatile memory structure and a method for operating the same are proposed. The non-volatile memory structure makes use of a single floating gate structure and a capacitor structure including a pair of regions doped with different type impurities to increase the capacitance and shrink the area. When performing programming operations to this memory structure, a voltage is applied to the source or a back bias is applied to the substrate of the transistor to greatly reduce the current requirement of a single-gate EEPROM device. When performing erase operations, the drain voltage is raised, and a small voltage is added to the gate to increase the F-N tunneling current, thereby accomplishing the effect of fast erase.

A single electron transistor device for sensing at least one particle, includes at least two electrodes positioned with a gap formed between the electrodes and an activation object positioned in the gap with an insulating layer between the activation object and each electrode. The activation object which is able to transfer electrons is arranged with at least one binding structure bonded to it for receiving the at least one particle. The electrodes are formed with an inter distance of less than 50 nm and the electrodes are connectable directly or indirectly to a signal acquisition system. The sensing device is arranged to allow a tunnelling current proportional to the presence of the at least one particle in the binding structure, to flow through the activation object. A method, and system using a single electron transistor device fabricated with micro/nano fabrication methods are also disclosed.

Generally, a method and circuit for improving the retention and reliability of unprogrammed anti-fuse memory cells. This is achieved by minimizing the tunneling current through the unprogrammed anti-fuse memory cells which can cause eventual gate oxide breakdown. The amount of time a read voltage is applied to the anti-fuse memory cells is reduced by pulsing a read voltage applied to a wordline connected to the unprogrammed anti-fuse memory cells, thereby reducing the tunneling current. Further tunneling current can be reduced by decoupling the unprogrammed anti-fuse memory cells from a sense amplifier that can drive the corresponding bitline to VSS.

The present invention relates to an impact ionisation avalanche transit time (IMPATT) diode device comprising an avalanche region and a drift region, wherein at least one narrow bandgap region, with a bandgap narrower than the bandgap in the avalanche region, is located adjacent to or within the avalanche region in order to generate within the narrow bandgap region a tunnel current which is injected into the avalanche region. This improves the predictability with which a current can be injected into the avalanche region and enables a relatively narrow pulse of current to be injected into the avalanche region in order to enable a relatively noise free avalanche multiplication. The narrow bandgap region may be located between a heavily doped contact region and the avalanche region and is preferably arranged to generate a tunnel current at the peak reverse bias applied to the diode.

A magnetoresistive element has a ferromagnetic double tunnel junction having a stacked structure of a first antiferromagnetic layer/a first ferromagnetic layer/a first dielectric layer/a second ferromagnetic layer/a second dielectric layer/a third ferromagnetic layer/a second antiferromagnetic layer. The second ferromagnetic layer that is a free layer consists of a Co-based alloy or a three-layered film of a Co-based alloy/a Ni—Fe alloy/a Co-based alloy. A tunnel current is flowed between the first ferromagnetic layer and the third ferromagnetic layer.

According to the invention, a bidirectional semiconductor light emitting element is provided, which comprises: a first semiconductor region of a first type of conductivity; a second semiconductor region of a second type of conductivity provided on the first semiconductor region; a third semiconductor region of a first conductivity type provided on the second semiconductor region; and a semiconductor light emitting layer interposed in the second semiconductor region, the light emitting layer emitting light by an injection of a tunneling current generated at a reverse-biased p-n junction between the first and second regions or between the second and third regions under an application of a voltage of a first polarity across the first and third semiconductor regions, and the light emitting layer emitting light by an injection of a tunneling current generated at another reverse-biased p-n junction between the first and second regions or between the second and third regions under an application of a voltage of a second polarity, which is opposite to the first polarity, across the first and third semiconductor regions.