Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure

A technology of compound gate dielectric and gate dielectric, used in semiconductor devices, electrical components, circuits, etc., can solve problems such as reducing channel mobility, avoid premature breakdown, good surface quality, and weaken the reduction of breakdown voltage. Effect

Inactive Publication Date: 2012-11-14
UNIV OF ELECTRONICS SCI & TECH OF CHINA
View PDF7 Cites 40 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since there are many defects after surface ion implantation, the SiO in the channel implantation region 2 There are still a large number of trap states at the / SiC interface, which not only reduces the channel mobility, but also a large number of SiC / SiO 2 Interface traps and high-field-induced traps together form FN tunneling current, and this gate structure can only partially alleviate gate dielectric breakdown caused by FN tunneling current

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure
  • SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure
  • SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0017] In order to make the technical solution to be explained in the present invention and the superiority of the present invention clearer, the specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings. The specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0018] A SiC VDMOS device with a compound gate dielectric structure, its cell structure is as follows Figure 4 As shown, it includes: metal gate electrode 1, polysilicon gate 2, gate dielectric, metal source electrode 5, silicon carbide N + Source region 6, silicon carbide P + Contact area 7, SiC P-base area 8, SiC Nˉdrift area 9, SiC N + Substrate 10, metal drain electrode 11; cells from bottom to top are metal drain electrode 11, silicon carbide N + Substrate 10, silicon carbide N – Drift region 9; there is a silicon carbide P-base region 8 on both sides of the top of...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with a composite gate dielectric structure, and belongs to the technical field of power semiconductor devices. A thought of differentiating modulation of electric fields is adopted according to difference of intensities of electric fields and difference of defect concentrations of gate dielectrics in different areas, namely, high-k gate dielectrics are adopted in channel regions with high-defect concentration and a low electric field, so that a large quantity of trap states caused by using a SiO2 / SiC interface is avoided; the influence on Fowler-Nordheim (FN) tunneling current is obviously reduced; and meanwhile, because the electric field intensity in a channel injection area is small, the reduction on gate dielectric breakdown voltage caused by small offset of conduction band / valence band is weakened; and moreover, a SiO2 gate dielectric (a junction field-effect transistor (JFET) area is formed in a way of extension and is not subjected to ion injection, the surface quality of the JFET area is good, and the SiO2 / SiC interface state is low) is adopted by the JFET area with low defect concentration and a high electric field, and enough high conduction band offset is supplied by the SiO2 dielectric, so that the ahead breakdown of the gate dielectric is avoided.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and relates to a double diffused metal oxide semiconductor field effect transistor (DMOS) device structure, in particular to a silicon carbide (SiC) DMOS device with a composite gate dielectric structure. Background technique [0002] Silicon carbide (SiC), as a wide-bandgap semiconductor material that has attracted much attention in recent years, has excellent physical properties such as wide bandgap, high critical breakdown electric field, high thermal conductivity, and high electron saturation drift velocity. High power, high frequency, and strong irradiation fields have broad application prospects. [0003] Compared with gallium nitride (GaN) and other wide-bandgap semiconductor materials, SiC materials can directly generate silicon dioxide (SiO2) through thermal oxidation. 2 ), this advantage makes SiC an ideal material for making high-power MOSFET devices. Conventional...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/51
Inventor 邓小川孙鹤饶成元王向东张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products