According to embodiments of the present invention, a
semiconductor device includes a plurality of nanodevices (ND1, ND2) including a plurality of upper transistors and a plurality of lower transistors. The plurality of nanodevices includes upper active regions (135, 140, 145) and lower active regions (120, 125) that are offset from each other across the plurality of upper transistors and the plurality of lower transistors. A first front-side gate
cut dielectric pillar (190, 195) is adjacent to and parallel with a first
nanodevice of the plurality of nanodevices along an x-axis. A backside surface of the first front-side gate
cut dielectric pillar extends a first width along a y-axis. A first backside
dielectric filler (240, 245) is in direct contact with the backside surface of the first front-side gate
cut dielectric pillar. A frontside surface of the first backside dielectric filler extends a second width along the y-axis. The second width is greater than the first width.