Bilateral cut staggered stack field effect transistor

Abstract

According to embodiments of the present invention, a semiconductor device includes a plurality of nanodevices (ND1, ND2) including a plurality of upper transistors and a plurality of lower transistors. The plurality of nanodevices includes upper active regions (135, 140, 145) and lower active regions (120, 125) that are offset from each other across the plurality of upper transistors and the plurality of lower transistors. A first front-side gate cut dielectric pillar (190, 195) is adjacent to and parallel with a first nanodevice of the plurality of nanodevices along an x-axis. A backside surface of the first front-side gate cut dielectric pillar extends a first width along a y-axis. A first backside dielectric filler (240, 245) is in direct contact with the backside surface of the first front-side gate cut dielectric pillar. A frontside surface of the first backside dielectric filler extends a second width along the y-axis. The second width is greater than the first width.

Description

Background Technology

[0001] This invention relates generally to the field of microelectronics, and more specifically, to a semiconductor device structure and a method for forming a semiconductor device.

[0002] Nanosheets (NS) are the leading device architecture for the continued scaling of CMOS dimensions. However, as device size shrinks and spacing becomes smaller, nanosheet technology has revealed problems, namely, interference between devices. Furthermore, as device size shrinks and spacing becomes smaller, forming connections to the back-side power supply network becomes more difficult. Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor device includes a plurality of nanodevices, each nanodevice comprising a plurality of upper transistors and a plurality of lower transistors. The plurality of nanodevices include upper active regions and lower active regions offset from each other across the plurality of upper and lower transistors. A first front-side gate-cut dielectric post is adjacent to and parallel to a first nanodevice among the plurality of nanodevices along the x-axis. The back surface of the first front-side gate-cut dielectric post extends a first width along the y-axis. A first back-side dielectric filler is in direct contact with the back surface of the first front-side gate-cut dielectric post. The front surface of the first back-side dielectric filler extends a second width along the y-axis. The second width is greater than the first width. Attached Figure Description

[0004] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments, which should be read in conjunction with the accompanying drawings. Various features in the drawings are not drawn to scale and are illustrated for clarity to facilitate understanding of the invention by those skilled in the art in conjunction with the specific embodiments. In the drawings:

[0005] Figure 1 A top view of several nanodevices according to embodiments of the present invention is shown.

[0006] Figures 2-4 Cross sections of multiple nanodevices are shown, respectively, according to embodiments of the present invention, after interlayer dielectric (ILD) deposition, nanosheet formation, shallow trench isolation (STI) region formation, gate formation, gate spacer and internal spacer formation, bottom dielectric isolation (BDI) layer formation, intermediate dielectric isolation (MDI) layer formation, source / drain formation, etch stop layer formation, self-aligned contact (SAC) capping layer formation, and chemical mechanical planarization (CMP).

[0007] Figure 5 A top view of a plurality of nanodevices after the formation of a first trench, a second trench, and a third trench, according to an embodiment of the present invention, is shown.

[0008] Figures 6-8 The X, Y1, and Y2 cross sections of a plurality of nanodevices after the formation of a first trench, a second trench, and a third trench, according to embodiments of the present invention, are shown respectively.

[0009] Figure 9 A top view of a plurality of nanodevices is shown after the formation of a first front gate diced dielectric post, a second front gate diced dielectric post, a first front dielectric pad, a second front dielectric pad, and a front dielectric filler, according to an embodiment of the present invention.

[0010] Figures 10-12 Cross sections X, Y1, and Y2 of a plurality of nanodevices are shown respectively, according to embodiments of the present invention, after forming a first front gate diced dielectric post, a second front gate diced dielectric post, a first front dielectric pad, a second front dielectric pad, and a front dielectric filler.

[0011] Figures 13-15 Cross sections X, Y1, and Y2 of multiple nanodevices are shown respectively, according to embodiments of the present invention, after the formation of the lower source / drain contact, source / drain contact, multiple gate contacts, back-end process (BEOL) layer, and bonding to the carrier wafer.

[0012] Figures 16-18 Cross sections of multiple nanodevices, X, Y1, and Y2, are shown respectively after flipping the carrier wafer and removing the substrate, according to an embodiment of the present invention.

[0013] Figures 19-21 Cross-sections of multiple nanodevices, X, Y1, and Y2, are shown respectively, after the etch stop layer and the underlying substrate layer have been removed, according to an embodiment of the present invention.

[0014] Figures 22-24 Cross sections of multiple nanodevices after back-side ILD (BILD) layer deposition and CMP are shown, according to embodiments of the present invention.

[0015] Figures 25-27 The X, Y1, and Y2 cross sections of a plurality of nanodevices after the formation of the fourth, fifth, and sixth trenches are shown respectively according to embodiments of the present invention.

[0016] Figures 28-30 Cross sections X, Y1, and Y2 of a plurality of nanodevices are shown respectively, according to embodiments of the present invention, after forming a back-side gate-cut dielectric post, a first back-side dielectric pad, a second back-side dielectric pad, a first back-side dielectric filler, and a second back-side dielectric filler.

[0017] Figures 31-33Cross sections X, Y1, and Y2 of multiple nanodevices are shown respectively, according to embodiments of the present invention, after forming multiple back-side source / drain contacts, upper source / drain contacts, and back-side power transmission networks. Detailed Implementation

[0018] This document discloses specific embodiments of the claimed structures and methods; however, it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which can take various forms. The invention can be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Details of well-known features and techniques may have been omitted in the description to avoid unnecessarily obscuring the presented embodiments.

[0019] It should be understood that, unless the context clearly specifies otherwise, the singular forms of “a,” “an,” and “the” include plural references. Thus, for example, unless the context clearly specifies otherwise, a reference to “a component surface” includes a reference to one or more of such surfaces.

[0020] References to "an embodiment," "an embodiment," "an exemplary embodiment," etc., in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it should be understood that those skilled in the art can implement that feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.

[0021] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall correspond to the orientation of the disclosed structures and methods as shown in the accompanying drawings. The terms “above,” “on top of,” “on the top,” “formed on,” or “formed on the top of” mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an intermediate element (such as an interface structure) may exist between the first and second elements. The term “direct contact” means that the first element (such as a first structure) and the second element (such as a second structure) are connected at their interface without any intermediate conductive layer, insulating layer, or semiconductor layer.

[0022] To avoid obscuring the presentation of embodiments of the present invention, some process steps or operations known in the art may be combined in the following detailed description for illustrative purposes, and may not be described in detail in some cases. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description focuses more on the unique features or elements of various embodiments of the present invention.

[0023] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be designed without departing from the scope of the invention. It should be noted that various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are illustrated in the following description and drawings. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limited in this respect. Thus, coupling of entities can refer to direct or indirect coupling, and positional relationships between entities can be direct or indirect. As an example of an indirect positional relationship, references in this specification to the formation of layer "A" on layer "B" include a case where one or more intermediate layers (e.g., layer "C") are located between layer "A" and layer "B," provided that the relevant characteristics and functions of layer "A" and layer "B" are not substantially altered by the intermediate layers (multiple layers).

[0024] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms “comprise / comprising,” “include / including,” “have / having,” “contain / containing,” or any variations thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0025] Additionally, the term "exemplary" as used herein means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" can be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" can be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0026] As used herein, the term "about" modifying the quantity of ingredients, components, or reactants used in this invention refers to possible variations in quantity, such as typical measurement and liquid handling procedures used to prepare concentrations or solutions. Furthermore, variations may arise from unintentional errors in measurement procedures, differences in the manufacture, origin, or purity of ingredients used in preparing compositions or carrying out methods. The terms "about" or "substantially" are intended to include the degree of error associated with a measurement of a particular quantity based on equipment available at the time of filing. For example, "about" may include a range of ±8%, or 5%, or 2% of a given value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0027] The various processes used to form microchips that will be packaged into integrated circuits (ICs) can be broadly categorized into four main types: thin film deposition, removal / etching, semiconductor doping, and patterning / photolithography. Deposition refers to any process of growing, coating, or otherwise transferring material on a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and the newer atomic layer deposition (ALD). Removal / etching refers to any process of removing material from a wafer. Examples include etching processes (wet or dry), reactive ion etching (RIE), and chemical mechanical planarization (CMP). Semiconductor doping alters electrical properties by doping (e.g., the source and drain of a transistor), typically through diffusion and / or ion implantation. These doping processes are followed by furnace tube annealing or rapid thermal annealing (RTA). Annealing activates the implanted dopant. Thin films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by applying a voltage.

[0028] Reference will now be made in detail to embodiments of the invention, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements.

[0029] Clause 1. A semiconductor device comprising a plurality of nanodevices, the plurality of nanodevices including a plurality of upper transistors and a plurality of lower transistors, wherein the plurality of nanodevices includes upper active regions and lower active regions offset from each other across the plurality of upper transistors and the plurality of lower transistors. A first front-side gate-cut dielectric post is adjacent to and parallel to the first nanodevice among the plurality of nanodevices along the x-axis, wherein a back-side surface of the first front-side gate-cut dielectric post extends a first width along the y-axis. A first back-side dielectric filler is in direct contact with the back-side surface of the first front-side gate-cut dielectric post, wherein a front-side surface of the first back-side dielectric filler extends a second width along the y-axis, and wherein the second width is greater than the first width.

[0030] Clause 2. The semiconductor device according to Clause 1, wherein the upper active region may include a plurality of upper nanosheets and the lower active region may include a plurality of lower nanosheets, wherein the plurality of upper nanosheets may be closer to the first front gate cleaved dielectric post than the plurality of lower nanosheets.

[0031] Clause 3. A semiconductor device according to any of the preceding clauses, wherein a plurality of upper nanosheets and a plurality of lower nanosheets may be offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0032] Clause 4. A semiconductor device according to any of the preceding clauses, wherein the semiconductor device may include a first front dielectric pad extending along a first inner sidewall of a plurality of upper nanosheets, and a second front dielectric pad extending along a second inner sidewall of the plurality of upper nanosheets. A front dielectric filler may be located between the first and second front dielectric pads.

[0033] Clause 5. The semiconductor device according to any of the preceding clauses, wherein the semiconductor device may further include a back-side gate-cut dielectric post in direct contact with the back-side surface of the front-side dielectric filler.

[0034] Clause 6. A semiconductor device according to any of the preceding clauses, wherein the first front-side dielectric pad, the second front-side dielectric pad, the first front-side gate-cut dielectric post, and the back-side gate-cut dielectric post may comprise the same dielectric material, and wherein the first back-side dielectric filler and the front-side dielectric filler may comprise different dielectric materials.

[0035] Clause 7. A semiconductor device according to any of the preceding clauses, wherein a first front-side gate-cut dielectric post and a back-side gate-cut dielectric post may be offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0036] Clause 8. A semiconductor device according to any of the preceding clauses, wherein the back surface of the front dielectric filler may extend a third width along the y-axis, wherein the front surface of the back gate diced dielectric post may extend a fourth width along the y-axis, and wherein the third width may be greater than the fourth width.

[0037] Clause 9. A semiconductor device comprising a plurality of nanodevices, the plurality of nanodevices including a plurality of upper transistors and a plurality of lower transistors, wherein the plurality of nanodevices includes upper active regions and lower active regions offset from each other across the plurality of upper transistors and the plurality of lower transistors. A first front-side gate-cut dielectric post and a second front-side gate-cut dielectric post are respectively adjacent to and parallel to the first and second nanodevices in the plurality of nanodevices along the x-axis, wherein the back surface of the first and second front-side gate-cut dielectric posts each extends a first width along the y-axis. A first back-side dielectric filler and a second back-side dielectric filler are in direct contact with the back surface of the first and second front-side gate-cut dielectric posts, respectively, wherein the front surface of the first and second back-side dielectric fillers each extends a second width along the y-axis, wherein the second width is greater than the first width.

[0038] Clause 10. The semiconductor device according to any of the preceding clauses, wherein the upper active region may include a plurality of upper nanosheets and the lower active region may include a plurality of lower nanosheets, wherein the plurality of upper nanosheets may be closer to the first front gate cleaved dielectric post than the plurality of lower nanosheets.

[0039] Clause 11. A semiconductor device according to any of the preceding clauses, wherein a plurality of upper nanosheets and a plurality of lower nanosheets may be offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0040] Clause 12. The semiconductor device according to any of the preceding clauses, wherein the semiconductor device may further include a first front dielectric pad extending along a first inner sidewall of a plurality of upper nanosheets, and a second front dielectric pad extending along a second inner sidewall of a plurality of upper nanosheets. A front dielectric filler may be located between the first and second front dielectric pads.

[0041] Clause 13. A semiconductor device according to any of the preceding clauses, wherein the semiconductor device may further include a back-side gate-cut dielectric pillar in direct contact with the back-side surface of the front-side dielectric filler. A first back-side dielectric pad and a second back-side dielectric pad may be disposed along the inner sidewall of the second back-side dielectric filler and the inner sidewall of the first back-side dielectric filler, respectively, wherein the first front-side dielectric pad and the second back-side dielectric pad may be offset from each other across a plurality of upper transistors and a plurality of lower transistors, and wherein the second front-side dielectric pad and the first back-side dielectric pad may be offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0042] Clause 14. The semiconductor device according to any of the preceding clauses, wherein the first front-side dielectric pad, the second front-side dielectric pad, the first front-side gate-cut dielectric post, the second front-side gate-cut dielectric post, the first back-side gate-cut dielectric post, the second back-side gate-cut dielectric post, and the back-side gate-cut dielectric post may comprise the same dielectric material, and wherein the first back-side dielectric filler, the second back-side dielectric filler, and the front-side dielectric filler may comprise different dielectric materials.

[0043] Clause 15. A semiconductor device according to any of the preceding clauses, wherein a front-side dielectric filler and a first back-side dielectric filler may be offset from each other across a plurality of upper transistors and a plurality of lower transistors, and wherein a front-side dielectric filler and a second back-side dielectric filler may be offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0044] Clause 16. A semiconductor device according to any of the preceding clauses, wherein a first front-side gate-cut dielectric post and a back-side gate-cut dielectric post may be offset from each other across a plurality of upper transistors and a plurality of lower transistors, and wherein a second front-side gate-cut dielectric post and a back-side gate-cut dielectric post may be offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0045] Clause 17. A semiconductor device comprising a plurality of nanodevices, the plurality of nanodevices including a plurality of upper transistors and a plurality of lower transistors, wherein the plurality of nanodevices includes upper active regions and lower active regions offset from each other across the plurality of upper transistors and the plurality of lower transistors, wherein the upper active regions include upper source / drain electrodes, and wherein the lower active regions include lower source / drain electrodes. A first front-side gate-cut dielectric post and a second front-side gate-cut dielectric post are respectively adjacent to and parallel to the first and second nanodevices in the plurality of nanodevices along the x-axis, wherein the back surface of the first and second front-side gate-cut dielectric posts each extends a first width along the y-axis. A first back-side dielectric filler and a second back-side dielectric filler are in direct contact with the back surface of the first and second front-side gate-cut dielectric posts, respectively, wherein the front surface of the first and second back-side dielectric fillers each extends a second width along the y-axis, wherein the second width is greater than the first width.

[0046] Clause 18. A semiconductor device according to any of the preceding clauses, wherein the upper source / drain and the lower source / drain may be offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0047] Clause 19. The semiconductor device according to any of the preceding clauses, wherein the upper active region may further include a plurality of upper nanosheets, and the lower active region may further include a plurality of lower nanosheets, wherein the plurality of upper nanosheets may be closer to the first front gate cleaved dielectric post than the plurality of lower nanosheets.

[0048] Clause 20. A semiconductor device according to any of the preceding clauses, wherein a plurality of upper nanosheets and a plurality of lower nanosheets may be offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0049] Clause 21. The semiconductor device according to any of the preceding clauses, wherein the semiconductor device may further include a first front dielectric pad extending along a first inner sidewall of a plurality of upper nanosheets and a second front dielectric pad extending along a second inner sidewall of a plurality of upper nanosheets. A front dielectric filler may be located between the first and second front dielectric pads.

[0050] Clause 22. A semiconductor device according to any of the preceding clauses, wherein the semiconductor device may further include a back-side gate-cut dielectric post that is in direct contact with the back side of a front-side dielectric filler. A first back-side dielectric pad and a second back-side dielectric pad may be disposed along the inner sidewall of the second back-side dielectric filler and the inner sidewall of the first back-side dielectric filler, respectively, wherein the first front-side dielectric pad and the second back-side dielectric pad are offset from each other across a plurality of upper transistors and a plurality of lower transistors, and wherein the second front-side dielectric pad and the first back-side dielectric pad are offset from each other across a plurality of upper transistors and a plurality of lower transistors.

[0051] Clause 23. A semiconductor device according to any of the preceding clauses, wherein the upper source / drain can directly contact the outer sidewall of the first front dielectric pad, and wherein the lower source / drain can directly contact the inner sidewall of the second back dielectric pad.

[0052] Clause 24. A semiconductor device comprising a plurality of nanodevices, the plurality of nanodevices including a plurality of upper transistors and a plurality of lower transistors, wherein the plurality of nanodevices includes upper active regions and lower active regions offset from each other across the plurality of upper and lower transistors, wherein the upper active regions include upper source / drain electrodes, and wherein the lower active regions include lower source / drain electrodes. Upper source / drain contacts and lower source / drain contacts are respectively connected to the upper source / drain and the lower source / drain. A first front-side gate-cut dielectric post and a second front-side gate-cut dielectric post are respectively adjacent to and parallel to the first and second nanodevices in the plurality of nanodevices along the x-axis, wherein the back surface of the first front-side gate-cut dielectric post and the back surface of the second front-side gate-cut dielectric post each extend a first width along the y-axis. The first back-side dielectric filler and the second back-side dielectric filler are in direct contact with the back-side surfaces of the first front-side gate-cut dielectric pillar and the second front-side gate-cut dielectric pillar, respectively. The front-side surfaces of the first and second back-side dielectric fillers each extend a second width along the y-axis, wherein the second width is greater than the first width.

[0053] Clause 25. A semiconductor device according to any of the preceding clauses, wherein an upper source / drain contact may extend downward from the back side of a plurality of nanodevices to connect to the back side of an upper source / drain, and wherein a lower source / drain contact may extend upward from the front side of a plurality of nanodevices to connect to the front side of a lower source / drain.

[0054] When a back-side power rail via (VBPR) extends downwards from the front contact, the via may be located between two active regions on a nanodevice. Scaling of stacked field-effect transistors (FETs) is limited by deep VBPR connections. Interleaved stacked FETs eliminate the need for deep VBPRs. However, in interleaved stacked FET arrangements, a bonding process flow is required, and for a contact polysilicon pitch of 45 nanometers (nm) and a contact size of approximately 12 nm, a 3-nanometer (nm) gate alignment misalignment results in approximately 25% contact area reduction. Therefore, using a bonding process flow to implement interleaved stacked FET solutions is not ideal.

[0055] By employing a monolithic process flow with a single gate pattern, the risk of gate alignment misalignment can be prevented. This invention does not require that all advantages be incorporated into every embodiment of the invention.

[0056] This invention aims to form an interleaved stacked FET, such that the active regions of the upper and lower transistors are offset from each other. This interleaved stacked FET is formed through a multi-stage process. The first stage forms a first trench by etching a portion of the gate, a self-aligned contact (SAC) capping layer, an interlayer dielectric (ILD), an upper source / drain, and an upper nanosheet; and forms second and third trenches by etching a portion of the SAC capping layer and the gate. The second stage forms a first front dielectric pad, a second front dielectric pad, and a front dielectric filler within the first trench, and fills the second and third trenches with dielectric material to form front gate-cut dielectric pillars through the gate and ILD. The third stage forms source / drain contacts along the inner sidewall of the first front dielectric pad within the ILD and dielectric filler. The fourth stage forms a fourth trench by etching a portion of the shallow trench isolation (STI) region, the ILD, and the gate; and forms the fifth and sixth trenches by etching portions of the gate, ILD, back-side ILD (BILD) layer, lower source / drain, lower nanosheet, bottom dielectric isolation (BDI) layer, and middle dielectric isolation (MDI) layer. The fifth stage fills the fourth trench with dielectric material to form a back-side gate-cut dielectric pillar through the gate and ILD. The fifth stage also forms a first back-side dielectric pad and a first back-side dielectric filler within the fifth trench, and a second back-side dielectric pad and a second back-side dielectric filler within the sixth trench. The sixth stage forms a back-side source / drain contact along the outer wall of the second back-side dielectric pad within the second back-side dielectric filler and the ILD.

[0057] Figure 1A top view of multiple nanodevices ND1, ND2 according to an embodiment of the present invention is shown. The devices, adjacent and parallel along the x-axis, include a first nanodevice ND1 and a second nanodevice ND2, each comprising a plurality of upper transistors and a plurality of lower transistors. Cross section X is a cross section perpendicular to the gate along the horizontal axis of the first nanodevice ND1. Cross section Y1 is a cross section parallel to the gate along the source / drain region 104 and spanning the multiple nanodevices ND1, ND2. Cross section Y2 is a cross section parallel to the gate along the gate region 102 and spanning the multiple nanodevices ND1, ND2. It is understood that embodiments of the present invention are not limited to nanodevices ND1, ND2, and other devices may be used, including but not limited to nanosheet transistors, FinFETs, nanowires, and planar devices.

[0058] Figures 2-4 The X, Y1, and Y2 cross sections of multiple nanodevices ND1 and ND2 are shown respectively after the following steps according to an embodiment of the present invention: deposition of interlayer dielectric (ILD) 170, formation of nanosheets 120, 125, 135, 140, and 145, formation of shallow trench isolation (STI) region 114, formation of gate 160, formation of gate spacer 150 and inner spacer 155, formation of bottom dielectric isolation (BDI) layer 115, formation of intermediate dielectric isolation (MDI) layer 130, formation of source / drain electrodes 165A, 165B, 165C, 165D, 165E, and 165F, formation of etch stop layer 110, formation of self-aligned contact (SAC) capping layer 175, and CMP. Multiple nanodevices ND1, ND2 include a substrate 105, an etch stop layer 110, a lower substrate layer 112, an STI region 114, a first lower nanosheet 120, a second lower nanosheet 125, a first upper nanosheet 135, a second upper nanosheet 140, and a third upper nanosheet 145. As used herein, the terms "upper" and "lower" refer to the orientation of the structure before wafer flipping. Therefore, the structure located above the MDI layer 130 before wafer flipping is referred to as "upper," and the structure located below the MDI layer 130 before wafer flipping is referred to as "lower." The substrate 105 and the etch stop layer 110 can be, for example, materials including but not limited to, silicon (Si), silicon germanium (SiGe), Si:C (carbon-doped silicon), carbon-doped silicon germanium (SiGe:C), III-V, II-V compound semiconductors, or other similar semiconductors. Furthermore, multilayer semiconductor materials can be used as the semiconductor material for the substrate 105. In some embodiments, the substrate 105 includes both a semiconductor material and a dielectric material. The semiconductor substrate 105 may also include organic semiconductors or layered semiconductors, such as Si / SiGe, silicon-on-insulator, or SiGe-on-insulator. A portion or all of the semiconductor substrate 105 may also be amorphous, polycrystalline, or single-crystal. The semiconductor substrate 105 and the etch stop layer 110 may be doped, undoped, or contain both doped and undoped regions.

[0059] A first sacrificial layer (not shown) is formed directly on the lower substrate layer 112. A second sacrificial layer (not shown) is formed directly on the first sacrificial layer (not shown). A first lower nanosheet 120 is formed directly on the second sacrificial layer (not shown). A third sacrificial layer (not shown) is formed directly on the first lower nanosheet 120. A second lower nanosheet 125 is formed directly on the third sacrificial layer (not shown). A fourth sacrificial layer (not shown) is formed directly on the second lower nanosheet 125. An MDI layer 130 is formed directly on the fourth sacrificial layer (not shown). A fifth sacrificial layer (not shown) is formed directly on the MDI layer 130. A first upper nanosheet 135 is formed directly on the fifth sacrificial layer (not shown). A sixth sacrificial layer (not shown) is formed directly on the first upper nanosheet 135. A second upper nanosheet 140 is formed directly on the sixth sacrificial layer (not shown). A seventh sacrificial layer (not shown) is formed directly on the second upper nanosheet 140. A third upper nanosheet 145 is formed directly on the seventh sacrificial layer (not shown). The first sacrificial layer (not shown), the second sacrificial layer (not shown), the third sacrificial layer (not shown), the fourth sacrificial layer (not shown), the fifth sacrificial layer (not shown), the sixth sacrificial layer (not shown), and the seventh sacrificial layer (not shown) are collectively referred to below as a plurality of sacrificial layers (not shown). Furthermore, the first lower nanosheet 120 and the second lower nanosheet 125 are collectively referred to below as a plurality of lower nanosheets 120, 125, and the first upper nanosheet 135, the second upper nanosheet 140, and the third upper nanosheet 145 are collectively referred to below as a plurality of upper nanosheets 135, 140, 145. The plurality of sacrificial layers (not shown) may be composed, for example, SiGe with a Ge content of approximately 35%. The plurality of lower nanosheets 120, 125 and the plurality of upper nanosheets 135, 140, 145 may be composed, for example, Si. The number of nanosheets and the number of sacrificial layers described above are not intended to be limiting, and it is understood that the number of nanosheets and the number of sacrificial layers may vary in embodiments of the invention. After forming multiple lower nanosheets 120, 125, multiple upper nanosheets 135, 140, 145, and multiple sacrificial layers (not shown) (i.e., after forming the nanosheet stack), the nanosheet stack (including alternating Si and SiGe layers) can be further patterned using conventional photolithography and etching processes. After the nanosheet stack is formed and patterned, the STI region 114 is formed by dielectric filling, CMP, and dielectric etching.

[0060] A dummy gate material is deposited and then patterned to form a dummy gate (not shown), followed by conformal dielectric pad deposition and anisotropic etching to form gate spacers 150 and a BDI layer 115. The BDI layer 115 is directly above the underlying substrate layer 112. The nanosheet stack at the S / D region 104 is then etched, followed by recess etching of the sacrificial layer (not shown) to form internal spacers 155. Next, a first upper source / drain 165A, a second upper source / drain 165B, a first lower source / drain 165C, a second lower source / drain 165D, a third upper source / drain 165E, and a third lower source / drain 165F are epitaxially grown on the exposed sidewalls of multiple lower nanosheets 120, 125 and multiple upper nanosheets 135, 140, 145. An ILD layer 170 is then deposited, and CMP is performed to remove the dummy gate hard mask (not shown). The sacrificial layer (not shown) is then removed, and the gate 160 is subsequently formed. The first lower source / drain 165C, the second lower source / drain 165D, and the third lower source / drain 165F are formed directly on the BDI layer 115. The first upper source / drain 165A (i.e., the upper source / drain in the claim), the second upper source / drain 165B, and the third upper source / drain 165E are respectively formed in the ILD 170 above the first lower source / drain 165C (i.e., the lower source / drain in the claim), the second lower source / drain 165D, and the third lower source / drain 165F.

[0061] The first upper source / drain 165A, the second upper source / drain 165B, the first lower source / drain 165C, the second lower source / drain 165D, the third upper source / drain 165E, and the third lower source / drain 165F can be, for example, n-type epitaxy or p-type epitaxy. For n-type epitaxy, an n-type dopant selected from the phosphorus (P), arsenic (As), and / or antimony (Sb) group can be used. For p-type epitaxy, a p-type dopant selected from the boron (B), gallium (Ga), indium (In), and / or thallium (Tl) group can be used. Other doping techniques can also be used, such as ion implantation, vapor phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, and / or any suitable combination of these techniques. In some embodiments, the dopant is activated by thermal annealing (such as laser annealing, flash annealing, rapid thermal annealing (RTA), or any suitable combination of these techniques).

[0062] exist Figure 2In this configuration, the ILD 170 is directly formed over the first upper source / drain 165A, the second upper source / drain 165B, the first lower source / drain 165C, and the second lower source / drain 165D, and surrounds one side of the gate spacer 150, the MDI layer 130, and a portion of the internal spacer 155. Figure 3 In this process, the ILD 170 is directly formed on the first upper source / drain 165A, the first lower source / drain 165C, the third upper source / drain 165E, the third lower source / drain 165F, and the STI region 114.

[0063] exist Figure 2 In this configuration, gate material is deposited in a space formed by removing multiple sacrificial layers (not shown) and directly deposited on the third upper nanosheet 145 to form a replacement gate (i.e., gate 160). Figure 4 In this configuration, gate material is deposited in a space formed by removing multiple sacrificial layers (not shown) and directly deposited on the third upper nanosheet 145 and the STI region 114 to form gate 160. Gate 160 may include, for example, a gate dielectric pad (such as a high-k dielectric, such as HfO2, ZrO2, HfLaOx, etc.), a work function layer (such as TiN, TiAlC, TiC, etc.), and a conductive metal filler (such as W). Figure 2 and Figure 4 In this process, dielectric material is deposited directly on the gate 160 to form the SAC capping layer 175.

[0064] Figure 5 A top view of a plurality of nanodevices ND1, ND2 after the formation of a first trench 180, a second trench 182 and a third trench 184, is shown according to an embodiment of the present invention. Figure 5 This is intended to illustrate the effect of gate region 102 ( Figure 1 In the process, the cutting (i.e., the first trench 180, the second trench 182 and the third trench 184) is performed between the first nanodevice ND1 and the second nanodevice ND2, and at the unit boundary between the first nanodevice ND1 and the second nanodevice ND2.

[0065] Figures 6-8 Cross-sections of multiple nanodevices ND1, ND2, and ND2 after the formation of the first trench 180, the second trench 182, and the third trench 184, according to embodiments of the present invention, are shown respectively. Figure 6In this structure, the first upper source / drain 165A, the second upper source / drain 165B, the SAC capping layer 175, multiple upper nanosheets 135, 140, 145, and portions of the ILD 170 and gate 160 are etched, for example, by RIE to form a first trench 180. The bottom surface of the first trench 180 exposes the top surface of the ILD 170 and the MDI layer 130. Figure 7 In this process, portions of ILD 170, the first upper source / drain 165A, and the third upper source / drain 165E are etched, for example, by RIE to form a first trench 180. The bottom surface of the first trench 180 exposes a portion of the top surface of ILD 170. Different portions of ILD 170 are etched, for example, by RIE to form a second trench 182 and a third trench 184. The bottom surfaces of the second trench 182 and the third trench 184 expose different portions of the top surface of ILD 170. Figure 8 In this process, portions of the SAC capping layer 175, the gate 160, and multiple upper nanosheets 135, 140, 145 are etched, for example, by RIE to form a first trench 180. The bottom surface of the first trench 180 exposes portions of the top surfaces of the gate 160 and the MDI layer 130. Different portions of the SAC capping layer 175 and the gate 160 are etched, for example, by RIE to form a second trench 182 and a third trench 184. The bottom surfaces of the second trench 182 and the third trench 184 expose different portions of the top surface of the gate 160.

[0066] Figure 9 A top view of a plurality of nanodevices ND1, ND2 after forming a first front gate diced dielectric post 190, a second front gate diced dielectric post 195, a first front dielectric pad 192, a second front dielectric pad 194, and a front dielectric filler 200, is shown according to an embodiment of the present invention. Figure 9 Intended to illustrate gate region 102 ( Figure 1 The cuts in the front gate diced dielectric pillar 190, the second front gate diced dielectric pillar 195, the first front dielectric pad 192, the second front dielectric pad 194, and the front dielectric filler 200 are filled. The first front gate diced dielectric pillar 190 is adjacent to and parallel to the first nanodevice ND1 along the x-axis. The second front gate diced dielectric pillar 195 is adjacent to and parallel to the second nanodevice ND2 along the x-axis.

[0067] Figures 10-12Cross-sections of multiple nanodevices ND1, ND2, after the formation of a first front-side gate diced dielectric pillar 190, a second front-side gate diced dielectric pillar 195, a first front-side dielectric pad 192, a second front-side dielectric pad 194, and a front-side dielectric filler 200, are shown respectively according to an embodiment of the present invention. Pad material is deposited in a first trench 180 and etched back to form the first front-side dielectric pad 192 and the second front-side dielectric pad 194 located on the sidewalls of the first trench 180. Pad material is also deposited in the second trench 182 and the third trench 184 to form the first front-side gate diced dielectric pillar 190 and the second front-side gate diced dielectric pillar 195, respectively. The pad material may be composed of, for example, SiN, SiBCN, SiOCN, SiOC, or SiC. Figure 10 In this process, a portion of the first front-side dielectric pad 192 is selectively removed, for example, by a RIE. Figure 11 In this process, the top surface of the ILD 170 is exposed by selectively removing portions of the first front gate cut dielectric post 190, the second front gate cut dielectric post 195, the first front dielectric pad 192, and the second front dielectric pad 194, for example, via a RIE. Figure 12 In this process, portions of the first front gate cleaved dielectric pillar 190, the second front gate cleaved dielectric pillar 195, the first front dielectric pad 192, and the second front dielectric pad 194 are selectively removed, for example, by a re-embedded electrode array (RIE), to expose the top surface of the SAC capping layer 175. Then, a dielectric filler material is deposited in the first trench 180 to form a front dielectric filler 200 located between the first front dielectric pad 192 and the second front dielectric pad 194. The front dielectric filler 200 may be composed of, for example, SiO2. Figure 15 In the middle, the first front dielectric pad 192 extends along the first inner sidewall of the plurality of upper nanosheets 135, 140, 145. The second front dielectric pad 194 extends along the second inner sidewall of the plurality of upper nanosheets 135, 140, 145.

[0068] Figures 13-15 Cross-sections of multiple nanodevices ND1, ND2, respectively, after the formation of lower source / drain contacts 215, source / drain contacts 220, multiple gate contacts 225A, 225B, back-end process (BEOL) layer 205, and bonding to carrier wafer 210, are shown according to embodiments of the present invention. Multiple trenches (not shown) formed during mid-end process (MOL) patterning are filled with conductive metals (e.g., including silicide pads such as Ni, Ti, NiPt; adhesion metal pads such as TiN; and conductive metal fillers such as W, Co, or Ru) to form the lower source / drain contacts 215, source / drain contacts 220, and multiple gate contacts 225A, 225B. Figure 14In the middle, the lower source / drain contact 215 is directly located above the first lower source / drain 165C. The source / drain contact 220 is directly located above the third upper source / drain 165E. Figure 15 In this configuration, the first gate contact 225A is located directly above the gate 160 between the first front-side gate diced dielectric post 190 and the SAC capping layer 175. The second gate contact 225B is located directly above the gate 160 between the second front-side gate diced dielectric post 195 and the SAC capping layer 175. The BEOL layer 205 may include multiple metal layers and vias between them. Figure 13 In this configuration, the BEOL layer 205 is formed directly on top of the first front dielectric pad 192. Figure 14 In this configuration, the BEOL layer 205 is directly formed over the first front-side gate-cut dielectric pillar 190, the second front-side gate-cut dielectric pillar 195, the first front-side dielectric pad 192, the second front-side dielectric pad 194, the front-side dielectric filler 200, the ILD 170, the lower source / drain contact 215, and the source / drain contact 220. Figure 15 In this configuration, the BEOL layer 205 is directly formed over the first front gate diced dielectric pillar 190, the second front gate diced dielectric pillar 195, the SAC capping layer 175, the first gate contact 225A, the second gate contact 225B, the gate 160, the first front dielectric pad 192, the second front dielectric pad 194, and the front dielectric filler 200. Figures 13-15 In this process, the carrier wafer 210 is directly formed on the BEOL layer 205 through a bonding process (e.g., oxide-oxide bonding).

[0069] Figures 1-15 The processing technology of the front side of substrate 105 is shown, while Figures 16-33 The back-side processing of substrate 105 is shown. Figures 16-18 Cross-sections of multiple nanodevices ND1, ND2, respectively, after the carrier wafer 210 is flipped and the substrate 105 is removed, according to an embodiment of the present invention, are shown. The carrier wafer 210 is flipped and becomes a handler wafer. The substrate 105 is removed by a combination of processes such as wafer grinding, CMP, and / or selective dry / wet etching, and stops on the etch stop layer 110.

[0070] Figures 19-21 The X, Y1, and Y2 cross sections of a plurality of nanodevices ND1, ND2 after the etch stop layer 110 and the lower substrate layer 112 have been removed, according to an embodiment of the present invention. The etch stop layer 110 is removed to expose the lower substrate layer 112. The lower substrate layer 112 is removed by, for example, a selective wet or dry etching process.

[0071] Figures 22-24 Cross-sections of multiple nanodevices ND1, ND2, after deposition of a back-side ILD (BILD) layer 230 and CMP, according to an embodiment of the present invention, are shown in X, Y1, and Y2. The BILD layer 230 can be made of, for example, SiC or SiOC. Figure 22 In this process, BILD layer 230 is deposited directly on top of BDI layer 115. Figures 23-24 In this process, BILD layer 230 is deposited directly on top of BDI layer 115. Figures 22-24 In this process, a portion of the BILD layer 230 is selectively removed, for example, by CMP.

[0072] Figures 25-27 The X, Y1, and Y2 cross sections of multiple nanodevices ND1, ND2 after the formation of the fourth trench 235, the fifth trench 237, and the sixth trench 239, according to embodiments of the present invention, are shown respectively. Figure 26 In the middle, portions of ILD 170 and STI region 114 are etched, for example, by RIE, to form the fourth trench 235. Figure 27 In this process, a portion of the gate 160 and the STI region 114 are etched, for example, by RIE, to form a fourth trench 235. Figures 26-27 In this case, the bottom surface of the fourth trench 235 exposes a portion of the top surface of the front dielectric filler 200. Figure 26 In this process, a portion of ILD 170, BILD layer 230, STI region 114, BDI layer 115, and the third lower source / drain 165F are etched, for example, by RIE, to form a fifth trench 237. The bottom surface of the fifth trench 237 exposes the top surface of the second front-side gate diced dielectric pillar 195 and a portion of the top surface of ILD 170. A portion of ILD 170, BILD layer 230, STI region 114, BDI layer 115, and the first lower source / drain 165C are etched, for example, by RIE, to form a sixth trench 239. The bottom surface of the sixth trench 239 exposes the top surface of the first front-side gate diced dielectric pillar 190 and a portion of the top surface of ILD 170. Figure 27In this process, a portion of the BILD layer 230, STI region 114, BDI layer 115, MDI layer 130, and gate 160 are etched, for example, by RIE, to form a fifth trench 237. The bottom surface of the fifth trench 237 exposes a portion of the top surface of the second front-side gate diced dielectric pillar 195 and the top surface of the gate 160. A portion of the BILD layer 230, STI region 114, BDI layer 115, MDI layer 130, and gate 160 are etched, for example, by RIE, to form a sixth trench 239. The bottom surface of the sixth trench 239 exposes a portion of the top surface of the first front-side gate diced dielectric pillar 190 and the top surface of the gate 160.

[0073] Figures 28-30 Cross-sections of multiple nanodevices ND1, ND2, after the formation of a back-side gate-cut dielectric pillar 250, a first back-side dielectric pad 242, a second back-side dielectric pad 244, a first back-side dielectric filler 240, and a second back-side dielectric filler 245, according to embodiments of the present invention, are shown in X, Y1, and Y2. Pad material is deposited in a fourth trench 235 to form the back-side gate-cut dielectric pillar 250. The back-side gate-cut dielectric pillar 250 is in direct contact with the back side of the front-side dielectric filler 200. Pad material is also deposited in a fifth trench 237 and a sixth trench 239, and etched back to form the first back-side dielectric pad 242 and the second back-side dielectric pad 244, respectively. The first back-side dielectric pad 242 and the second back-side dielectric pad 244 are located on the inner sidewalls of the fifth trench 237 and the sixth trench 239, respectively. The pad material can be made of, for example, SiN. Figures 29-30 In this process, a portion of the back-side gate-cut dielectric pillar 250, the first back-side dielectric pad 242, and the second back-side dielectric pad 244 are selectively removed, for example, by a RIE (Reverse Engineering Interchange) to expose the top surface of the BILD layer 230 and the STI region 114. Dielectric filler material is then deposited in the fifth trench 237 and the sixth trench 239 to form the first back-side dielectric filler 240 (i.e., the second back-side dielectric filler in the claim) and the second back-side dielectric filler 245 (i.e., the first back-side dielectric filler in the claim), respectively. The first back-side dielectric pad 242 and the second back-side dielectric pad 244 are disposed along the inner sidewalls of the first back-side dielectric filler 240 and the second back-side dielectric filler 245, respectively. The first front-side dielectric pad 192 and the second back-side dielectric pad 244 are offset from each other across a plurality of upper transistors and a plurality of lower transistors. The second front dielectric pad 194 and the first back dielectric pad 242 are offset from each other across a plurality of upper transistors and a plurality of lower transistors. The first back dielectric filler 240 and the second back dielectric filler 245 may be made of, for example, SiO2.

[0074] Therefore, the first front-side dielectric pad 192, the second front-side dielectric pad 194, the first front-side gate-cut dielectric post 190, the second front-side gate-cut dielectric post 195, and the back-side gate-cut dielectric post 250 are made of the same dielectric material. The first back-side dielectric filler 240, the second back-side dielectric filler 245, and the front-side dielectric filler 200 are made of different dielectric materials. Figure 30 In the middle, the first back-side dielectric pad 242 extends along the first outer sidewalls of the plurality of lower nanosheets 120, 125, the first outer sidewall of the BDI layer 115, and the first outer sidewall of the MDI layer 130. The second back-side dielectric pad 244 extends along the second outer sidewalls of the plurality of lower nanosheets 120, 125, the second outer sidewall of the BDI layer 115, and the second outer sidewall of the MDI layer 130.

[0075] Figures 31-33 Cross-sections of multiple nanodevices ND1, ND2 after the formation of multiple back-side source / drain contacts 250A, 250B, upper source / drain contact 260, and back-side power transmission network (BSPDN) 255, according to embodiments of the present invention, are shown in X, Y1, and Y2. Multiple trenches (not shown) formed during back-end process (BEOL) patterning are filled with conductive metals (e.g., including silicide pads such as Ni, Ti, NiPt; adherent metal pads such as TiN; and conductive metal fillers such as W, Co, or Ru) to form the multiple back-side source / drain contacts 250A, 250B, and upper source / drain contact 260. Figure 31 In the middle, the first back-side source / drain contact 250A is directly located above the second lower source / drain contact 165D. Figure 32 In this configuration, the second back-side source / drain contact 250B is directly located above the third lower source / drain 165F. The upper source / drain contact 260 extends downward from the back side of the plurality of nanodevices ND1, ND2 to connect to the back side of the first upper source / drain 165A. The lower source / drain contact 215 extends upward from the front side of the plurality of nanodevices ND1, ND2 to connect to the front side of the first lower source / drain 165C. Figure 31 In this configuration, the BSPDN 255 is formed directly on the BILD layer 230 and the first back-side source / drain contact 250A. Figure 32 In this configuration, the BSPDN 255 is directly formed on the back-side gate-cut dielectric pillar 250, the BILD layer 230, the first back-side dielectric filler 240, the second back-side dielectric filler 245, the first back-side dielectric pad 242, the second back-side dielectric pad 244, the STI region 114, the second back-side source / drain contact 250B, and the upper source / drain contact 260. Figure 33In this process, the BSPDN 255 is directly formed on the back gate diced dielectric pillar 250, the BILD layer 230, the first back dielectric filler 240, the second back dielectric filler 245, the first back dielectric pad 242, the second back dielectric pad 244, and the STI region 114.

[0076] exist Figures 31-33 In this design, multiple nanodevices include upper and lower active regions offset from each other across multiple upper and lower transistors. The upper active region includes multiple upper nanosheets 135, 140, 145, a first upper source / drain 165A, a second upper source / drain 165B, and a third upper source / drain 165E. The lower active region includes multiple lower nanosheets 120, 125, a first lower source / drain 165C, a second lower source / drain 165D, and a third lower source / drain 165F. The upper nanosheets 135, 140, 145 are closer to the first front-side gate-cut dielectric pillar 190 than the lower nanosheets 120, 125. The upper nanosheets 135, 140, 145 and the lower nanosheets 120, 125 are offset from each other across the multiple upper and lower transistors. The first upper source / drain 165A and the first lower source / drain 165C are offset from each other across multiple upper transistors and multiple lower transistors. The first upper source / drain 165A is in direct contact with the outer sidewall of the first front dielectric pad 192. The first lower source / drain 165C is in direct contact with the inner sidewall of the second back dielectric pad 244.

[0077] The back surface of the first front gate diced dielectric post 190 extends along the y-axis with a first width W1. The back surface of the second front gate diced dielectric post 195 also extends along the y-axis with a first width W1. The second back dielectric filler 245 is in direct contact with the back surface of the first front gate diced dielectric post 190. The first back dielectric filler 240 is in direct contact with the back surface of the second front gate diced dielectric post 195. The front surfaces of the first back dielectric filler 240 and the second back dielectric filler 245 each extend along the y-axis with a second width W2. The second width W2 is greater than the first width W1.

[0078] The first front-side gate-cut dielectric pillar 190 and the back-side gate-cut dielectric pillar 250 are offset from each other across multiple upper transistors and multiple lower transistors. The second front-side gate-cut dielectric pillar 195 and the back-side gate-cut dielectric pillar 250 are also offset from each other across multiple upper transistors and multiple lower transistors. The front-side dielectric filler 200 and the first back-side dielectric filler 240 are offset from each other across multiple upper transistors and multiple lower transistors. The front-side dielectric filler 200 and the second back-side dielectric filler 245 are also offset from each other across multiple upper transistors and multiple lower transistors. The back-side surface of the front-side dielectric filler 200 extends a third width W3 along the y-axis. The front-side surface of the back-side gate-cut dielectric pillar 250 extends a fourth width W4 along the y-axis. The third width W3 is greater than the fourth width W4.

[0079] Multiple nanodevices ND1 and ND2 include upper and lower active regions offset from each other across multiple upper and lower transistors. The back surface of a first front-side gate-cut dielectric post 190 extends along the y-axis with a first width W1. The front surface of a second back-side dielectric filler 245 extends along the y-axis with a second width W2. The second width W2 is greater than the first width W1. The first front-side gate-cut dielectric post 190 and the second back-side dielectric filler 245 are made of different dielectric materials.

[0080] Understandable, Figures 1-33 This is merely an illustration of one implementation and does not imply any limitation on how different embodiments can be implemented. Many modifications can be made to the depicted environment based on design and implementation requirements.

[0081] The description of various embodiments of the invention is presented for illustrative purposes and is not intended to be exhaustive or to limit the invention to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is for the purpose of best explaining the principles of the embodiments, their practical application, or improvements to the prior art, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor device, comprising: Multiple nanodevices, the multiple nanodevices including multiple upper transistors and multiple lower transistors, wherein the multiple nanodevices include upper active regions and lower active regions offset from each other across the multiple upper transistors and the multiple lower transistors; A first front-side gate-cut dielectric post, the first front-side gate-cut dielectric post being adjacent to and parallel to a first nanodevice among the plurality of nanodevices along the x-axis, wherein the back surface of the first front-side gate-cut dielectric post extends a first width along the y-axis; and A first back-side dielectric filler is in direct contact with the back surface of the first front-side gate-cut dielectric post, wherein the front surface of the first back-side dielectric filler extends a second width along the y-axis, and wherein the second width is greater than the first width.

2. The semiconductor device of claim 1, wherein the upper active region comprises a plurality of upper nanosheets, and the lower active region comprises a plurality of lower nanosheets, wherein the plurality of upper nanosheets are closer to the first front gate cleaved dielectric post than the plurality of lower nanosheets.

3. The semiconductor device of claim 2, wherein the plurality of upper nanosheets and the plurality of lower nanosheets are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

4. The semiconductor device according to claim 3, further comprising: A first front dielectric pad and a second front dielectric pad, wherein the first front dielectric pad extends along the first inner sidewall of the plurality of upper nanosheets, and the second front dielectric pad extends along the second inner sidewall of the plurality of upper nanosheets; as well as A front dielectric filler is located between the first front dielectric pad and the second front dielectric pad.

5. The semiconductor device according to claim 4, further comprising: A back-side gate-cut dielectric post is provided, which is in direct contact with the back surface of the front-side dielectric filler.

6. The semiconductor device of claim 5, wherein the first front dielectric pad, the second front dielectric pad, the first front gate-cut dielectric post, and the back gate-cut dielectric post are made of the same dielectric material, and wherein the first back dielectric filler and the front dielectric filler are made of different dielectric materials.

7. The semiconductor device of claim 6, wherein the first front gate dicing dielectric post and the back gate dicing dielectric post are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

8. The semiconductor device of claim 7, wherein the back surface of the front dielectric filler extends a third width along the y-axis, wherein the front surface of the back gate diced dielectric post extends a fourth width along the y-axis, and wherein the third width is greater than the fourth width.

9. The semiconductor device according to claim 1, comprising: A second front-side gate-cut dielectric post, the second front-side gate-cut dielectric post being adjacent to and parallel to a second nanodevice among the plurality of nanodevices along the x-axis, wherein the back surface of the second front-side gate-cut dielectric post extends the first width along the y-axis; and A second back-side dielectric filler is in direct contact with the back surface of the second front-side gate-cut dielectric post, wherein the front surface of the second back-side dielectric filler extends the second width along the y-axis.

10. The semiconductor device of claim 9, wherein the upper active region comprises a plurality of upper nanosheets and the lower active region comprises a plurality of lower nanosheets, wherein the plurality of upper nanosheets are closer to the first front gate cleaved dielectric post than the plurality of lower nanosheets.

11. The semiconductor device of claim 10, wherein the plurality of upper nanosheets and the plurality of lower nanosheets are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

12. The semiconductor device of claim 11, further comprising: A first front dielectric pad and a second front dielectric pad, wherein the first front dielectric pad extends along the first inner sidewall of the plurality of upper nanosheets, and the second front dielectric pad extends along the second inner sidewall of the plurality of upper nanosheets; as well as A front dielectric filler is located between the first front dielectric pad and the second front dielectric pad.

13. The semiconductor device of claim 12, further comprising: A back-side gate-cut dielectric post is provided, which is in direct contact with the back surface of the front-side dielectric filler. as well as A first back-side dielectric pad and a second back-side dielectric pad are located along the inner sidewall of the second back-side dielectric filler and the inner sidewall of the first back-side dielectric filler, respectively. The first front-side dielectric pad and the second back-side dielectric pad are offset from each other across the plurality of upper transistors and the plurality of lower transistors, and the second front-side dielectric pad and the first back-side dielectric pad are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

14. The semiconductor device of claim 13, wherein the first front-side dielectric pad, the second front-side dielectric pad, the first front-side gate-cut dielectric post, the second front-side gate-cut dielectric post, the first back-side gate-cut dielectric post, the second back-side gate-cut dielectric post, and the back-side gate-cut dielectric post are made of the same dielectric material, and wherein the first back-side dielectric filler, the second back-side dielectric filler, and the front-side dielectric filler are made of different dielectric materials.

15. The semiconductor device of claim 14, wherein the front dielectric filler and the first back dielectric filler are offset from each other across the plurality of upper transistors and the plurality of lower transistors, and wherein the front dielectric filler and the second back dielectric filler are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

16. The semiconductor device of claim 15, wherein the first front-side gate-cut dielectric post and the back-side gate-cut dielectric post are offset from each other across the plurality of upper transistors and the plurality of lower transistors, and wherein the second front-side gate-cut dielectric post and the back-side gate-cut dielectric post are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

17. The semiconductor device of claim 9, wherein the upper active region includes an upper source / drain, and wherein the lower active region includes a lower source / drain.

18. The semiconductor device of claim 17, wherein the upper source / drain and the lower source / drain are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

19. The semiconductor device of claim 18, wherein the upper active region further comprises a plurality of upper nanosheets, and the lower active region further comprises a plurality of lower nanosheets, wherein the plurality of upper nanosheets are closer to the first front gate cleaved dielectric post than the plurality of lower nanosheets.

20. The semiconductor device of claim 19, wherein the plurality of upper nanosheets and the plurality of lower nanosheets are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

21. The semiconductor device of claim 20, further comprising: A first front dielectric pad and a second front dielectric pad, wherein the first front dielectric pad extends along the first inner sidewall of the plurality of upper nanosheets, and the second front dielectric pad extends along the second inner sidewall of the plurality of upper nanosheets; as well as A front dielectric filler is located between the first front dielectric pad and the second front dielectric pad.

22. The semiconductor device of claim 21, further comprising: A back-side gate-cut dielectric post is provided, which is in direct contact with the back surface of the front-side dielectric filler. as well as A first back-side dielectric pad and a second back-side dielectric pad are located along the inner sidewall of the second back-side dielectric filler and the inner sidewall of the first back-side dielectric filler, respectively. The first front-side dielectric pad and the second back-side dielectric pad are offset from each other across the plurality of upper transistors and the plurality of lower transistors, and the second front-side dielectric pad and the first back-side dielectric pad are offset from each other across the plurality of upper transistors and the plurality of lower transistors.

23. The semiconductor device of claim 22, wherein the upper source / drain is in direct contact with the outer sidewall of the first front dielectric pad, and wherein the lower source / drain is in direct contact with the inner sidewall of the second back dielectric pad.

24. The semiconductor device according to claim 9, wherein: The upper active region includes an upper source / drain, and the lower active region includes a lower source / drain; and The semiconductor device includes an upper source / drain contact and a lower source / drain contact respectively connected to the upper source / drain and the lower source / drain.

25. The semiconductor device of claim 24, wherein the upper source / drain contact extends downward from the back side of the plurality of nanodevices to connect to the back side of the upper source / drain, and wherein the lower source / drain contact extends upward from the front side of the plurality of nanodevices to connect to the front side of the lower source / drain.

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