100 results about "Impact ionization" patented technology

The invention relates to a method and system for extracting a flicker noise model of a high-voltage MOS device, and the method comprises the steps: designing high-voltage MOS devices of different sizes, and carrying out the measurement to obtain the DC characteristic data of each device in an operable voltage range and the flicker noise characteristic data of each device under different bias voltage conditions; based on the direct-current characteristic data, performing model fitting on the direct-current performance of the high-voltage MOS device to obtain a direct-current characteristic model, the direct-current characteristic model comprising an intrinsic current part and a collision ionization current part; and based on the direct current characteristic model and the flicker noise characteristic data, carrying out model fitting on flicker noise brought by the intrinsic current part and flicker noise brought by the collision ionization current part to obtain a flicker noise model. By fitting the noise source model associated with the magnitude of the collision ionization current, the flicker noise characteristics of the collision ionization current part are subjected to function characterization, and the flicker noise characteristic characterization precision of the high-voltage MOS device under high-voltage bias is improved.

A memory device according to the present invention includes memory cells, each of the memory cells includes a semiconductor base material that is formed on a substrate and that stands on the substrate in a vertical direction, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform an erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first gate conductor layer partially surrounds a side surface of the semiconductor base material, and the second gate conductor layer entirely surrounds the side surface of the semiconductor base material.

The present invention proposes a single-particle burnout simulation method, comprising: obtaining a preset impact ionization coefficient, lattice temperature, electric field strength, and current density parameters for particle impact; determining the impact ionization parameters based on the impact ionization coefficient and the lattice temperature; determining the electron ionization parameters and the hole ionization parameters based on the impact ionization parameters and the electric field strength; and simulating the localized electron-hole pair generation rate based on the electron ionization parameters, the hole ionization parameters, the current density parameters, and a preset electron-hole pair localized generation rate model. The present invention has the beneficial effect of simulating the electron-hole pair generation rate during single-particle impact, thereby achieving the impact ionization generated when a single-particle effect occurs in a simulated device, thereby simulating the single-particle burnout caused by a single high-energy particle incident on a semiconductor device.

A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and to input page data for the page write operation to a sense amplifier circuit during the page erase operation.

The invention relates to a high-responsivity infrared detector chip structure, and relates to the field of semiconductor infrared detectors. Comprising a narrow-band gap absorption layer which is used for generating photon-generated carriers through light absorption; the medium-band-gap charge control layer is located between the narrow-band-gap absorption layer and the wide-band-gap collision ionization multiplication layer and used for limiting a built-in electric field to be only located in the wide-band-gap collision ionization multiplication layer and preventing the electric field from extending to the narrow-band-gap absorption layer; and the wide-band-gap collision ionization multiplication layer is separated from the narrow-band-gap absorption layer and is used for realizing collision ionization multiplication in a high electric field and amplifying light current. By separating the narrow-band-gap absorption layer from the wide-band-gap collision ionization multiplication layer and introducing the medium-band-gap charge control layer, balance between high gain and low dark current is realized.

The invention is suitable for the technical field of heat treatment, and provides a metal deep ion nitriding heat treatment process which comprises the following steps: (a) preparing a quantum dot catalyst layer; (b) acoustic resonance plasma treatment; (c) magnetic field enhanced diffusion; (d) carrying out grain boundary passivation treatment; according to the preparation method, Fe3O4 (at) Gd quantum dots are deposited on a nanocrystallization surface, an electron conduction channel is provided by utilizing a Fe3O4 carrier, N2 molecules are captured by Gd < 3 + > through physical adsorption, unpaired electrons are injected into a pi orbit of the N2 molecules, so that N is equivalent to N bond energy is reduced, and the layer permeation time is shortened; the plasma sheath oscillation frequency is matched with the inherent frequency of the workpiece, acoustic resonance is excited, and the plasma penetration depth is increased; plasma forms a standing wave field on the surface of a workpiece, and the uniformity deviation of an infiltrated layer is reduced. The strong magnetic field perpendicular to the electric field is applied, so that electrons do spiral motion, the collision ionization probability is increased, and the deep nitrogen concentration is improved; through reaction of terbium steam and grain boundary impurities, a brittleness source is eliminated, and the impact toughness is improved.

The invention relates to the technical field of semiconductor manufacturing, and provides a SiGe HBT breakdown voltage simulation method, device, equipment and medium, and the method comprises the steps: building a structure model according to the actual structure parameters of a SiGe HBT; obtaining a quantitative relation between a carrier ionization coefficient and electric field intensity based on an impact ionization model, and constructing a physical model according to the carrier ionization coefficient; carrying out temperature correction on the carrier ionization coefficient according to a preset standard parameter value; and based on the structure model and the physical model, carrying out breakdown voltage simulation according to a preset bias, and generating a breakdown curve of the SiGe HBT. According to the method, the problems of poor simulation adaptability, insufficient temperature adaptability and high optimization cost of the SiGe HBT breakdown voltage in the prior art are solved, electric field distribution, carrier transport and collision ionization processes in a device are accurately analyzed before actual tape-out, and a reliable simulation tool is provided for balancing the tradeoff contradiction between the SiGe HBT high-frequency performance and the breakdown voltage.

A groove is formed in a first semiconductor layer 1, a sidewall of the groove is coated with a first insulating film 2, a first impurity layer 3 and a second impurity layer 4 thereon are disposed in the groove, a second semiconductor layer 7 is disposed on the second impurity layer, a first semiconductor is disposed at the other part, an n+ layer 6a and an n+ layer 6c are positioned at respective ends of the second semiconductor layer 7 and connected to a source line SL and a bit line BL, respectively, a first gate insulating layer 8 is formed on the second semiconductor layer 7, and a first gate conductor layer 9 is connected to a word line WL. Voltage applied to the source line SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region 12 of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes from the channel region 12.

Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.

An atmospheric pressure electron impact ionization mass spectrometer system includes an atmospheric pressure ionization component operated at an atmospheric pressure. An electron impact ionization mass spectrometer includes an electron ionization source. An atmospheric pressure interface operates below about 10 Torr. The atmospheric pressure interface includes a source block to focus a plurality of molecules and ions from the atmospheric pressure ionization component at the atmospheric pressure into the electron ionization source which operates at a pressure below about 10-3 Torr.

A memory device includes pages each constituted by a plurality of memory cells arranged in columns on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each page are controlled to perform a page write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the semiconductor body and further lowering a voltage of the semiconductor body with capacitive coupling with the first gate conductor layer and with the second gate conductor layer, and in the page erase operation, at least two or more pages are simultaneously selected from among the pages and the page erase operation is performed.

A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.

The invention discloses a laterally diffused metal oxide semiconductor device and a manufacturing method thereof, the device comprises a plurality of cells, each cell comprises a substrate, a drift region located in the substrate, N body regions, a source region, a drain region, a source region and a body contact region, the N body regions extend from the surface of the drift region into the drift region and are located in the middle region of the cell, n is a positive integer greater than or equal to 2, the first body region to the Nth body region are sequentially arranged in the direction perpendicular to the substrate, the first body region extends from the surface of the drift region, the second body region to the Nth body region are located in the drift region, the body contact region extends from the surface of the first body region into the first body region, the source region and the body contact region are in contact with each other, and the N is a positive integer greater than or equal to 2. The source regions are located at two ends of the body contact region. And the Nth body region collects holes generated by collision ionization, so that the Vbe voltage of the parasitic BJT is reduced, and the safe working region of the device is improved.

A photomultiplier containing a solid-state photoconductive film composed of amorphous selenium (a-Se) is provided. In the a-Se-containing photomultiplier, a hole-blocking layer is provided, which maximizes gain and maintains low dark conductivity. Furthermore, the hole-blocking layer enables reliable and repeatable impact ionization without irreversible breakdown. The hole-blocking layer is a non-insulating metal oxide with a dielectric constant (k) greater than 10.

A data retention operation of holding positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base body is performed by controlling voltages applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines; and a data erase operation is performed by removing positive hole groups from inside the semiconductor base body by controlling the voltages applied to plate lines, word lines, source line, odd-numbered bit lines, and even-numbered bit lines and lowering a voltage of The semiconductor base body by means of capacitive coupling between the plate lines and word lines. A block is made up of memory cells arrayed in a matrix, and storage data is read from the memory cells in the block alternately to the odd-numbered bit lines and even-numbered bit line.

This application relates to a method for optimizing the structural parameters of a shield-gate trench-type field-effect transistor. The method includes: obtaining established structural parameters and initial undetermined structural parameters; extracting the peak electric field path of the transistor; intercepting a plurality of sampling points on the peak electric field path; generating a collision ionization integral distribution curve based on the collision ionization integrals of the plurality of sampling points; determining whether the number of target ionization integral values in the collision ionization integral distribution curve is less than a target threshold. If so, update the initial undetermined structural parameters and then re-perform the step of determining whether the number of target ionization integral values in the collision ionization integral distribution curve is less than the target threshold until the number of target ionization integral values is greater than or equal to the target threshold. If not, use the current undetermined structural parameters as the target structural parameters. The solution provided by this application can effectively balance the contradictory relationship between the specific on-resistance and the breakdown voltage, thereby effectively reducing the static power consumption of the transistor.

The invention discloses a compact Marx generator based on an impact ionization semiconductor device, and relates to the field of a pulse power technology and a power semiconductor device crossing technology. Comprising N stages of sub Marx generators which are cascaded in sequence, and each sub Marx generator comprises an impact ionization semiconductor device, a first charging isolation element, a second charging isolation element, an energy storage unit, a first ground capacitor and a second ground capacitor; for any stage of sub Marx generator, the first end of the impact ionization semiconductor device is connected with the first end of the first charging isolation element, the first end of the first ground capacitor and the first end of the energy storage unit, the second end of the first ground capacitor is grounded, the second end of the impact ionization semiconductor device is connected with the first end of the second charging isolation element, and the second end of the second charging isolation element is grounded. The second end of the second charging isolation element is connected with the second end of the energy storage unit and the first end of the second ground capacitor, and the second end of the second ground capacitor is grounded. According to the compact Marx generator, the conduction safety is improved.

The application belongs to the technical field of semiconductor devices, and provides a super-junction structure parameter optimization method in a given temperature range, so that the optimized super-junction structure meets the expected withstand voltage value in the given temperature range, and ensures that the specific on-resistance is minimum under the same condition, so that the energy consumption of the super-junction structure is minimum; first, a design withstand voltage fitting expression is constructed, the design withstand voltage BV design in the given temperature range is obtained by re-fitting the fitting expression require , so that the actual BV value of the optimization result in the actual application is higher than the expected withstand voltage BV require , thereby ensuring that the device will not break down in advance, and has the minimum specific on-resistance; then, by using a newly proposed effective collision ionization rate model, an analytical expression of the structure parameters (doping depth optimization value W opt and doping concentration optimization value N opt ) related to the design withstand voltage BV design , the aspect ratio AR and the maximum temperature T max is given, which provides a more convenient solving way for the parameter optimization of the super-junction structure.

The application relates to an anti-single-particle GaN HEMT device with a comb-shaped channel structure and belongs to the technical field of semiconductors. The device comprises, from bottom to top, a buffer layer, a barrier layer, a passivation layer, a source, a gate and a drain, and further comprises a comb-shaped channel structure, wherein the comb-shaped channel structure is located on the left side of the drain, above the barrier layer, and a blocking layer exists between the drain and the barrier layer. The application introduces a comb-shaped n-type AlGaN channel on the left side of the drain and separates the drain from the barrier layer by the blocking layer; a large number of carriers generated after single-particle incidence can be discharged through the comb-shaped n-type AlGaN channel, not only the electric field near the drain is modulated, but also the high voltage near the drain is borne by the blocking layer, the high field formed on the side of the drain close to the gate after single-particle incidence is greatly reduced, the collision ionization rate of the carriers near the drain and the transient current in the device are reduced, and the single-particle burnout voltage of the device is improved.

The invention relates to a method for preparing an electron transport layer in a perovskite battery through magnetron sputtering and the perovskite battery, the magnetron sputtering is carried out by adopting the method provided by the invention, secondary electrons generated by target materials serving as cathodes are interacted by an electric field and a magnetic field, and then are effectively controlled in a space defined by at least two target materials, so that the electron transport layer in the perovskite battery is prepared. Columnar plasmas are formed, the collision ionization probability between electrons and reaction gas is further increased, the ionization degree of the reaction gas is effectively improved, and the deposition rate of the electron transport layer on the surface of the perovskite layer is increased. Besides, the plasma formed by the secondary electrons is bound in the space enclosed by the at least two target materials, so that the bombardment effect of the electrons with relatively high kinetic energy on the substrate can be avoided, the damage to the substrate is further effectively reduced, meanwhile, the temperature rise of the perovskite layer in the magnetron sputtering process is also inhibited, and the cycling stability of the perovskite battery is ensured.

An improved structure of a lateral n-channel LDMOS transistor is provided to avoid gate-oxide breakdown that occurs during transistor operation. The LDMOS transistor includes a dielectric isolation structure that physically isolates a region including a parasitic NPN transistor from a region that generates a hole current due to weak impact ionization (i.e., the extended drain region of the LDMOS transistor). According to an embodiment of the present disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to reduce the gain of the parasitic NPN transistor and reduce the back-gate resistance in order to further improve the robustness of the LDMOS transistor.

The application belongs to the technical field of power devices, and provides a silicon carbide power device with high avalanche robustness and a preparation method and a chip thereof. A hetero buried island region is formed on a first side of an interface between an N-type drift region and a silicon carbide substrate, the hetero buried island region is arranged opposite to a P-type well region, the P-type well region and the N-type drift region form a PN junction, and the hetero buried island region is introduced in a region far from the PN junction to form a heterojunction structure, so that the high collision ionization production rate is transferred to the heterojunction, and then when an avalanche is introduced in high-speed switching, the collision ionization production rate of the PN junction is transferred to the heterojunction, the capture of holes by a gate dielectric layer is avoided, the drift of a threshold voltage and a forward conduction voltage of a parasitic diode of the device is avoided, and the robustness of the device is improved.

A memory device includes pages each including memory cells arranged in columns in plan view on a substrate, and voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes, generated by an impact ionization phenomenon, inside a semiconductor body. The first and second impurity regions are connected to source and bit lines, the first and second gate conductor layers are connected to word and plate lines, and voltages applied to these lines are controlled to perform a page write operation, a page erase operation, and a page read operation. In the page write operation, the group of positive holes are retained inside the semiconductor body at a first time, and a page write post-processing operation of making a group of excess positive holes disappear is performed at a second time.

The present application relates to the field of pharmaceutical analysis, and more particularly to a method for simultaneously determining the contents of multiple components in Yinhu Ganmao Powder based on GC-MS technology, which comprises a method for simultaneously determining the contents of multiple components in Yinhu Ganmao Powder or volatile oil. The method comprises the following steps: (1) performing GC analysis on the extract of Yinhu Ganmao Powder or volatile oil; (2) performing mass spectrometry identification using a mass spectrometry library, with the mass spectrometry conditions being: ion source is electron impact ionization (EI), energy is 70 eV, ion source temperature is 200 DEG C, interface temperature is 250 DEG C, full scan mode is m / z 45-500, electron multiplier voltage is 1.5 kV, and collision gas is argon (99.99%). The present application establishes a method for simultaneously determining the contents of multiple components in Yinhu Ganmao Powder or volatile oil based on GC-MS technology, wherein more than 50 compounds are identified in the volatile oil of Yinhu Ganmao Powder, and more than 25 compounds are identified in the n-hexane extract of the powder.

The invention relates to the field of infrared photoelectric devices, in particular to a cascade noise reduction planar avalanche photodiode, which comprises a cascade multiplication region between a substrate and a cap layer. A PN junction is formed in the cascade multiplication region, and the PN junction is a planar PN junction. The invention also comprises a preparation method of the cascaded noise-reduction planar avalanche photodiode. The structure of the linear avalanche photodiode is improved and innovated, a multiplication region and a cascade gain stage are introduced, a plurality of gain stages are connected in series, and each stage can amplify a signal once to maximize collision ionization caused by electrons and minimize hole ionization at the same time. By optimizing the thickness and doping concentration of each sub-layer in each gain stage, additional multiplication noise and dark current are reduced, thereby improving device gain and reducing device noise. According to the preparation method, a planar junction process is utilized, and a P-type region is formed by two times of diffusion to realize a planar junction, so that the dark current of the device is reduced.

A method for determining the presence of a perfluoro- or polyfluorochemical (PFC), such as a PFAS compound, in a sample is described. The method involves generating sample ions from the sample using electron impact ionization (El), direct laser ionization, or field desorption ionization, and mass-analyzing the sample ions using a mass analyzer to generate mass spectral data. The mass analyzer has a mass accuracy of approximately ≤ 100 ppm and a resolution of approximately ≥ 10,000. The method further includes determining whether an ion peak is present in the mass spectral data exhibiting an accurate mass-to-charge ratio within ± 100 ppm of a first accurate mass-to-charge ratio (m / z). The first accurate mass-to-charge ratio (m / z) is the exact mass-to-charge ratio of an ion that indicates the presence of a PFC in the sample.The procedure further includes determining whether a PFC is present in the sample if it is determined that an ion peak is present which has an accurate mass-to-charge ratio within ± 100 ppm of the first accurate mass-to-charge ratio m / z.

Aiming at the problem that the service life of a device is shortened due to electrode damage caused by ion bombardment, the invention provides a grid regulation and control type vertical structure micro-nano plasma triode which is of a vertical structure and comprises a substrate, a lower electrode, a grid, an upper electrode, a vertical insulating layer and a horizontal insulating layer. The lower electrodes are arranged above the substrate, the grid electrode is arranged above the lower electrodes, the horizontal insulating layers cover the upper layer and the lower layer of the grid electrode, the vertical insulating layers are distributed on the side edges of the grid electrode, the upper electrodes are arranged above the upper horizontal insulating layers, the edges of the upper electrodes are flush with the edges of the vertical insulating layers, and a vertical air channel is formed between the two upper electrodes. The grid electrode can effectively regulate and control ion and electron distribution in a channel, collision ionization is increased, micro-nano plasma formation is promoted, and the working voltage of the device is reduced. In addition, the grid electrode can regulate and control the electric field distribution in the vertical channel, change the ion motion trail, inhibit high-speed ions from directly bombarding the electrode, and prolong the service life of the device.

This invention relates to the field of energy storage materials technology, specifically disclosing a graft-modified polyethylene dielectric material, its preparation method, and its applications. The material is prepared by chemically grafting 1-(3-thiopropyl)-2-vinylpyridine betaine (SPV) into the polyethylene backbone. The pyridine rings in the SPV side groups, through their conjugated electron effect, introduce localized energy level structures into the nonpolar polyethylene matrix, forming distributed deep-trap charge-capturing regions. This significantly suppresses the migration and collisional ionization of charge carriers under high electric fields, effectively improving the material's breakdown field strength and high-field service stability. Simultaneously, the grafting modification method does not disrupt the regular arrangement of the polyethylene backbone, thus maintaining the inherent low dielectric loss, good flexibility, and processing performance of polyethylene. It is particularly suitable for the preparation of high-energy-density film capacitors and has broad application prospects in electrical equipment operating under extreme conditions such as new energy vehicles, aerospace, and smart grids.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with a variable-angle funnel-shaped field oxide structure. The STI side wall angle is regulated and controlled in a segmented mode, an inclination angle structure is introduced to the position close to a high-voltage drift region, a gradually-changed field oxygen boundary is formed, transverse expansion and gradient slow release of an electric field at the edge of the drift region can be achieved, the electric field concentration effect at the STI corner is remarkably weakened, and the vertical boundary of the lower portion maintains the structural stability; and stress concentration caused by deep groove etching is avoided. Finally, compared with a traditional STI LDMOS structure with a single side wall angle, breakdown voltage (BV) can be partially improved, on resistance (Ron) of a drift region can be remarkably reduced, collision ionization rate on a drain electrode-field oxygen interface is reduced, a hot carrier injection (HCI) effect is remarkably inhibited, and the service life of a device is prolonged.

The application discloses a kind of anti single particle radiation reinforced gallium nitride high electron mobility transistor, comprising: Si substrate, GaN buffer layer, N type AlGaN layer being arranged in the top layer local position of GaN buffer layer, AlGaN barrier layer being arranged on GaN buffer layer and N type AlGaN layer, P type GaN layer being arranged above N type AlGaN layer and inside AlGaN barrier layer, surface SiN passivation layer, and drain electrode, gate electrode, source electrode;The N type AlGaN layer is generated below barrier layer between gate and drain in the application, so that output current is improved;By generating P type GaN layer and N type AlGaN layer between source and drain, the conduction band energy level can be raised, the injection of electrons from source to buffer layer under off state is blocked, the buffer layer leakage current is reduced, the internal electric field of device is weakened, the collision ionization generation of electron-hole pair is reduced, the single particle transient current is reduced, and the device radiation resistance performance is improved.