40 results about "Impact ionization" patented technology

The invention relates to the technical field of semiconductor manufacturing, and provides a SiGe HBT breakdown voltage simulation method, device, equipment and medium, and the method comprises the steps: building a structure model according to the actual structure parameters of a SiGe HBT; obtaining a quantitative relation between a carrier ionization coefficient and electric field intensity based on an impact ionization model, and constructing a physical model according to the carrier ionization coefficient; carrying out temperature correction on the carrier ionization coefficient according to a preset standard parameter value; and based on the structure model and the physical model, carrying out breakdown voltage simulation according to a preset bias, and generating a breakdown curve of the SiGe HBT. According to the method, the problems of poor simulation adaptability, insufficient temperature adaptability and high optimization cost of the SiGe HBT breakdown voltage in the prior art are solved, electric field distribution, carrier transport and collision ionization processes in a device are accurately analyzed before actual tape-out, and a reliable simulation tool is provided for balancing the tradeoff contradiction between the SiGe HBT high-frequency performance and the breakdown voltage.

A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.

The invention discloses a compact Marx generator based on an impact ionization semiconductor device, and relates to the field of a pulse power technology and a power semiconductor device crossing technology. Comprising N stages of sub Marx generators which are cascaded in sequence, and each sub Marx generator comprises an impact ionization semiconductor device, a first charging isolation element, a second charging isolation element, an energy storage unit, a first ground capacitor and a second ground capacitor; for any stage of sub Marx generator, the first end of the impact ionization semiconductor device is connected with the first end of the first charging isolation element, the first end of the first ground capacitor and the first end of the energy storage unit, the second end of the first ground capacitor is grounded, the second end of the impact ionization semiconductor device is connected with the first end of the second charging isolation element, and the second end of the second charging isolation element is grounded. The second end of the second charging isolation element is connected with the second end of the energy storage unit and the first end of the second ground capacitor, and the second end of the second ground capacitor is grounded. According to the compact Marx generator, the conduction safety is improved.

The application relates to an anti-single-particle GaN HEMT device with a comb-shaped channel structure and belongs to the technical field of semiconductors. The device comprises, from bottom to top, a buffer layer, a barrier layer, a passivation layer, a source, a gate and a drain, and further comprises a comb-shaped channel structure, wherein the comb-shaped channel structure is located on the left side of the drain, above the barrier layer, and a blocking layer exists between the drain and the barrier layer. The application introduces a comb-shaped n-type AlGaN channel on the left side of the drain and separates the drain from the barrier layer by the blocking layer; a large number of carriers generated after single-particle incidence can be discharged through the comb-shaped n-type AlGaN channel, not only the electric field near the drain is modulated, but also the high voltage near the drain is borne by the blocking layer, the high field formed on the side of the drain close to the gate after single-particle incidence is greatly reduced, the collision ionization rate of the carriers near the drain and the transient current in the device are reduced, and the single-particle burnout voltage of the device is improved.

The invention relates to a method for preparing an electron transport layer in a perovskite battery through magnetron sputtering and the perovskite battery, the magnetron sputtering is carried out by adopting the method provided by the invention, secondary electrons generated by target materials serving as cathodes are interacted by an electric field and a magnetic field, and then are effectively controlled in a space defined by at least two target materials, so that the electron transport layer in the perovskite battery is prepared. Columnar plasmas are formed, the collision ionization probability between electrons and reaction gas is further increased, the ionization degree of the reaction gas is effectively improved, and the deposition rate of the electron transport layer on the surface of the perovskite layer is increased. Besides, the plasma formed by the secondary electrons is bound in the space enclosed by the at least two target materials, so that the bombardment effect of the electrons with relatively high kinetic energy on the substrate can be avoided, the damage to the substrate is further effectively reduced, meanwhile, the temperature rise of the perovskite layer in the magnetron sputtering process is also inhibited, and the cycling stability of the perovskite battery is ensured.

The application belongs to the technical field of power devices, and provides a silicon carbide power device with high avalanche robustness and a preparation method and a chip thereof. A hetero buried island region is formed on a first side of an interface between an N-type drift region and a silicon carbide substrate, the hetero buried island region is arranged opposite to a P-type well region, the P-type well region and the N-type drift region form a PN junction, and the hetero buried island region is introduced in a region far from the PN junction to form a heterojunction structure, so that the high collision ionization production rate is transferred to the heterojunction, and then when an avalanche is introduced in high-speed switching, the collision ionization production rate of the PN junction is transferred to the heterojunction, the capture of holes by a gate dielectric layer is avoided, the drift of a threshold voltage and a forward conduction voltage of a parasitic diode of the device is avoided, and the robustness of the device is improved.

The present application relates to the field of pharmaceutical analysis, and more particularly to a method for simultaneously determining the contents of multiple components in Yinhu Ganmao Powder based on GC-MS technology, which comprises a method for simultaneously determining the contents of multiple components in Yinhu Ganmao Powder or volatile oil. The method comprises the following steps: (1) performing GC analysis on the extract of Yinhu Ganmao Powder or volatile oil; (2) performing mass spectrometry identification using a mass spectrometry library, with the mass spectrometry conditions being: ion source is electron impact ionization (EI), energy is 70 eV, ion source temperature is 200 DEG C, interface temperature is 250 DEG C, full scan mode is m / z 45-500, electron multiplier voltage is 1.5 kV, and collision gas is argon (99.99%). The present application establishes a method for simultaneously determining the contents of multiple components in Yinhu Ganmao Powder or volatile oil based on GC-MS technology, wherein more than 50 compounds are identified in the volatile oil of Yinhu Ganmao Powder, and more than 25 compounds are identified in the n-hexane extract of the powder.

A method for determining the presence of a perfluoro- or polyfluorochemical (PFC), such as a PFAS compound, in a sample is described. The method involves generating sample ions from the sample using electron impact ionization (El), direct laser ionization, or field desorption ionization, and mass-analyzing the sample ions using a mass analyzer to generate mass spectral data. The mass analyzer has a mass accuracy of approximately ≤ 100 ppm and a resolution of approximately ≥ 10,000. The method further includes determining whether an ion peak is present in the mass spectral data exhibiting an accurate mass-to-charge ratio within ± 100 ppm of a first accurate mass-to-charge ratio (m / z). The first accurate mass-to-charge ratio (m / z) is the exact mass-to-charge ratio of an ion that indicates the presence of a PFC in the sample.The procedure further includes determining whether a PFC is present in the sample if it is determined that an ion peak is present which has an accurate mass-to-charge ratio within ± 100 ppm of the first accurate mass-to-charge ratio m / z.

Aiming at the problem that the service life of a device is shortened due to electrode damage caused by ion bombardment, the invention provides a grid regulation and control type vertical structure micro-nano plasma triode which is of a vertical structure and comprises a substrate, a lower electrode, a grid, an upper electrode, a vertical insulating layer and a horizontal insulating layer. The lower electrodes are arranged above the substrate, the grid electrode is arranged above the lower electrodes, the horizontal insulating layers cover the upper layer and the lower layer of the grid electrode, the vertical insulating layers are distributed on the side edges of the grid electrode, the upper electrodes are arranged above the upper horizontal insulating layers, the edges of the upper electrodes are flush with the edges of the vertical insulating layers, and a vertical air channel is formed between the two upper electrodes. The grid electrode can effectively regulate and control ion and electron distribution in a channel, collision ionization is increased, micro-nano plasma formation is promoted, and the working voltage of the device is reduced. In addition, the grid electrode can regulate and control the electric field distribution in the vertical channel, change the ion motion trail, inhibit high-speed ions from directly bombarding the electrode, and prolong the service life of the device.

This invention relates to the field of energy storage materials technology, specifically disclosing a graft-modified polyethylene dielectric material, its preparation method, and its applications. The material is prepared by chemically grafting 1-(3-thiopropyl)-2-vinylpyridine betaine (SPV) into the polyethylene backbone. The pyridine rings in the SPV side groups, through their conjugated electron effect, introduce localized energy level structures into the nonpolar polyethylene matrix, forming distributed deep-trap charge-capturing regions. This significantly suppresses the migration and collisional ionization of charge carriers under high electric fields, effectively improving the material's breakdown field strength and high-field service stability. Simultaneously, the grafting modification method does not disrupt the regular arrangement of the polyethylene backbone, thus maintaining the inherent low dielectric loss, good flexibility, and processing performance of polyethylene. It is particularly suitable for the preparation of high-energy-density film capacitors and has broad application prospects in electrical equipment operating under extreme conditions such as new energy vehicles, aerospace, and smart grids.

The utility model relates to the technical field of air purification and disinfection, and provides a high-pressure high-energy tunnel particle sterilization mechanism and a device thereof, the high-pressure high-energy tunnel particle sterilization mechanism comprises an outer tubular column, an inner conductor and a fixing frame, the outer tubular column is internally provided with a channel for the inner conductor to pass through, the inner wall of the channel is provided with threads, the outer tubular column is vertically arranged on the fixing frame, and the outer tubular column is vertically arranged on the fixing frame. The inner electric conductor is a metal electric conductor with the outer side face in a continuous corrugated shape, the height of the inner electric conductor is the same as that of the outer tubular column, the inner electric conductor is located in the middle of the outer tubular column, and the lower end of the inner electric conductor is vertically and fixedly arranged on the fixing frame. A high-pressure high-energy particle release ring is formed by the outer tubular column and the inner electric conductor, so that a high-energy particle tunnel body is formed between the outer tubular column and the inner electric conductor, particles in the tunnel body are impacted and ionized, bacteria, viruses and particles passing through the tunnel body are impacted and ionized, original structures are damaged, and the bacteria, the viruses and the particles die instantly. The disinfection and sterilization effects are achieved.

The application discloses a low-noise and low-working-voltage microwave diode and a preparation method thereof, and the microwave diode is a vertical heterojunction structure composed of indium selenide (InSe) and black phosphorus (BP). The traditional material for preparing an impact ionization avalanche transit time (IMPATT) microwave diode is replaced by the two-dimensional material BP, and a ballistic avalanche mechanism unique to the BP, that is, a scattering-free quantum coherent transport avalanche mode, so that the IMPATT microwave diode in the application is obviously lower than a traditional avalanche device in terms of avalanche noise, and the avalanche threshold voltage is 2-3 orders of magnitude lower than that of the traditional device. In addition, the bipolarity of the BP makes it unnecessary to chemically dope the material when the IMPATT diode is prepared, thereby reducing the preparation difficulty of the device. Compared with the IMPATT diode prepared from the traditional material, the IMPATT diode in the application not only has lower avalanche noise and avalanche breakdown voltage, but also is simple to prepare, thereby greatly improving the working performance of the device.

The invention discloses a fast erasing method for a nonvolatile memory based on channel hot electron induced hot hole injection and application of the fast erasing method. In a nonvolatile flash memory with split gates, positive source voltage, positive drain voltage and negative storage gate voltage are applied when a selection gate (MG) and a storage node (MS) are started; high-energy channel hot electrons are generated in the channel; high-density hot holes are generated in a channel region through the collision ionization effect of channel hot electrons; hot holes are injected into the charge trapping layer through the tunneling oxide layer, so that the neutralization of stored electrons is completed, and the erasing operation is realized. According to the invention, the collision ionization effect of hot electrons is utilized to generate high-density hot holes, and the hot holes are injected into the charge trapping layer for rapid erasing, so that the erasing efficiency is remarkably improved, the electric field stress is reduced, and the durability and retention performance of equipment are improved.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line, and the bit line is connected to a sense amplifier circuit via a switch circuit. During a page read operation, page data of a memory cell group selected by the word line is read into a sense amplifier circuit concurrently with a memory cell refresh operation for forming positive hole groups.

This invention relates to an LDMOS device and its manufacturing method. The LDMOS device includes: a source region; a drain region; a drift region; a field oxide layer; a gate extending from near the edge of the source region onto the field oxide layer; a first low-doped region located directly below the field oxide layer on the side near the source region; and a second low-doped region located directly below the gate on the side near the drain region. The region between the first and second low-doped regions has a first conductivity type. The first and second low-doped regions have the first conductivity type, and their doping concentration is lower than that of the region between them; or the first and second low-doped regions have a second conductivity type. This invention introduces low-doped or inverted regions into areas of concentrated electric field, making the potential line distribution sparser in these two areas, reducing the collisional ionization rate, and mitigating the hot carrier injection effect in these areas.

The invention provides a storage array and a preparation method thereof, a memory and electronic equipment, and relates to the technical field of data storage. The memory array comprises a substrate and a plurality of memory cells, each memory cell in turn comprises a transistor, and the transistor in turn comprises a source electrode, a drain electrode, a grid electrode and a channel. Wherein the source electrode comprises a source electrode doped region formed in the substrate, the drain electrode comprises a metal silicide layer, the channel is located in the substrate, one side of the channel is in contact with the metal silicide layer, and the other side of the channel is in contact with the source electrode doped region. The grid electrode is arranged on the channel. One side of the metal silicide layer of the drain electrode is in contact with the channel, so that a Schottky junction can be formed between the metal silicide layer and the channel, the electric field intensity of the drain electrode region is increased, the voltage required for causing collision ionization is reduced, and the turn-on voltage and the driving energy consumption of the device are further reduced.

This invention provides a method for predicting surface flashover voltage in a perfluoroisobutyronitrile (PFOS) mixed gas based on plasma dynamics. It comprehensively considers the effects of gas molecule desorption and collisional ionization, surface charge accumulation at the gas-solid interface, and carrier traps in the solid medium on the solid side. A surface flashover model is constructed, and by solving the continuity governing equations, Poisson's equation, and local field approximation equations for charged particles, the spatiotemporal distribution of the electric field intensity and the transport of charged particles in space are obtained, serving as a means to predict the surface flashover voltage. This invention not only predicts surface flashover voltage but also holds promise as a data reference for the development of environmentally friendly insulating gas equipment, saving experimental costs and improving R&D efficiency.

The invention provides a super junction structure parameter optimization method and apparatus, a terminal device and a storage medium. The method comprises the steps of establishing a temperature dependence model of each physical parameter in a super junction structure; wherein the temperature dependence model is used for describing the change rule of the physical parameters along with the temperature; establishing constraint conditions according to a planar junction theory and an avalanche breakdown principle; wherein the constraint conditions comprise a collision ionization integral breakdown condition and a buffer layer boundary condition; obtaining target information based on the design target of the super junction structure; wherein the target information comprises breakdown voltage, depth-to-width ratio and temperature; solving a performance parameter optimization value of the super junction structure under the target information according to the temperature dependence model and the constraint condition; wherein the performance parameters comprise depletion layer thickness, doping concentration and specific on-resistance. According to the method, the optimization calculation of the performance parameters of the super junction structure can be realized in a larger temperature range.

Hybrid MOSFET designs in which low ON resistance RON and high transconductance Gm values can be achieved while improving the safe operating area (SOA) of the device. Embodiments accomplish these design goals by adding a sub-gate drift region substantially only under the conductive layer of the gate structure, thereby allowing the drain to be positioned in closer proximity to the source and thus reducing RON and increasing Gm. The sub-gate drift region also reduces the peak drain-side E-field by dividing the E-field into two edges. This aspect helps push out the onset of breakdown mechanisms such as band-to-band tunneling and / or impact ionizations. Another aspect is a stepped gate oxide that is thicker in the drift region, which reduces parasitic CGD and improves the breakdown voltage, BVDSS, thus enhancing device reliability. Hybrid MOSFETs are particularly useful in cascode applications such as for envelope tracking and average power tracking.

The invention provides a method for predicting lower surface flashover voltage of perfluoroisobutyronitrile mixed gas based on plasma dynamics, which comprises the following steps of: constructing a surface flashover model by comprehensively considering the influence of desorption and collision ionization of gas molecules related to a gas side, charge accumulation on the surface of a gas-solid interface and a carrier trap existing in a solid medium on a solid side; by solving a continuity control equation, a Poisson equation and a local field approximation equation of the charged particles, the spatial and temporal distribution condition of the electric field intensity and the transport condition of the charged particles in the space are obtained as a means for predicting the surface flashover voltage. The method not only can predict the surface flashover voltage, but also is expected to serve as data reference for research and development of environment-friendly insulating gas equipment, test cost is saved, and research and development efficiency is improved.

Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.

The application discloses a pixelated superconductor coupled semiconductor electron multiplication detector and a detection method. The application comprises a detection array composed of a plurality of microelement pixels, wherein the microelement pixels comprise an energy absorption layer, a superconducting induction layer, a tunnel insulation layer and a semiconductor charge multiplication region; the energy absorption layer is configured to receive target particles or radiation and cause energy deposition; the superconducting induction layer is configured to absorb the energy deposition and excite non-equilibrium quasi-particles; the tunnel insulation layer is configured to allow the non-equilibrium quasi-particles to realize cold injection into the semiconductor charge multiplication region through quantum tunneling effect; and the semiconductor charge multiplication region is configured to amplify the injected carriers through an intrinsic avalanche collision ionization mechanism in an extremely low temperature environment; wherein each microelement pixel works in a Geiger mode, and each microelement pixel is connected to a common output end in a parallel mode, and the reconstruction of incident energy is realized by digitally counting the microelement pixels that cause Geiger discharge.

The invention relates to an ionization system (2) for ionizing gases, comprising an ionization chamber (4) and, connected to the ionization chamber (4), a feed line (8) for feeding neutral gas into the ionization chamber (4). According to the invention, a feed line (8) is assigned a predischarge stage (12) designed to pre-ionize the gas flowing through the feed line (8) and to generate free electrons, and the ionization chamber (4) is assigned a main discharge stage (14) designed to accelerate and impact-ionize the free electrons, in particular substantially over the entire volume (V) of the neutral gas, wherein the predischarge stage (12) and the main discharge stage (14) have a common coil assembly (15). The invention furthermore relates to an associated spaceflight propulsion unit (100) and to a spacecraft (300), to a use and to a method (200).

The invention provides a depletion type metal-oxide-semiconductor field effect transistor (MOSFET) structure with radiation hardening. According to the invention, a traditional polysilicon gate is improved into a separated gate structure; p well buffer layers are introduced below the P well regions on the left side and the right side respectively; and an N-type doped slowly-changing region is introduced between the N + substrate and the N-drift region. According to the invention, the N-type doped slowly-varying region can effectively optimize the longitudinal electric field distribution in the device, alleviate the peak electric field, and inhibit the avalanche breakdown caused by collision ionization, thereby comprehensively improving the single particle resistance of the device; the separation gate structure can effectively prevent a large number of holes from accumulating at the bottom of the central gate oxide layer after heavy ions are incident, and restrain the concentration of an electric field in the gate oxide layer, so that the single event gate penetration (SEGR) resistance of the depletion type MOSFET is remarkably improved; besides, the P-well buffer layer helps to accelerate extraction of transient holes generated by bombardment of radiation particles in the device body, enables the transient holes to flow out of the body rapidly, inhibits starting of a parasitic transistor, and has a good inhibition effect on single event burnout (SEB).

The invention discloses a calculation method and device for a numerical value of a semiconductor device, electronic equipment and a storage medium, and is used for solving the problem that electrical simulation under a high-voltage working condition cannot meet requirements in the prior art. The method comprises the following steps: determining a control equation of a semiconductor device to be solved; performing gummel iteration on the control equation based on a preset initial value, and determining a current intermediate solution of the control equation; under the constraint of the constraint condition, determining the corrected carrier collision ionization rate based on the carrier collision ionization rate objective function and the current intermediate solution of the control equation; fixing a collision ionization term in the control equation as a corrected carrier collision ionization rate constant value, and performing gummel iteration to obtain an intermediate solution of the current converted control equation; and based on the intermediate solution of the current converted control equation, repeating the step of solving the corrected carrier collision ionization rate in a constraint manner until the intermediate solution of the current converted control equation in the next round meets a set condition, and determining the intermediate solution as a final solution of the control equation.

The application relates to a nanosecond high-voltage pulse driving thyristor overcurrent conduction device and method, which comprises a thyristor module, a spiral wire pulse generation module, a primary switch module and an auxiliary trigger unit. The thyristor module adopts a conventional commercial sheet-shaped thyristor module; the spiral wire pulse generation module is formed by interlacing and tightly winding two metal belts and two insulating belts, and the whole is in a planar spiral shape; a small fast thyristor is used to form the primary switch module in series connection; and a semiconductor circuit breaker is used to steepen the pulse at the output end of the spiral wire. The nanosecond high-voltage pulse is used to act on the anode and the cathode of the conventional sheet-shaped thyristor, a bundle of fast propagation impact ionization waves is generated in the semiconductor structure of the thyristor, and the conductive channels are uniformly distributed on the whole semiconductor cylindrical cross section of the thyristor. The impact ionization wave mode makes the thyristor obtain the performance far exceeding the rated current and the current rising rate in the conventional trigger mode.

The application discloses a non-volatile memory fast erasing method based on channel hot electron induced hot hole injection and application thereof. In the non-volatile flash memory with split gate, a positive source voltage, a positive drain voltage and a negative storage gate voltage are applied under the opening of a selection gate MG and a storage node MS, so as to generate high-energy channel hot electrons in the channel. High-density hot holes are generated in the channel region through the collision ionization effect of the channel hot electrons. The hot holes are used to inject the charge trapping layer through the tunneling oxide layer, the neutralization of the storage electrons is completed, and the erasing operation is realized. The application generates high-density hot holes through the collision ionization effect of the hot electrons, and the hot holes are used to inject the charge trapping layer for fast erasing, so that the erasing efficiency is improved, the electric field stress is reduced, and the durability and retention performance of the equipment are improved.

The present application belongs to the technical field of lightning protection and arc extinguishing, and particularly relates to a novel lightning protection and arc extinguishing device, which solves the problem that the existing lightning protection and arc extinguishing device is prone to burst due to excessive pressure in the compressed pipeline when using compressed air for arc extinguishing. The arc extinguishing effect of the device is not affected by the size of the device and environmental conditions, but the arc is extinguished by using the chemical properties of the gas itself. SF6 gas is a strong electronegative gas, and its molecules are easily adsorbed by free electrons to form large negative ions, thereby weakening the collision ionization process in the gas. Therefore, the SF6 gas has excellent electrical insulation strength, excellent arc extinguishing effect, and stable protection effect. The device is provided with several levels of gas arc extinguishing channels to ensure that the electric arc can be completely extinguished. The tin ball is composed of inert gas SF6 and a shell. When the temperature in the channel rises, the shell is melted by high temperature, and the inert gas SF6 in the interior enters the arc extinguishing chamber together with the electric arc and completes the extinguishing of the electric arc in the arc extinguishing chamber.

The application provides a trench terminal connection ground buried layer SiC JBS diode and a preparation method thereof. The diode comprises, from bottom to top, a cathode, a substrate, a buffer layer, a first epitaxial layer, a second epitaxial layer, and an anode located on the surface of the terminal transition ring of the second epitaxial layer. The first epitaxial layer comprises, inside and close to one side of the second epitaxial layer, a ground buried layer located in a preset area and a terminal transition ring located outside the preset area. In the direction perpendicular to the plane where the substrate is located, the orthographic projection of the second epitaxial layer and the orthographic projection of the terminal transition ring do not overlap. The side of the second epitaxial layer, inside and far away from the first epitaxial layer, comprises a main junction. Since the ground buried layer accelerates the discharge of excess carriers, effectively modulates the peak electric field distribution inside the device, reduces the electric field at the epitaxial / substrate homojunction, and further reduces the collision ionization at the homojunction, the single event transient current and the transient temperature are effectively reduced, and the threshold of the device leakage degradation is improved.

The invention discloses an IGBT (Insulated Gate Bipolar Translator) cell, which comprises a collector structure, an N-drift region, an emitter structure and a gate structure, the N-drift region is arranged above the collector structure, and the emitter structure and the gate structure are arranged above the N-drift region; the gate structure adopts a trench gate structure and comprises a plurality of deep trench gates and shallow trench gates which are arranged in parallel, collision ionization at the bottoms of the shallow trench gates is reduced by adjusting the arrangement mode of deep trenches, and the deep trench gates are used for shielding an electric field. The dynamic anti-avalanche capability of the whole device can be improved. In addition, the deep groove plays a role in shielding an electric field, the capacitance between the grid electrode and the collector electrode of the device is reduced, and the switching loss of the device can be reduced.