5 results about "Parasitic bipolar transistor" patented technology

The invention discloses a transistor, a semiconductor device, a preparation method thereof and electronic equipment. The transistor comprises a source electrode, a channel region and a drain electrode which are sequentially arranged along a first direction, and a grid electrode which is arranged at the periphery of the channel region in an insulating manner; the source electrode comprises a first semiconductor layer and a second semiconductor layer, the same ends of the first semiconductor layer and the second semiconductor layer in the first direction are connected with the channel region, and the second semiconductor layer is located on the side, close to the grid electrode, of the first semiconductor layer in the direction perpendicular to the first direction. The doping concentration of the first semiconductor layer is smaller than that of the second semiconductor layer. The invention relates to the technical field of semiconductor devices, in particular to a transistor, a semiconductor device, a preparation method of the semiconductor device and electronic equipment, and aims to restrain accumulation of holes in a channel as a starting point, relieve formation of a parasitic bipolar transistor and prolong storage retention time.

The present invention proposes a latch-up circuit capable of suppressing a trigger operation of a latch-up circuit formed by a parasitic bipolar transistor and a parasitic resistor in a semiconductor substrate on which a plurality of wells are formed, and a semiconductor structure having a structure capable of suppressing a trigger operation of a latch-up circuit.

The application discloses an anti-radiation LDMOS device structure and a preparation method thereof and electronic equipment. A plurality of uniformly distributed metal grooves are introduced in a second-conductivity-type drift region, the metal grooves are surrounded by a first-conductivity-type heavily doped region in the second-conductivity-type drift region, the metal grooves are connected to a source metal electrode and a drain metal electrode through a polysilicon resistor, the potential of the metal electrode in the drift region is regulated through voltage division of the polysilicon resistor, when a single particle is incident, a large number of free carriers are generated in the drift region, the carriers are attracted by the nearest metal groove under the action of an electric field, a new path is provided for the discharge of holes, the hole current is prevented from gathering to the source to lift the body region potential, and thus a parasitic bipolar transistor is prevented from being triggered to be turned on, and thus the SEB resistance of the LDMOS device is improved.

The application provides a super-junction MOSFET device structure and a preparation method thereof. By forming split-gate trenches and forming P-type shunt regions between the split-gate trenches, and combining independent contact holes of the source region and the shunt region with a metal layer structure, the overlapping area of the gate and the drain is effectively reduced to reduce the Miller capacitance and the gate-drain charge, thereby reducing the switching loss. The JFET effect area below the traditional planar gate and the parasitic resistance introduced by the JFET effect area are eliminated, the conduction resistance characteristics are significantly improved, and the split-gate trenches can play a role in lateral depletion to optimize the electric field distribution of the P-type shunt region, so that the P-type shunt region becomes a breakdown weak point. In the large-current off process, the P-type shunt region provides an additional low-impedance discharge path for the hole current, suppresses the current density flowing through the P-type base region, effectively prevents the opening of the parasitic bipolar transistor, avoids thermal runaway failure, and significantly improves the off ability and long-term reliability of the device under severe conditions of large current and high voltage.

The invention relates to a modeling method, device, system and medium for a floating body effect of a silicon-on-insulator device, and the method comprises the steps: building a set of strong nonlinear coupling equation set which takes channel current, threshold voltage, parasitic bipolar transistor current, body source voltage and a weak multiplication ionization factor as variables; four key physical processes of collision ionization, body charge accumulation, body bias effect and parasitic transistor conduction and interaction thereof are integrated in the model completely and explicitly, so that the model ensures the prediction completeness from the physical mechanism; therefore, the complex warping effect of the silicon-on-insulator device under high drain-source voltage can be simulated with high precision, and an accurate device model basis is provided for the design of a high-performance and high-reliability integrated circuit.