17 results about "Parasitic bipolar transistor" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a high-temperature-resistant VDMOS power transistor used in an extreme environment and a preparation method, the high-temperature-resistant VDMOS power transistor used in the extreme environment comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a lower P + layer, a P well layer and an N well layer, side P + layers are formed on the two sides of the single MOS cell and located between the source electrode and the lower P + layer through ion implantation. The side P + layer and the N well layer are distributed in an axial symmetry mode, and the profile of the section formed after the side P + layer and the N well layer are combined is in a shape like a Chinese character'ao '. According to the invention, through the axisymmetric concave deep junction structure formed by the side P + layer and the N well layer, the lateral expansion capability of a depletion region is obviously enhanced, the parasitic resistance of the P well layer is reduced, the conduction path of a parasitic bipolar transistor is blocked by the structure, and the latch-up effect at high temperature is avoided.

To improve performance of a semiconductor device.SOLUTION: A dummy field structure part 100 is included in a non-element formation region R2. The dummy field structure part 100 includes: a deep type well 110; an n-type well 120; a trench STI; a conductor layer 150; a first n-type semiconductor region 140; a second n-type semiconductor region 130A; and a second n-type semiconductor region 130B. A semiconductor device includes not only a parasitic bipolar transistor Tr1, but also a parasitic bipolar transistor Tr2.SELECTED DRAWING: Figure 8

The invention discloses a transistor, a semiconductor device, a preparation method thereof and electronic equipment. The transistor comprises a source electrode, a channel region and a drain electrode which are sequentially arranged along a first direction, and a grid electrode which is arranged at the periphery of the channel region in an insulating manner; the source electrode comprises a first semiconductor layer and a second semiconductor layer, the same ends of the first semiconductor layer and the second semiconductor layer in the first direction are connected with the channel region, and the second semiconductor layer is located on the side, close to the grid electrode, of the first semiconductor layer in the direction perpendicular to the first direction. The doping concentration of the first semiconductor layer is smaller than that of the second semiconductor layer. The invention relates to the technical field of semiconductor devices, in particular to a transistor, a semiconductor device, a preparation method of the semiconductor device and electronic equipment, and aims to restrain accumulation of holes in a channel as a starting point, relieve formation of a parasitic bipolar transistor and prolong storage retention time.

The invention discloses a Pwell doping structure for improving the VSWR (Voltage Standing Wave Ratio) of a radio frequency power VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) and a preparation method of the Pwell doping structure, and relates to the field of semiconductor materials, so that the radio frequency power VDMOS has the capability of coping with a high voltage standing wave Ratio, the Pwell doping structure for improving the VSWR of the radio frequency power VDMOS at least comprises a substrate; the donor type drift layer is formed on the substrate; acceptor-type doped regions formed in the first region and the second region of the donor-type drift layer; the P-type heavily doped region and the N-type doped region are formed on the acceptor-type doped region, and the P-type heavily doped region is in contact with the N-type doped region; the source electrode metal layers are formed in the first groove and the second groove of the acceptor type doped region; and the source electrode metal layers are in contact with the P-type heavily doped region and the N-type doped region. According to the structure, the parasitic resistance in the VDMOS is reduced, the conduction effect of a parasitic bipolar transistor (BJT) is inhibited, and the capability of the radio frequency power VDMOS for coping with a high voltage standing wave ratio is improved.

The present invention proposes a latch circuit capable of suppressing a trigger operation of the latch circuit formed of a parasitic resistor and a parasitic bipolar transistor in a semiconductor substrate in which a plurality of wells are formed, and a semiconductor substrate having a structure capable of suppressing the trigger operation of the latch circuit.

The present invention proposes a latch-up circuit capable of suppressing a trigger operation of a latch-up circuit formed by a parasitic bipolar transistor and a parasitic resistor in a semiconductor substrate on which a plurality of wells are formed, and a semiconductor structure having a structure capable of suppressing a trigger operation of a latch-up circuit.

The invention provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate; the N-type drift layer is positioned on one side of the substrate; the P-type base region is positioned on one side, far away from the substrate, of the N-type drift layer; the N-type source region and the P-type source region are located in the P-type base region; a gate trench located between the N-type source region and the P-type source region; the gate dielectric layer is located at the bottom and on the side wall of the gate groove, and the gate groove is filled with the gate layer; the total interlayer dielectric layer is positioned on one side, far away from the substrate, of the P-type base region; the N-type source region and the P-type source region are isolated by the total interlayer dielectric layer; the source electrode is positioned between the total interlayer dielectric layers and is respectively connected with the N-type source region and the P-type source region; and the drain is positioned on one side, far away from the N-type drift layer, of the substrate. According to the invention, the N-type source region and the P-type source region are separated by the total interlayer dielectric layer, so that the electron current and the hole current can be detected respectively, and whether the conduction failure of the parasitic bipolar transistor exists or not can be judged accurately when the failure occurs.

The present invention relates to the field of MOS semiconductor technology and discloses a high-temperature resistant VDMOS power transistor for use in extreme environments and a method for preparing the same. The transistor comprises a plurality of juxtaposed MOS cells, each of which includes a drain, a semiconductor epitaxial layer, a gate, and a source. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a lower P+ layer, a P-well layer, and an N-well layer. Side P+ layers are formed on both sides of the MOS cell and between the source and the lower P+ layer by ion implantation. The side P+ layers are axially symmetrical with the N-well layer, and the combined cross-sectional profile of the side P+ layers and the N-well layer is in the shape of a "concave" character. The present invention utilizes an axially symmetrical "concave" deep junction structure formed by the side P+ layers and the N-well layer to significantly enhance the lateral expansion capability of the depletion region and reduce the parasitic resistance of the P-well layer. This structure blocks the conduction path of the parasitic bipolar transistor and avoids latch-up at high temperatures.

The present invention provides an ESD protection device with adjustable trigger voltage and a method for manufacturing the same. The ESD protection structure comprises: a deep well of a first conductivity type and a functional device layer, the functional device layer being located within the deep well and comprising: a body region of a second conductivity type; a source and a drain of a first conductivity type; a gate structure disposed on the surface of the body region; an opening defined between the gate structure and the drain, with a lightly doped drain region disposed below the opening. When an influx of electrostatic positive current causes the voltage between the source and the body region below the channel region to reach a turn-on threshold voltage, the parasitic NPN bipolar transistor is turned on. The present invention also provides a method for manufacturing an ESD protection device with adjustable trigger voltage. The functional device layer manufactured by the method is located within the deep well and is compatible with actual CMOS triple-well processes.

The invention provides a semiconductor device and a manufacturing method thereof, and a design method of the semiconductor device, the semiconductor device comprises an IGBT cell and a current sensor cell, the IGBT cell and the current sensor cell are integrated on the same drift region, and the IGBT cell and the current sensor cell share a grid electrode; the barrier layer is located in the drift region, the barrier layer divides the semiconductor device into a first cellular region, a second cellular region and a transition region, the transition region is located between the first cellular region and the second cellular region, the barrier layer is located in the drift region of the transition region, the first cellular region is an IGBT cellular region, and the second cellular region is a current sensor cellular region. The second cell region and the first cell region share a grid electrode, and the transition region is provided with a barrier layer, so that the base region concentration of a parasitic bipolar transistor between the second cell region and the first cell region can be improved, interference to the current sensor can be reduced, and the accuracy of current output by the current sensor is improved. According to the technical scheme, the success rate of primary design of the device is improved.

Switch device comprising: a switch (10; 20; 40; 71) comprising a control terminal, a first load terminal and a second load terminal, a switch driver (16; 26; 48; 70) coupled to the control terminal of the switch (10; 20; 40; 71), an inverse current detector (15; 62; 710) configured to detect an inverse current condition at the first and second load terminals of the switch, and a voltage driver (14; 60, 61; 74, 77) configured to drive a node (OUT_R) associated with the switch driver (16; 26; 48; 70) to a predetermined voltage in response to the detection of an inverse current condition by the inverse current detector (15; 62; 710), wherein the switch driver (16; 26; 48; 70) comprises a semiconductor structure comprising a parasitic bipolar transistor (515; 516), wherein the voltage driver (14; 60, 61; 74, 77) is configured to prevent the parasitic bipolar transistor (515, 516) from pulling the node to a potential that prevents closure of the switch (10; 20; 40; 71) during an inverse current state.

A semiconductor device includes a dummy field structure in a non-element forming region. The dummy field structure includes a deep n-type well, an n-type well, a trench, a conductor layer, a first n-type semiconductor region, a second n-type semiconductor region, and a third n-type semiconductor region. The semiconductor device includes not only a first parasitic bipolar transistor but also a second parasitic bipolar transistor.

To provide a semiconductor device that suppresses the operation of a parasitic bipolar transistor during recovery switching and achieves both low loss and high recovery tolerance.SOLUTION: A semiconductor device 100 has a gate-controlled diode 101 including: a first semiconductor layer 1 of a first conductivity type; a second semiconductor layer 2 of the first conductivity type having a lower impurity concentration than the first semiconductor layer; a third semiconductor layer 3 of a second conductivity type; a fourth semiconductor layer 4 of the second conductivity type having a higher impurity concentration than the third semiconductor layer; a fifth semiconductor layer 5 of the second conductivity type having a higher impurity concentration than the fourth semiconductor layer 4; a sixth semiconductor layer 6 of the first conductivity type; a first electrode 11; a second electrode 12; a gate insulating film 23; and a gate electrode 22. The second electrode includes a protrusion 12A in contact with the fifth semiconductor layer and the sixth semiconductor layer, and the fourth semiconductor layer is in contact with the fifth semiconductor layer and the gate insulating film and is arranged such that the fourth semiconductor layer 4 and the sixth semiconductor layer do not overlap when viewed in a plane.SELECTED DRAWING: Figure 2

The application discloses an anti-radiation LDMOS device structure and a preparation method thereof and electronic equipment. A plurality of uniformly distributed metal grooves are introduced in a second-conductivity-type drift region, the metal grooves are surrounded by a first-conductivity-type heavily doped region in the second-conductivity-type drift region, the metal grooves are connected to a source metal electrode and a drain metal electrode through a polysilicon resistor, the potential of the metal electrode in the drift region is regulated through voltage division of the polysilicon resistor, when a single particle is incident, a large number of free carriers are generated in the drift region, the carriers are attracted by the nearest metal groove under the action of an electric field, a new path is provided for the discharge of holes, the hole current is prevented from gathering to the source to lift the body region potential, and thus a parasitic bipolar transistor is prevented from being triggered to be turned on, and thus the SEB resistance of the LDMOS device is improved.

The application provides a super-junction MOSFET device structure and a preparation method thereof. By forming split-gate trenches and forming P-type shunt regions between the split-gate trenches, and combining independent contact holes of the source region and the shunt region with a metal layer structure, the overlapping area of the gate and the drain is effectively reduced to reduce the Miller capacitance and the gate-drain charge, thereby reducing the switching loss. The JFET effect area below the traditional planar gate and the parasitic resistance introduced by the JFET effect area are eliminated, the conduction resistance characteristics are significantly improved, and the split-gate trenches can play a role in lateral depletion to optimize the electric field distribution of the P-type shunt region, so that the P-type shunt region becomes a breakdown weak point. In the large-current off process, the P-type shunt region provides an additional low-impedance discharge path for the hole current, suppresses the current density flowing through the P-type base region, effectively prevents the opening of the parasitic bipolar transistor, avoids thermal runaway failure, and significantly improves the off ability and long-term reliability of the device under severe conditions of large current and high voltage.

The invention relates to a modeling method, device, system and medium for a floating body effect of a silicon-on-insulator device, and the method comprises the steps: building a set of strong nonlinear coupling equation set which takes channel current, threshold voltage, parasitic bipolar transistor current, body source voltage and a weak multiplication ionization factor as variables; four key physical processes of collision ionization, body charge accumulation, body bias effect and parasitic transistor conduction and interaction thereof are integrated in the model completely and explicitly, so that the model ensures the prediction completeness from the physical mechanism; therefore, the complex warping effect of the silicon-on-insulator device under high drain-source voltage can be simulated with high precision, and an accurate device model basis is provided for the design of a high-performance and high-reliability integrated circuit.

The present invention suppresses the operation of a parasitic bipolar transistor during recovery switching, and achieves both low loss and high recovery resistance. A gate-controlled diode 101 includes: a first semiconductor layer 1 of a first conductivity type; a second semiconductor layer 2 of the first conductivity type in which the impurity concentration is lower than in the first semiconductor layer 1; a third semiconductor layer 3 of a second conductivity type; a fourth semiconductor layer 4 of the second conductivity type in which the impurity concentration is higher than in the third semiconductor layer 3; a fifth semiconductor layer 5 of the second conductivity type in which the impurity concentration is higher than in the fourth semiconductor layer 4; a sixth semiconductor layer 6 of the first conductivity type; a first electrode 11; a second electrode 12; a gate insulating film 23; and a gate electrode 22. The second electrode 12 has a protruding part 12A in contact with the fifth semiconductor layer 5 and the sixth semiconductor layer 6. The fourth semiconductor layer 4 is in contact with the fifth semiconductor layer 5 and the gate insulating film 23. The fourth semiconductor layer 4 and the sixth semiconductor layer 6 are disposed so as not to overlap in a plan view.