24 results about "Conductivity modulation" patented technology

This invention provides a bidirectional transient voltage suppressor with low dynamic resistance and high surge capability, comprising: a heavily doped semiconductor substrate of a first conductivity type; a first epitaxial layer disposed on the substrate; a conduction modulation buried layer disposed on the first epitaxial layer; a second epitaxial layer disposed on the conduction modulation buried layer; a heavily doped first conductivity type region disposed on the second epitaxial layer; a first electrode disposed on the front side of the heavily doped first conductivity type region and a second electrode disposed on the back side of the substrate; the conduction modulation buried layer is disposed inside the double epitaxial body region and is configured to form a high-concentration conductivity modulation region of charge carriers under transient high current impact conditions, forming a body region-dominated conduction path between the first epitaxial layer and the second epitaxial layer, so that the conduction current changes from concentrated conduction in the PN junction region to a laterally extended and planar distributed overall conduction mode within the body region, thereby reducing the dynamic resistance of the device and improving the surge carrying capacity of the device.

This invention belongs to the field of semiconductor technology, specifically providing a gallium oxide insulated-gate bipolar transistor (IGBT) power device, including a vertical device and a horizontal device. This invention uses nickel oxide, copper oxide, or diamond as the P-type region, forming a heterojunction structure with N-type gallium oxide. During device operation, the heterojunction on the high-potential side is forward-biased, allowing a large number of holes to be injected into the N-type gallium oxide drift region. This introduces a conductivity modulation effect in the drift region, achieving high current density and low on-state voltage drop, thus realizing the basic working principle of the IGBT device. Simultaneously, the horizontal IGBT introduces P-type nickel oxide or diamond with N-type gallium oxide to form a superjunction structure with a high-voltage drift region, achieving higher breakdown voltage with the same drift region length, thus improving device performance. In summary, this invention, based on the principle of heterojunction, proposes the concept of gallium oxide IGBT for the first time, providing a new approach for the research of gallium oxide high-voltage, high-current power devices.

The invention belongs to the technical field of semiconductors, and relates to a GaN HEMT device with an adjustable threshold voltage structure. A PNP triode structure is introduced into a grid electrode of the device, an N-end extraction electrode serves as a threshold value control electrode, and a P-end extraction electrode on the topmost layer serves as the grid electrode. The gate voltage of the whole device must exceed the threshold value control electrode voltage and the opening voltage of the top PN junction, so that the channel of the device can be opened. Meanwhile, due to hole injection brought by the BJT structure, the structure of the invention also has a conductivity modulation effect, the transconductance of the device can be improved, and the grid control capability can be enhanced. The device is provided with the externally given threshold control electrode, so that the device can realize adjustable threshold voltage, and different threshold voltages can be realized by applying different voltages through the threshold control electrode.

A control system to control a conductivity modulation device of a power switch array. The control system includes: a system controller to receive an indication indicating that the system controller is to adjust a driving characteristic of the conductivity modulation device, and to output a command signal; and a switch controller configured to receive the command signal and control energy delivery to the load by controlling on and off of the conductivity modulation device. The switch controller comprises an adjustable driving element, an interface and a driving characteristic control device; the adjustable driving element is used for controlling rising time and / or falling time of voltage on the conductivity modulation device; an interface coupled to the system controller and configured to receive and interpret the command signal and output a drive characteristic signal, the driving characteristic control device is used for receiving a driving characteristic signal and changing the driving characteristic by controlling the adjustable driving element in response to the driving characteristic signal so as to adjust the rising time and / or the falling time of the voltage on the conductivity modulation device.

This application discloses an IGBT structure and semiconductor device. The IGBT structure includes: a substrate, a drift region of a first conductivity type, a collector region of a second conductivity type, an active gate, a body region of a second conductivity type, a first doped region of a second conductivity type, an emitter region of a first conductivity type, and a second doped region of a second conductivity type. The active gate extends from a first main surface to a second main surface into the drift region. The first doped region and the body region are respectively disposed on both sides of the active gate and are located on the side of the drift region facing the first main surface. The emitter region is located on the side of the body region facing the first main surface and is located between two adjacent active gates. The emitter region includes a first emitter region and a second emitter region, and the first emitter region and the second emitter region respectively cover at least partially the first body region and the second body region. The doping concentration of the second doped region is greater than the doping concentration of the body region. According to the IGBT structure and semiconductor device of this application, conductivity modulation caused by narrow mesa between active gates can be effectively avoided, thus preventing the CIBL effect.

The present application provides a method for fabricating an RC-IGBT cell and an RC-IGBT chip. The fabrication method includes: processing a semiconductor substrate and forming a gate composed of an oxide layer and polysilicon thereon; etching a plurality of hole regions in the middle of the gate; injecting N+ emitters in the hole regions through a photomask with a preset structure, wherein the region where the N+ emitters are injected is the IGBT region, and the region where the N+ emitters are not injected is the FRD region. The fabrication method provided by the present application segments the strip gate, etches a plurality of hole regions in the middle of the gate, and uses a photomask with a preset structure to rationally layout the positions of the N+ emitters in the hole regions, enabling the diode part not short-circuited by the channel to enter the conductivity modulation state first, effectively reducing VF, and optimizing VF-shift.

The invention relates to a power semiconductor technology, in particular to an IGBT (Insulated Gate Bipolar Translator) device integrated with an MOS (Metal Oxide Semiconductor) controlled floating Schottky diode and a preparation method. Compared with a previous Floating P-body IGBT structure, the IGBT provided by the invention has the advantages that an MOS (Metal Oxide Semiconductor) is embedded into an emitter end to control two floating Schottky diodes (a P-type Schottky diode and an N-type Schottky diode) which are connected in series; when the device is in a forward conduction state, the potential of the floating P-type region is smaller than the sum of the turn-on voltages of the two floating Schottky diodes, carrier injection can be further enhanced, carrier distribution can be further optimized, the conductivity modulation effect of the device is further enhanced, and therefore the conduction loss of the device is reduced. When the device is in a short-circuit tolerance state, the voltage at the collector electrode end and the emitter electrode end of the device is large, at the moment, the potential of the floating P-type region is larger than the sum of the starting voltages of the two floating Schottky diodes, holes in the device body disappear through floating metal compounding, the saturation current of the device is reduced, and the short-circuit tolerance capacity of the device is improved.

The invention provides a novel RC-IGBT structure with a hole circulation path and a good compromise relationship, which comprises a device main body, collector metal is arranged at the bottom of the device main body, a p + collector region, an FS layer, an n-drift region, a groove with a grid electrode at the top, an n + emitter region, a p + contact region and a p base region are sequentially arranged upwards, a second CS storage layer is arranged at the bottom, and the emitter composite structure on the two sides comprises a deep p-type region, a deeper p-type region, a hole channel and a CS storage layer. Through the above structure, the deep p-type region and the deeper p-type region optimize the electric field distribution, improve the doping concentration of the CS layer, enhance the hole accumulation effect, reduce the conduction voltage drop, accelerate the carrier export during the turn-off of a hole channel, and shorten the turn-off time, and at the same time, under the short-circuit working condition, the structures cooperatively export holes, weaken the conductivity modulation effect, improve the short-circuit endurance capability, and improve the performance of the device. And finally, good balance of voltage resistance, conduction voltage drop and switching speed is realized, and the comprehensive performance of the device is remarkably improved.

This invention discloses a Schottky diode and its fabrication method. The Schottky diode includes an N-type epitaxial layer and a barrier metal layer stacked sequentially from bottom to top. A trench extending in the front-back direction is formed on the upper side of the N-type epitaxial layer. The trench is filled with a channel structure, which includes a gate oxide layer, two polysilicon layers located on both sides of the gate oxide layer, and two lightly doped P-type layers located on both sides of the two polysilicon layers. A heavily doped P-type layer connected to the lightly doped P-type layer is provided on the upper side of the N-type epitaxial layer, and the heavily doped P-type layer is in contact with the barrier metal layer. The Schottky diode provided by this invention utilizes the ohmic contact formed by the heavily doped P-type layer and the barrier metal layer, and the lightly doped P-type layer as a conductivity modulation layer, which greatly improves the surge resistance of the device without affecting the switching characteristics of the Schottky diode.

The invention discloses a unidirectional anti-surge circuit and device. The unidirectional anti-surge circuit comprises a bidirectional TVS diode and a unidirectional diode. The bidirectional TVS diode comprises a P-type substrate, the P-type substrate comprises a first surface and a second surface which are oppositely arranged, and the first surface and the second surface are respectively diffused to form a first N-type diffusion region and a second N-type diffusion region and are respectively electrically connected with a first node and a second node; the unilateral diode comprises an anode and a cathode, the anode is electrically connected with the first node, and the cathode is electrically connected with the second node; when the voltage difference between the second node and the first node is larger than or equal to the breakdown voltage of the bidirectional TVS diode, electrons in the first N-type diffusion region or the second N-type diffusion region enter the P-type base region, and then conductance modulation is carried out on the P-type base region. The bidirectional TVS diode capable of generating the conductivity modulation effect is connected with the unidirectional diode in parallel, so that the unidirectional voltage hysteresis function is realized, and the clamping voltage of the unidirectional anti-surge circuit is further reduced.

The invention discloses a full-light-control reconfigurable logic device based on a zinc oxide / perovskite core-shell microwire and a preparation method thereof, the full-light-control reconfigurable logic device comprises a ZnO microwire as a core, a perovskite shell layer and indium particles, the ZnO microwire is fixed on quartz glass in a suspended manner through the indium particles, and the ZnO microwire is wrapped by the perovskite shell layer; conductivity modulation is carried out on a light gating effect of a ZnO channel through a perovskite shell layer, a negative photoconductive effect is presented during visible light irradiation, a negative photoconductive effect is presented during weak ultraviolet light irradiation, and a positive photoconductive effect is presented during strong ultraviolet light irradiation; the basic current of a device is adjusted by changing the wavelength and power of modulated light, different logic gate functions (OR, AND, NOR, NOT and NAND) are realized, the basic logic gate function with complete functions is realized on a single device, and the integration level of the device is increased to a great extent.

The invention discloses a conductivity modulation enhanced III-nitride electronic device and a preparation method thereof. The device comprises a PN junction and a light reflection structure, the PN junction comprises a first conductive characteristic region and a second conductive characteristic region which are in direct contact, the conductive characteristics of the first conductive characteristic region and the second conductive characteristic region are opposite, the first conductive characteristic region is located on a first surface, inclined table surfaces are arranged on the two sides of the first surface, and the normal directions of the inclined table surfaces point to the direction in the PN junction; the light reflection structure comprises a first reflection layer, and the first reflection layer covers the first face and covers the inclined table face in a profiling mode. According to the invention, the inclined mesa is matched with the light reflecting layer, so that escaping photons are reflected back to the semiconductor structure, the conductivity modulation phenomenon is enhanced, and the effects of greatly enhancing the conductivity modulation phenomenon of the device and improving the anti-surge characteristic of the device are realized while the reverse electrical characteristic of the device is not influenced.

The invention relates to a power semiconductor technology, in particular to an IGBT (Insulated Gate Bipolar Translator) device integrated with a self-biased floating Schottky diode and a preparation method. Compared with a previous Floating P-body IGBT structure, according to the IGBT provided by the invention, a floating self-biased P-type Schottky diode and an N-type Schottky diode which are connected in series are embedded in a P-body, and the anode of the P-type Schottky diode of the device is connected with the anode of the N-type Schottky diode through floating metal; when the potential of the floating P-type region is greater than the sum of the turn-on voltages of the two floating Schottky diodes, the floating P-type region provides a conduction path for hole current to reduce saturation current, the short-circuit endurance capability of the device is improved, and the extraction of holes from the device body is accelerated to improve the turn-off loss of the device; and when the potential of the floating P-type region is smaller than the sum of the turn-on voltages of the two floating Schottky diodes, the conductivity modulation effect is further enhanced, so that the conduction capability is improved.

An insulated gate bipolar transistor capable of reducing turn-off loss relates to the technical field of semiconductor power devices, introduces a P-type injection layer to replace a part of an N-type layer to form a new carrier storage layer compared with a traditional device cellular structure, and effectively provides a new design scheme for structural adjustment of conduction saturation voltage and turn-off loss. According to the newly introduced P-type carrier storage layer, when the insulated gate bipolar transistor is switched on at + 15V of the gate, accumulation of carriers (holes) can be realized from a P-type layer to an N-type layer, so that the conductivity modulation effect is enhanced, and the conduction saturation voltage is reduced. The newly introduced P-type carrier storage layer can be changed into a P-type layer from P-when the insulated gate bipolar transistor is turned off at the gate of-5V / -8V, so that the extraction of carriers (holes) during turn-off is enhanced, the accumulation of the carriers (holes) is reduced, the turn-off time is shortened, the tail current is reduced, and the turn-off loss is reduced.

The present invention belongs to the technical field of power semiconductor devices and relates to a self-biased split-insulated gate bipolar transistor with a full-trench structure and a method for manufacturing the same. The present invention uses layout routing to lead out the floating P-region potential in the transition region, and integrates the diode and capacitor through module packaging, so that C is connected in series between the split gates 11-1, 11-2, 11-3, 11-4, 11-5, 11-6 and the emitter metal 1. The floating P-region potential is used to charge the capacitor when the device is blocked, thereby providing a bias potential for the split gate. Therefore, the split gate also has a stable potential. This potential attracts electrons near the split gate to accumulate and form an electron accumulation layer. This accumulation layer improves the injection efficiency of the channel, further enhances the drift region conductivity modulation effect, and reduces the forward conduction voltage drop of the device.

The invention discloses a conductivity regulation and control method for semiconductor heterojunctions with different crystal orientations, and the method comprises the steps: obtaining the electrical energy band structures of two materials with different crystal orientations through employing a first principle calculation method, and calculating the effective mass of semiconductor materials with different crystal orientations; adopting a first principle calculation method to obtain conduction band orders of the two materials in different crystal orientations; solving the channel carrier concentration in the heterojunction composed of the two materials under different crystal orientations by combining a Schrodinger-Poisson equation; constructing a scattering mechanism of channel carriers in the heterojunction formed by the two materials under the different crystal orientations, and calculating the mobility of the channel carriers in the heterojunction formed by the two materials under the different crystal orientations; and according to the calculation model of the channel carrier concentration and mobility, obtaining the regulation and control method of the channel carrier conductance in the heterojunction composed of the two materials under different crystal orientations. According to the method, the relation between the physical parameters and the crystal orientation of the semiconductor heterojunction is extracted, efficient regulation and control of multi-system heterojunction conductivity are achieved, the model calculation amount is small, and universality is high.

The invention provides a charge throttling layer structure and method for reducing on resistance of a high-power high-voltage device. The charge throttling layer structure comprises a substrate, a charge throttling layer, an N + region and an oxide layer, the charge throttling layer, the N + region and the oxide layer are sequentially grown on the substrate from bottom to top; the charge throttling layer and the N + region are both doped regions, and the doping concentration of the N + region is larger than that of the charge throttling layer. In the manufacturing process of the high-voltage bipolar semiconductor power device, a multi-time and multi-step doping process (such as doping boron, phosphorus and aluminum impurities) is adopted, a charge throttling layer with specific concentration distribution is manufactured in a base region of the device, and the on-resistance of the base region of the device can be effectively reduced by enhancing the conductivity modulation effect in the conduction process of the device by the charge throttling layer, so that the on-resistance of the base region of the device is improved. And the heat accumulation of the device in the working process is reduced.

The invention provides a bidirectional transient voltage suppressor with low dynamic resistance and high surge capacity. The bidirectional transient voltage suppressor comprises a heavily doped first conductive type semiconductor substrate; the first epitaxial layer is arranged on the substrate; the conduction modulation buried layer is arranged on the first epitaxial layer; the second epitaxial layer is arranged on the conduction modulation buried layer; the heavily doped first conductive type region is arranged on the second epitaxial layer; the first electrode is arranged on the front surface of the heavily doped first conductive type region; the second electrode is arranged on the back surface of the substrate; the conduction modulation buried layer is arranged in the double epitaxial body region and is configured to form a carrier high-concentration conductivity modulation region under a transient large current impact condition, and a body region leading conduction path is formed between the first epitaxial layer and the second epitaxial layer; conduction current is converted from PN junction local area concentrated conduction into an integral conduction mode of transverse expansion and planar distribution in a body area range, so that the dynamic resistance of the device is reduced, and the surge bearing capacity of the device is improved.

This invention belongs to the field of power semiconductor technology, specifically relating to a trench gate-controlled composite power device with low on-state voltage and low switching losses. The device is a non-fully symmetrical composite structure, integrating an IGBT unit structure and a trench MOS gate-controlled thyristor (MCT) unit structure on the same semiconductor substrate. The device includes an anode structure, an electric field cutoff layer, an N-type drift region, a base region structure, a cathode structure, and a trench gate structure. The trench gate penetrates the base region and extends into the drift region, enabling the modulation of carriers in different regions. During conduction, the MCT structure triggers a PNPN conduction mechanism, enhancing the conductivity modulation effect and reducing the on-state voltage. During turn-off, the trench gate forms a carrier extraction channel within the N-type base region, accelerating minority carrier removal and thus reducing switching losses. This structure achieves synergistic optimization of conduction and switching performance by controlling the spatiotemporal distribution of carrier injection and extraction, making it suitable for high power density and high-frequency power electronics applications.

The utility model provides a groove type silicon carbide gate turn-off thyristor, which introduces a structure similar to a groove IGBT (Insulated Gate Bipolar Translator), changes the path of free carriers injected from a collector through an N + substrate to an emitter directly through an N-drift region, and enables the free carriers to pass through a gate path. In the process, minority carriers can be quickly removed, so that the switching loss is reduced, and the conductivity modulation effect of the N-drift region is enhanced. Wherein when the groove type SiC MCT works in a blocking state, gate-source voltage becomes zero potential or negative potential, a PN junction formed by a P type base region and an N-type drift region and an MOS structure formed between a gate electrode and the N-type drift region bear high voltage between a source and a drain, and the groove type SiC MCT has higher voltage endurance capability; when the device works in a forward conduction state, the P-base region can restrain a high electric field in the gate oxide layer, a strong conductivity modulation effect is achieved, and forward conduction voltage is reduced.

This invention discloses a quantum dot-modified flexible visual synaptic memristor and its fabrication method. The quantum dot-modified flexible visual synaptic memristor includes: a flexible substrate; a bottom electrode formed on the flexible substrate; a composite functional film composed of perovskite quantum dots and an organic ferroelectric polymer, formed on the bottom electrode; and multiple mutually spaced transparent top electrodes formed on the composite functional film. By applying light source signals and electrical pulse signals to the device, and utilizing the photoelectric response of the perovskite quantum dots and the conductivity modulation function of the ferroelectric polymer, the device simulates the light signal perception, data storage, and computation of an artificial vision system.

This invention discloses a silicon carbide MPS diode with high surge current, comprising a cathode ohmic contact electrode, a silicon carbide N+ substrate, and a silicon carbide N- epitaxial layer stacked sequentially. Multiple P+ injection regions are spaced apart on the silicon carbide N- epitaxial layer, and ohmic contact electrodes are disposed on the P+ injection regions. The gaps between the ohmic contact electrodes are filled with Schottky contact electrodes. Bipolar transport layers are disposed on both sides of the silicon carbide N- epitaxial layer. Due to the presence of the variable-doped bipolar transport layers, the PN junction forward voltage of the MPS diode is reduced, allowing the diode to enter the bipolar operating state earlier at a lower current. This results in a conductivity modulation effect, reducing the diode's on-resistance and lowering the chip temperature under high current, thereby improving the diode's surge current resistance and reverse breakdown voltage.

According to the SiC IGBT device and the preparation method thereof, heterojunction polycrystalline silicon is introduced into the front surface structure of the device, a polycrystalline silicon-SiC heterojunction is formed at the junction of the heterojunction polycrystalline silicon and a semiconductor layer, and due to the fact that the forbidden band width of the heterojunction polycrystalline silicon and the semiconductor layer is large, an energy band is bent downwards to form a large potential barrier on one side of SiC, and the energy band is bent downwards to form a large potential barrier on the other side of SiC. The potential barrier bent downwards inhibits holes from flowing out of the device through the emitter, in order to maintain electric neutrality, the holes induce electrons, the conductivity modulation effect is improved, and the conduction voltage drop is reduced. Meanwhile, when the device is turned off from turning on, the voltage of the drain electrode is further increased, the voltage is loaded to the heterojunction, the bent energy band is flattened, and the valence band of the polycrystalline silicon is higher than that of SiC, so that holes can flow into the polycrystalline silicon and finally flow out of the device through the emitter, the formation of trailing current is inhibited, and the device can be turned off quickly. That is to say, the turn-off characteristic can be improved while the forward conduction voltage drop of the device is reduced.

The invention discloses a reconfigurable memristor based on a two-dimensional covalent organic framework and a preparation method and application thereof.The memristor comprises a bottom electrode, a covalent organic framework-based active film layer and a top electrode which are sequentially arranged in a stacked mode, and the covalent organic framework-based active film layer is prepared by condensing 1, 3, 5-tri (4-aminophenyl) benzene and [1, 1 ': 4', 1 ''-terphenyl]-4, 4 ''-dicarboxaldehyde. According to the memristor, the covalent organic framework-based active film layer made of a specific material is adopted, so that reconfigurable switching between a synaptic mode and a pain neuron mode in the same device under different electrical regulation and control conditions is realized, and stable analog conductivity modulation and multi-level storage can be realized in the synaptic mode; threshold triggering and quick response can be achieved in a pain neuron mode, and a high-integration-level and low-power-consumption device implementation scheme is provided for an end-side neuromorphic hardware system.