9results about How to "Reduce conduction voltage drop" patented technology

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, at least two super junction structure layers arranged on one side of the substrate, wherein the super junction structure layer comprises P-type strip buried regions and N-type strip buried regions which are arranged alternately and have the same extending direction, and the extending directions of the P-type strip buried regions in adjacent super junction structure layers are different; and an N-type buried layer arranged between the adjacent super junction structure layers. The longitudinal super junction structure layer is added, so that the withstand voltage performance of the whole device is improved, and the super high voltage super junction IGBT is realized. The N-type buried layer is arranged, so that the outflow of holes is prevented. The accumulation of holes appears below the N-type buried layer. When the number of holes is greater than that of electrons, the area cannot maintain charge balance, more electron current is injected into the area by the emitter, the concentration of carriers locally increases, and the reduction of on-state voltage drop is realized.

The invention discloses a silicon carbide diode structure, a chip structure and a preparation method thereof. Each of the diode structure and the chip structure comprises a cathode metal and an N + type silicon carbide substrate above the cathode metal, and a first N-type silicon carbide epitaxial layer, a second N-type silicon carbide epitaxial layer and a P + type shielding region are sequentially arranged above the N + type silicon carbide substrate; one end, far away from the N + type silicon carbide substrate, of the second N-type silicon carbide epitaxial layer is provided with a longitudinal step groove, the longitudinal step groove penetrates through the second N-type silicon carbide epitaxial layer and a part of the first N-type silicon carbide epitaxial layer, and the side wall and the bottom of the step groove are coated by anode metal. The chip structure further comprises a plurality of cellular structures which are provided with the layers and are different in structure. According to the invention, under the condition of not increasing the area of an active region chip, the Schottky contact area can be obviously increased, the conduction loss of the device is reduced, and the anti-surge capability of the device is improved.

The application discloses a GPP rectifier diode chip with a gradient-doped composite glass passivation layer, and belongs to the technical field of semiconductor devices. The GPP rectifier diode chip with the gradient-doped composite glass passivation layer comprises a base substrate, a gradient diffusion zone and a composite glass passivation layer. The application solves the problems of poor interface charge stability, large leakage current and insufficient long-term reliability of a conventional single-layer or multi-layer glass passivation layer of an existing GPP rectifier diode chip. The first gradient distribution of the resistivity of the base substrate along the thickness direction, the second gradient distribution of the impurity concentration of the gradient diffusion zone surface along the transverse direction and the composite glass passivation layer with periodic fluctuation of carbon content inhibit the concentration effect of the junction edge electric field, improve the interface matching property and compactness of the passivation layer and the semiconductor surface, thereby reducing the leakage current, and improving the voltage resistance and long-term working stability of the device.

This invention relates to the field of electrical technology, and more particularly to a flyback switching power supply absorption circuit, a transformer leakage inductance absorption method, and a chip. The circuit includes: a transformer comprising a primary winding NP and a secondary winding NS; a primary sub-circuit comprising an energy storage branch connected to the primary winding NP and an absorption branch connected to the primary winding NP, wherein when the energy storage branch is on, the primary winding NP stores energy, and when the absorption branch is on, it absorbs the leakage inductance energy of the transformer; and a secondary sub-circuit connected to the secondary winding NS, wherein when the secondary winding NS is on, it provides an output voltage VOUT to the load connected to the secondary winding NS. This invention can solve the problem of low power conversion efficiency. By absorbing leakage inductance energy through the absorption branch for use by the load connected to the secondary sub-circuit, the power conversion efficiency can be improved.

The invention discloses a driving circuit, a driving method and driving equipment of a switch assembly and a storage medium. The switch assembly comprises an MOS (Metal Oxide Semiconductor) and an IGBT (Insulated Gate Bipolar Translator), the driving circuit comprises a microcontroller which is respectively connected to a grid electrode of the MOS and a grid electrode of the IGBT, and the microcontroller is configured to control the MOS to be switched on and control the IGBT to be switched off when a working current is smaller than a first current threshold value, so that the working current passes through the MOS; when the working current is larger than or equal to the first current threshold value and smaller than the second current threshold value, the MOS is controlled to be firstly switched on and then switched off relative to the IGBT, so that the working current passes through the MOS and the IGBT which are connected in parallel; and when the working current is greater than or equal to the second current threshold value, controlling the IGBT to be switched on firstly and then switched off relative to the MOS, so that the working current passes through the MOS and the IGBT which are connected in parallel. According to the driving circuit of the switch assembly, different driving modes are implemented according to different current ranges of the working current, the switch device is protected, and the working efficiency of the switch device is improved.

The utility model provides a kind of bidirectional gallium nitride T type three-level power module and circuit board, wherein, upper bridge arm switch device, midpoint bidirectional switch device and lower bridge arm switch device are all bidirectional gallium nitride power switch;The first drive reference pin of upper bridge arm switch device is connected direct current positive bus;The first drive reference pin of midpoint bidirectional switch device and the first drive reference pin of lower bridge arm switch device are connected to the second drive reference pin of upper bridge arm switch device;The first drive reference pin of midpoint bidirectional switch device and the first drive reference pin of lower bridge arm switch device are also connected to the second drive reference pin of upper bridge arm switch device;The second drive reference pin of midpoint bidirectional switch device is connected direct current neutral line;The second drive reference pin of lower bridge arm switch device is connected direct current negative bus, can reduce the quantity of power tube, reduce conduction loss.

The application discloses a kind of multistage trench multi-channel integrated schottky diode's MISFET, comprising: gallium oxide substrate, drain, gallium oxide epitaxial layer, source;Gallium oxide epitaxial layer upper portion is equipped with including M≥2 level sub-trench multistage trench, the opening distance of first level sub-trench to M level sub-trench successively reduces;High resistance zone is equipped in gallium oxide epitaxial layer between multistage trench and the bottom of multistage trench, and N type low resistance zone is equipped on high resistance zone except the bottom of M level sub-trench;Schottky diode is integrated in M level sub-trench;Sub-trench bottom and sidewall except M level are deposited with gate dielectric layer, gate electrode is deposited on the surface of gate dielectric layer, and gate electrode and source are covered with interlayer dielectric layer.The application reduces the electric field at the surface of device, reduces the dependence of device on gate dielectric material thickness, while reducing the forward conduction resistance and third quadrant conduction resistance of device, improves the voltage resistance and reliability of gallium oxide MISFET device.

The invention provides a bus fault protection circuit, and relates to the technical field of integrated circuits, the bus fault protection circuit comprises a power supply end, a bus pin end, a comparator, a first voltage sampling circuit, a second voltage sampling circuit and an output driving branch; the output driving branch comprises an output driving tube and a protection transistor; the first voltage sampling circuit, the second voltage sampling circuit and the comparator are configured as follows: when the voltage value of the bus pin end is smaller than or equal to the voltage value of the power supply end, the output end of the comparator outputs a first level signal to the control electrode of the protection transistor based on the comparison result of the first sampling voltage and the second sampling voltage; the protection transistor is driven to be conducted; when the voltage value of the bus pin end is larger than the voltage value of the power supply end, the output end of the comparator outputs a second level signal to the control electrode of the protection transistor based on the comparison result of the first sampling voltage and the second sampling voltage so as to drive the protection transistor to be turned off, and fault high-voltage protection can be effectively carried out on the transmitter bus.

The application provides a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a back layer of a first conductive type which is composed of a buffer layer of the first conductive type and a freewheeling heavy doped region of the first conductive type under the deep trench field plate, a trench gate and a deep trench field plate which penetrate a body region of a second conductive type and extend into a substrate layer of the first conductive type; and the trench gate which also penetrates the heavy doped region of the first conductive type has a depth smaller than that of the deep trench field plate. The deep trench field plate which is short-circuited with the emitter and arranged on both sides of the trench gate can accumulate a large number of holes when the deep trench field plate is turned on, so that the on-state voltage drop is reduced. Meanwhile, the deep trench field plate optimizes the compromise relationship between the FRD breakdown voltage and the on-state voltage in the RC-IGBT with a vertical electric field distribution, so that the working loss of the RC-IGBT in the freewheeling state is reduced. In addition, the deep trench field plate can quickly extract the carriers in the depletion layer in the freewheeling state, so that the current released in the reverse recovery is reduced, and the peak current in the reverse recovery is reduced.