350results about How to "Reduce conduction voltage drop" patented technology

A method for producing a pn-junction for a semiconductor device of SiC intended to have at least one lateral zone of junction termination with a lower doping concentration of a first conductivity type than a main zone for smearing out the electrical field at said junction comprising at least the step of applying a first layer of SiC over the entire surface and on top of a second layer of SiC. A mask is applied on the first layer over a portion thereof where said main zone and an ohmic contact are to be formed. It is after that etched through the first layer to the second layer while leaving a main zone of said first layer and a contact layer thereof under said mask.

The invention discloses an integrated bootstrap high voltage driving chip and a technological structure thereof. Parasitic high voltage diodes realized by the integration technology in a high voltage level shift circuit are ingeniously utilized to charge a bootstrap capacitor, wherein the power terminal of the high voltage level shift circuit is a high side floating power supply VB, and the reference ground is floating voltage PGD. The PGD is controlled by a bootstrap control circuit. A first parasitic diode and a second parasitic diode are arranged between the VB and the PGD. The bootstrap control circuit is controlled by a high side signal and a low side signal. When the low side output signal LO is high level and the high side output signal HO is low level or the low side output signal LO is low level and the high side output signal HO is low level, the output PGD of the bootstrap control circuit is high level VCC. The VCC performs unidirectional charging to an external bootstrap capacitor through the first parasitic diode and the second parasitic diode. The integrated bootstrap high voltage driving chip is high in charging speed, high in charging efficiency, simple in circuit structure and low in cost.

The invention discloses a multi-level voltage source current converter comprises at least one phase unit. Each phase unit comprises an upper bridge arm, a lower bridge arm and a current conversion electric reactor, wherein the upper bridge arm and the lower bridge arm respectively comprise at least two sub-modules, a switch loop and a bridge arm electric reactor all of which are sequentially connected in series; all sub-modules in the same bridge arm are connected in series in the same direction; the sub-modules, connected with the switch loop, in the upper bridge arm are opposite to the sub-modules, connected with the switch loop, in the lower bridge arm in polarity; one end, connected with the electric reactor in series, of the upper bridge arm and one end, connected with the electric reactor in series, of the lower bridge arm are connected and have access to an alternating current network through the current conversion electric reactor; the other end of the upper bridge arm and the other end of the lower bridge arm serve as a first direct current endpoint and a second direct current endpoint of the phase unit respectively to have access to a direct current network. Each switch loop comprises a plurality of anti-parallel thyristor pairs which are connected in series. The multi-level voltage source current converter is applied to flexible direct-current transmission and the like, and has the advantages of being small in number of the sub-modules, low in cost, small in consumption, capable of effectively blocking fault currents when the direct current side breaks down, and the like. The invention further discloses a control method of the multi-level voltage source current converter.

An anode-short tunnel pump IGBT belongs to the technical field of semiconductor power devices. With an anode-short structure and a tunnel pump structure simultaneously introduced into a traditional IGBT, or a tunnel pump structure into an anode-short IGBT, or an anode-short structure into a tunnel pump IGBT, the invention gives the advantages of both the anode-short IGBT and the tunnel pump IGBT to the anode-short tunnel pump IGBT so as to improve the turn-off characteristic of the device and lower the conductive voltage drop of the device. The invention can better reconcile the positive saturation voltage drop with the turn-off time, and optimize the conductive characteristic of the device, so that the invention is suitable in particular for application environments characterized by high voltage, heavy current and high frequency.

The invention discloses a T-shaped multi-level inverter circuit based on reverse blocking IGBT (Insulated Gate Bipolar Transistor) antiparallel connection. The T-shaped multi-level inverter circuit comprises a two-way controllable switch (1), a power device (2) and a direct-current capacitor (3); the two-way controllable switch (1) comprises a plurality of reverse blocking IGBTs which are in antiparallel connection with each other in pairs; one side of a connecting wire of the reverse blocking IGBTs in antiparallel connection with each other in pairs after being connected in parallel is connected with a power switch tube, while the other side of the connecting wire is connected with the direct-current capacitor (3). The T-shaped multi-level inverter circuit is characterized in that after the reverse blocking IGBTs are in antiparallel connection with each other to form the two-way controllable switch, the antiparallel reverse blocking IGBTs are connected at the midpoints of a plurality of series capacitors without increasing the conduction loss, and then a plurality of midpoint voltage clamping circuits to realize five-level outputs, and with the increase of the number of output levels, the harmonic distortion of an output voltage is improved, the desired filter inductance is lower or the switching frequency can be reduced accordingly.

A semiconductor device includes a semiconductor substrate with: a drift layer; a base layer; and a collector layer and a cathode layer. In the semiconductor substrate, when a region operating as an IGBT device is an IGBT region and a region operating as a diode device is a diode region, the IGBT and diode regions are arranged alternately in a repetitive manner; a damaged region is arranged on a surface portion of the diode region in the semiconductor substrate. The IGBT and diode regions are demarcated by a boundary between the collector and cathode layers; and a surface portion of the IGBT region includes: a portion having the damaged region at a boundary side with the diode region; and another portion without the damaged region arranged closer to an inner periphery side relative to the boundary side.

The invention discloses a plane gate type IGBT (Insulated Gate Bipolar Translator) chip production method. The method comprises the steps: firstly carrying out front side processing, and injecting and annealing a second N type current carrier buried layer to a semiconductor substrate; etching, injecting and annealing a first N type current carrier buried layer injection window; etching a first N type current carrier buried layer; removing an oxidization layer on the surface of the semiconductor substrate; depositing an insulating material on the outer surface of the first N type current carrier buried layer, and photoetching and etching the deposited insulating material to form a media buried layer; completing the remaining front side processing technology; conducting back side processing, thinning the back side part to the needed thickness; injecting, doping and propelling and annealing an N buffer layer; injecting, doping and propelling and annealing a P+ collector electrode region; and producing a metal collector electrode. According to the plane gate type IGBT chip production method, the drop voltage of an IGBT chip is reduced, the compromise relation of the turn-off loss can be optimized, and lower power consumption can be realized, so that the power density, operating junction temperature and reliability of the IGBT chip can be improved.

The invention belongs to the technical field of power semiconductor devices, and relates to a diode with a floating island structure. The diode comprises an N-type semiconductor substrate, a cathode arranged at the bottom of the N-type semiconductor substrate, an N-type semiconductor drift region arranged on the upper layer of the N-type semiconductor substrate, a gate oxide layer arranged on the upper layer of the N-type semiconductor drift region, and an anode arranged on the upper layer of the gate oxide layer, wherein the gate oxide layer is of a trench gate structure, and an N-type semiconductor region is arranged between the portions, on the two sides of a trench, of the gate oxide layer. The diode is characterized in that a plurality of doping regions including P-type semiconductor doping regions are arranged in the N-type semiconductor drift region, and therefore the floating island structure is formed. The diode has the advantages that conductive voltage is reduced, the reverse recovery time is short, and the temperature characteristic is good. The diode is particularly suitable for trench type diodes.

Disclosed is a semiconductor device. The semiconductor device comprises at least one cell, and the structure of any cell comprises an N-type substrate, at least one N-type carrier barrier region, andat least one P-type electric field shielding region, wherein at least one first groove unit and at least one second groove unit are included on one side of the N-type substrate; at least one P-type semiconductor region is arranged on the other side of the N-type substrate, wherein the P-type semiconductor region is referred to as an anode region. The invention aims to provide the semiconductor device, wherein the semiconductor device has a novel cellular structure so as to obtain a large safe operating area, and the anti-short-circuit capability; the effect of a parasitic thyristor is eliminated; the low-grid-collector charges (QGC) are adopted to obtain the maximum anti-dv/dt capability; the emitter side electric conduction modulation is added, so that a relatively large current density and an extremely low conducting voltage drop can be obtained; and relatively turn-off loss and relatively low process complexity are achieved.

A trench gate IGBT designed to reduce on-state voltage while maintaining the withstand voltage, including a first drift layer formed on a first main surface of a buffer layer, a second drift layer of the first conductivity type formed on said first drift layer, a base layer of a second conductivity type formed on the second drift layer, an emitter layer of the first conductivity type selectively formed in the surface of the base layer, and a gate electrode buried from the surface of the emitter layer through into the second drift layer with a gate insulating film therebetween, wherein said first drift layer has a structure in which a first layer of the first conductivity type and a second layer of the second conductivity type are repeated in a horizontal direction.

The invention discloses a method for manufacturing a trench gate type IGBT (insulated gate bipolar transistor) chip, which comprises the following steps: selecting two N-shaped semiconductor substrates, and carrying out oxidation or deposition on one of the substrates, so that insulating materials including silicon oxides or nitric oxides are formed on the surface of the substrate; carrying out photoetching and etching on the insulating materials on the surface of the substrate so as to form a dielectric buried layer; carrying out photoetching and etching on the other substrates so as to form a figure coincided with the concave-convex surface of the dielectric buried layer; carrying out concave-convex surface butt-joint on the dielectric buried layer and the figure, and bonding the two substrates together at high temperature; according to voltage-withstanding requirements and machining allowances, respectively carrying out thinning processing on the two substrates, and controlling the dielectric buried layer at a design depth, so that a chip manufacturing intermediate is formed; and completing the manufacturing process of a trench gate type IGBT chip. According to the invention, the drop voltage of the chip is reduced, a compromising relation with shut-off loss is optimized, and the lower power consumption is realized, thereby improving the power density, operating junction temperature and reliability of the IGBT chip.

The invention discloses a planar gate IGBT (Insulated Gate Bipolar Transistor) chip, which comprises a collector metal electrode, a P+ collector region, an N- drift region, a P- base region, a P+ ohmic contact region, an N+ source region, a gate oxide layer, a polysilicon gate and a gate metal electrode which are arranged successively, and an emitter metal electrode arranged above the P+ ohmic contact region, wherein the polysilicon gate of the planar gate IGBT chip adopts a planar gate structure. The planar gate IGBT chip also comprises a first N-type carrier buried layer and/or a second N-type carrier buried layer. The first N-type carrier buried layer is located below the P- base region. The second N-type carrier buried layer is located below the gate oxide layer and at both sides of the P- base region. The planar gate IGBT chip has the beneficial effects that the compromise relation between conduction pressure drop and turn-off loss of the IGBT is reduced, lower power consumption is realized, and thus the power density, the operating junction temperature and the long-term reliability of the IGBT chip are increased.

A super-junction IGBT device comprises a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed in a horizontal direction. Device cell structures are formed at tops of super-junction cells and each comprise a trench gate having a gate trench striding across an interface of the corresponding P-type pillar and the corresponding N-type pillar. A body region is formed at a top of the corresponding N-type pillar, and a source region is formed on a surface of the body region. The top of each N-type pillar is provided with one body region and two trench gates located on two sides of the body region, and each body region is isolated from the P-type pillars on the two sides of the body region through the corresponding trench gates. The invention further discloses a method for manufacturing a super-junction IGBT device. Self-isolation of the P-type pillars is realized, the on-state current capacity of the device is improved, and the on-state voltage drop of the device is reduced.

The invention discloses a main and backup power supply fault detection and automatic switching control circuit which comprises a main module power supply and a backup module power supply, wherein the main module power supply and the backup module power supply are connected in parallel with each other; the output ends of the main module power supply and the backup module power supply are both cascaded with isolation circuits of completely identical circuit structures, so that parallel redundancy between two modules of a power supply is realized; the main and backup power supply fault detection and automatic switching control circuit can monitor working states of the main and backup power supplies in real time and realize automatic fault detection and switching between the power supply modules; compared with the conventional relay-control main and backup switching circuit, the main and backup power supply fault detection and automatic switching control circuit has the advantages that the mechanical design difficulty of the module power supplies is reduced, and the reliability of the module power supplies is improved; and the main module power supply and the backup module power supply are mutually controlled, so that the requirement that the main power supply is powered on first under a condition that the module power supplies work normally is met, and a power-on time sequence control circuit is eliminated.