31results about How to "Reduce conduction voltage drop" patented technology

The invention discloses a split gate IGBT (Insulated Gate Bipolar Translator) structure, and belongs to the field of semiconductor devices. Comprising collector metal, a P-type collector region, an N-type field stop layer and an N-type drift region which are sequentially arranged from bottom to top, an N-type storage layer, a P-type body region and emitter metal are sequentially arranged above the N-type drift region, an N + contact region is arranged in the P-type body region, a first oxide layer medium is arranged in the middle of the bottom of the emitter metal, a cross-shaped groove is formed in the N-type drift region, and a second oxide layer medium is arranged in the cross-shaped groove. The cross-shaped groove divides the N-type drift region, the N-type storage layer, the P-type body region and the N + contact region into a left part and a right part. The top of the cross-shaped groove is provided with a gate oxide layer, the bottom of the cross-shaped groove is provided with a second oxide layer medium, the top of the cross-shaped groove is provided with gate polycrystalline silicon which divides the gate oxide layer into a left part and a right part, and the left wide part and the right wide part of the cross-shaped groove are both internally provided with separation gate polycrystalline silicon. According to the split gate IGBT structure provided by the invention, the Miller capacitance and the conduction voltage drop can be effectively reduced.

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, at least two super junction structure layers arranged on one side of the substrate, wherein the super junction structure layer comprises P-type strip buried regions and N-type strip buried regions which are arranged alternately and have the same extending direction, and the extending directions of the P-type strip buried regions in adjacent super junction structure layers are different; and an N-type buried layer arranged between the adjacent super junction structure layers. The longitudinal super junction structure layer is added, so that the withstand voltage performance of the whole device is improved, and the super high voltage super junction IGBT is realized. The N-type buried layer is arranged, so that the outflow of holes is prevented. The accumulation of holes appears below the N-type buried layer. When the number of holes is greater than that of electrons, the area cannot maintain charge balance, more electron current is injected into the area by the emitter, the concentration of carriers locally increases, and the reduction of on-state voltage drop is realized.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device and a manufacturing method thereof, the IGBT device comprises an N-type semiconductor layer and a plurality of grooves located in the N-type semiconductor layer, gate electrodes are arranged in the grooves, and the gate electrodes are insulated and isolated from the N-type semiconductor layer through gate dielectric layers; the P-type body region is located between the adjacent grooves, and an N-type emitter region is arranged in the P-type body region; the N-type carrier storage layer is positioned below the P-type body region and is positioned between the adjacent grooves; the bottom of each groove is provided with a P-type protection layer, and the P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the groove. The IGBT device adopts the shallow trench, so that the on-state voltage drop can be reduced, and the process yield can be improved; the bottom of the groove is surrounded by the P-type protection layer, so that local charge balance can be formed, and voltage resistance is improved.

The invention discloses a high-voltage-withstanding Ga2O3 vertical power diode with a composite terminal and a preparation method thereof, and solves the problem that the reverse leakage current is too large due to the current edge collection effect and the electric field concentration effect in the existing gallium oxide power diode. The device comprises a cathode, a substrate, an epitaxial layer, an ion implantation region, a dielectric layer, a p-type NiO film layer covering the dielectric layer, and an anode metal layer covering the surface of the device from bottom to top. The preparation method comprises the following steps: cleaning an epitaxial wafer, manufacturing a cathode, photoetching to form a region to be injected with ions, injecting the ions, depositing a dielectric layer, depositing a p-type NiO thin film, and depositing an anode metal layer. According to the gallium oxide power diode, the dielectric layer edge terminal and the ion implantation edge terminal are introduced into the gallium oxide power diode, and the p-type NiO film is deposited on the dielectric layer, so that reverse electric leakage is remarkably reduced, the voltage resistance of the device is greatly improved, and the gallium oxide power diode has a wide application prospect in the fields of high power, military industry and the like.

The invention discloses a mining piezoelectric type vibration energy synchronous extraction circuit and method. The mining piezoelectric type vibration energy synchronous extraction circuit comprises a piezoelectric module, a synchronous switch module, an active rectification circuit module, a current zero-cross detection circuit module and an energy storage capacitor, two ends of the piezoelectric module are connected with positive and negative input ends of the active rectification circuit module; the energy storage capacitor is connected in parallel with a positive output end of the active rectification circuit module; the synchronous switch module is arranged between the piezoelectric module and the active rectification circuit module, and when the current zero-crossing detection circuit module detects a zero-crossing point of a current source in the piezoelectric module in real time, the synchronous switch module is controlled to be switched on; and when the absolute value of the input end voltage of the active rectification current module is greater than the conduction threshold value of the bridge arm switch tube corresponding to the active rectification current circuit module, the synchronous switch module is controlled to be cut off. According to the invention, the conversion efficiency of vibration piezoelectric energy is greatly improved, and the defect that a traditional diode rectification energy-taking circuit cannot be reliably used is overcome.

The invention discloses a silicon carbide diode structure, a chip structure and a preparation method thereof. Each of the diode structure and the chip structure comprises a cathode metal and an N + type silicon carbide substrate above the cathode metal, and a first N-type silicon carbide epitaxial layer, a second N-type silicon carbide epitaxial layer and a P + type shielding region are sequentially arranged above the N + type silicon carbide substrate; one end, far away from the N + type silicon carbide substrate, of the second N-type silicon carbide epitaxial layer is provided with a longitudinal step groove, the longitudinal step groove penetrates through the second N-type silicon carbide epitaxial layer and a part of the first N-type silicon carbide epitaxial layer, and the side wall and the bottom of the step groove are coated by anode metal. The chip structure further comprises a plurality of cellular structures which are provided with the layers and are different in structure. According to the invention, under the condition of not increasing the area of an active region chip, the Schottky contact area can be obviously increased, the conduction loss of the device is reduced, and the anti-surge capability of the device is improved.

The invention discloses a groove type IGBT device with low Miller capacitance, and belongs to the field of semiconductor devices. Comprising collector metal, a P-type collector region, an N-type field stop layer, an N-type drift region, an N-type storage layer, a P-type body region and emitter metal which are sequentially arranged from bottom to top, and an N + contact region is arranged in the P-type body region. A cross-shaped groove is arranged in the N-type drift region, and the cross-shaped groove divides the region from the N-type drift region to the N + contact region into a left part and a right part. The bottom of the cross-shaped groove is provided with a second oxide layer medium and first grid polycrystalline silicon which divides the second oxide layer medium into a left part and a right part, and the top of the cross-shaped groove is provided with a third oxide layer medium and second grid polycrystalline silicon which divides the third oxide layer medium into a left part and a right part. And the top end of the second grid polycrystalline silicon is flush with the bottom end of the emitter metal. According to the trench type IGBT device with the low Miller capacitance provided by the invention, the Miller capacitance and the conduction voltage drop can be effectively reduced.

The application discloses a GPP rectifier diode chip with a gradient-doped composite glass passivation layer, and belongs to the technical field of semiconductor devices. The GPP rectifier diode chip with the gradient-doped composite glass passivation layer comprises a base substrate, a gradient diffusion zone and a composite glass passivation layer. The application solves the problems of poor interface charge stability, large leakage current and insufficient long-term reliability of a conventional single-layer or multi-layer glass passivation layer of an existing GPP rectifier diode chip. The first gradient distribution of the resistivity of the base substrate along the thickness direction, the second gradient distribution of the impurity concentration of the gradient diffusion zone surface along the transverse direction and the composite glass passivation layer with periodic fluctuation of carbon content inhibit the concentration effect of the junction edge electric field, improve the interface matching property and compactness of the passivation layer and the semiconductor surface, thereby reducing the leakage current, and improving the voltage resistance and long-term working stability of the device.

This invention relates to the field of electrical technology, and more particularly to a flyback switching power supply absorption circuit, a transformer leakage inductance absorption method, and a chip. The circuit includes: a transformer comprising a primary winding NP and a secondary winding NS; a primary sub-circuit comprising an energy storage branch connected to the primary winding NP and an absorption branch connected to the primary winding NP, wherein when the energy storage branch is on, the primary winding NP stores energy, and when the absorption branch is on, it absorbs the leakage inductance energy of the transformer; and a secondary sub-circuit connected to the secondary winding NS, wherein when the secondary winding NS is on, it provides an output voltage VOUT to the load connected to the secondary winding NS. This invention can solve the problem of low power conversion efficiency. By absorbing leakage inductance energy through the absorption branch for use by the load connected to the secondary sub-circuit, the power conversion efficiency can be improved.

The utility model relates to the technical field of semiconductors, in particular to an insulated gate bipolar transistor, which comprises a transistor module, bare copper is arranged at the center of the transistor module, and a chip A and a chip B are respectively arranged below the bare copper and on the transistor module. A collector lead and a grid lead are sequentially arranged at the bottom of the transistor module, the chip A is connected with the collector lead through a first aluminum wire, and the chip A is connected with the grid lead through a second aluminum wire. The insulated gate bipolar transistor adopts a double-chip structure, and the IGBT with the double-chip structure has smaller switching loss under the condition of the same current and voltage, so that higher power bearing capacity is realized under the condition of the same size, the power density is improved, higher power output is favorably realized in a limited space, and the reliability of the IGBT is improved. Meanwhile, by means of the double-chip structure, when one part of chips are damaged, the other part of chips can still be used, and therefore the overall reliability is improved.

The invention discloses a reverse conducting RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Translator) device, which relates to the technical field of semiconductors, reduces a voltage turn-back phenomenon, improves the stability, the reliability, the voltage endurance capability and the switching speed of the device, and reduces the switching loss. By arranging the P + buffer layer and the field limiting ring structure, the thermal management performance and the voltage endurance capability of the device are improved, and the service life of the device is prolonged; and a composite buffer structure is formed, so that the conduction voltage drop and the switching loss of the device are reduced. According to the scheme, the IGBT device comprises a semiconductor substrate and an IGBT device main body formed on the semiconductor substrate, the IGBT device main body is composed of an emitter, a grid, a collector and a field limiting ring structure; the emitter region comprises a P + type emitter region and an N type base region; the emitter region further comprises an N + heavily doped region and an N-lightly doped region to form a composite buffer structure; the gate region comprises a gate oxide layer and a polycrystalline silicon filling layer; the collector region comprises an N + doped region and a P + buffer layer, and the N + doped region forms a PIN diode structure and is reversely connected with the IGBT device in parallel.

The invention provides a power device and a manufacturing method thereof, and the power device comprises a semiconductor layer which comprises a first doped region, a second doped region, a well region and a third doped region which are sequentially adjacent to each other in a direction from a second surface to a first surface; the isolation part extends into the second doped region from the first surface of the semiconductor layer and is adjacent to the well region and the third doped region; the semiconductor device further comprises a resistor structure and a diode structure, at least part of the resistor structure and / or the diode structure are / is located in the isolation part, the resistor structure is used for forming a first resistor, the diode structure is used for forming a first diode, one end of the first resistor is electrically connected with the third doped region, and the other end of the first resistor is electrically connected with the second doped region. The other end of the first resistor is electrically connected with the cathode of the first diode, and the anode of the first diode is electrically connected with the well region. The additional resistors and diodes are arranged in the power device, so that the potentials of different areas in the power device are adjusted, and the conduction voltage drop of the power device is further reduced.

The present invention discloses a high-conduction low-loss IGBT device structure and a preparation method thereof, wherein the IGBT device structure comprises an emitter metal layer, a dielectric layer, an N+ source region, a P-type base region, a drift region, a substrate and a collector layer arranged in sequence from top to bottom, and also comprises a trench gate penetrating the N+ source region and the P-type base region from top to bottom and extending into the drift region; wherein an insulating region is arranged between adjacent trench gates in the drift region, and a plurality of N-type doped regions are arranged in the substrate or the collector layer. The high-conduction low-loss IGBT device structure of the present invention and a preparation method thereof can reduce the on-state voltage drop Vcesat of the device, improve the on-state efficiency, reduce the tail current, and reduce the turn-off loss Eoff.

The invention discloses a semiconductor power device and an electronic device. The semiconductor power device comprises a substrate, a drift region, a base region, an active gate, two virtual gates and a carrier storage region, the base body is provided with a first surface and a second surface which are opposite; the drift region is arranged in the substrate and is positioned between the first surface and the second surface; the base region is arranged on one side of the drift region facing the first surface; an emitter region, a contact region and a preset injection region are arranged in the base region; the active gate and the virtual gate penetrate through the base region and extend to the drift region; the active gate is located between the two virtual gates; the carrier storage region is arranged on one side, facing the base region, in the drift region, and is positioned on two sides of the active gate and the virtual gate; the drift region comprises a first drift region which penetrates through the carrier storage region to be in contact with the base region, and the first drift region and the preset injection region are located on the same side, away from the active gate, of the virtual gate. The turn-off loss of the semiconductor power device is reduced while the conduction voltage drop of the semiconductor power device is reduced.

The invention discloses a driving circuit, a driving method and driving equipment of a switch assembly and a storage medium. The switch assembly comprises an MOS (Metal Oxide Semiconductor) and an IGBT (Insulated Gate Bipolar Translator), the driving circuit comprises a microcontroller which is respectively connected to a grid electrode of the MOS and a grid electrode of the IGBT, and the microcontroller is configured to control the MOS to be switched on and control the IGBT to be switched off when a working current is smaller than a first current threshold value, so that the working current passes through the MOS; when the working current is larger than or equal to the first current threshold value and smaller than the second current threshold value, the MOS is controlled to be firstly switched on and then switched off relative to the IGBT, so that the working current passes through the MOS and the IGBT which are connected in parallel; and when the working current is greater than or equal to the second current threshold value, controlling the IGBT to be switched on firstly and then switched off relative to the MOS, so that the working current passes through the MOS and the IGBT which are connected in parallel. According to the driving circuit of the switch assembly, different driving modes are implemented according to different current ranges of the working current, the switch device is protected, and the working efficiency of the switch device is improved.

The invention provides a bipolar SIC power device, and the device comprises a collector which is formed by alternately arranging a plurality of collector first doping type regions and a plurality of collector second doping type regions; the substrate is formed by alternately arranging a plurality of substrate second doping type regions and a plurality of substrate first doping type regions; wherein the substrate is located on the collector electrode; the epitaxial layer of the second doping type is formed on the substrate; wherein the second doping type region of the collector electrode is connected with the second doping type region of the substrate, the first doping type region of the collector electrode is connected with the second doping type region of the substrate, and the second doping type region of the collector electrode is connected with the first doping type region of the substrate. The technical problem that a traditional SiC IGBT device is large in conduction loss under the low-current condition is solved.

The invention provides a transverse MOS (Metal Oxide Semiconductor) device and a preparation method thereof. A buried oxide layer and a P-type drift region are grown on the upper surface of a P-type substrate in an upward variable doping epitaxial manner in sequence; the bottom of the gate is connected with the upper surface of the buried oxide layer; a dielectric layer is filled in the trench structure on the P-type drift region; the gate electrode is arranged on one side of the dielectric layer, a first P + region is arranged on the other side of the dielectric layer, the upper surface of the gate electrode and the upper surface of the first P + region are flush with the upper surface of the dielectric layer, and the drain electrode is arranged on the upper portion of the first P + region; an N-type well region is arranged between the dielectric layer and the gate electrode; the upper part of the N-type well region is provided with a second P + region and an N + region, the second P + region and the N + region are both located between the gate electrode and the dielectric layer, and the second P + region is located between the N + region and the gate electrode; the source electrode is arranged at the upper part of the N + region; the problem that the transverse electric field is low due to the fact that the surface of a traditional LDMOS high-voltage device depends on a silicon layer for voltage withstanding is solved, and the voltage withstanding capacity of the device in the transverse unit length is enhanced.

The invention discloses an SBD-integrated SiC MOSFET device and a preparation method thereof, and relates to the technical field of semiconductors. An SBD structure is arranged in the SiC MOSFET chip and connected with a body diode of the SBD structure in parallel, the embedded SBD diode increases the contact area of an N + region and metal in the vertical direction through a groove structure, meanwhile, the doping concentration of the N + region is far larger than that of an N-drift layer, the heavily-doped N + region can also reduce the conduction voltage drop of the embedded SBD diode, the follow current capacity of the SiC MOSFET device is greatly improved, and the performance of the SiC MOSFET device is improved. And the power loss is reduced. In the blocking state, the deeply injected PP region is beneficial to shielding the embedded SBD region and a high electric field at the bottom of the gate trench, and the reliability of the device can be improved.

The invention provides a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a first conductive type back surface layer, a trench gate and a deep trench field plate, wherein the first conductive type back surface layer is composed of a first conductive type buffer layer and a first conductive type follow current heavily doped region below the deep trench field plate; the trench gate penetrates through a second conductive type body region and extends into a first conductive type substrate layer; and the depth of the trench gate penetrating through the first conductive type heavily doped region is smaller than that of the deep trench field plate. The deep trench field plates in short circuit with the emitter electrode are arranged on the two sides of the trench gate, so that a large number of holes can be accumulated when the deep trench field plates are conducted, and the conduction voltage drop is reduced; meanwhile, the vertical electric field distribution is added into the deep trench field plate to optimize the compromise relation between the FRD breakdown voltage and the break-over voltage in the RC-IGBT, so that the working loss of the RC-IGBT in the follow current state is reduced; besides, carriers in a depletion layer can be rapidly extracted in a follow current state in cooperation with a deep trench field plate, so that the current released during reverse recovery is reduced, and the peak current of reverse recovery is reduced.

The utility model provides a kind of bidirectional gallium nitride T type three-level power module and circuit board, wherein, upper bridge arm switch device, midpoint bidirectional switch device and lower bridge arm switch device are all bidirectional gallium nitride power switch;The first drive reference pin of upper bridge arm switch device is connected direct current positive bus;The first drive reference pin of midpoint bidirectional switch device and the first drive reference pin of lower bridge arm switch device are connected to the second drive reference pin of upper bridge arm switch device;The first drive reference pin of midpoint bidirectional switch device and the first drive reference pin of lower bridge arm switch device are also connected to the second drive reference pin of upper bridge arm switch device;The second drive reference pin of midpoint bidirectional switch device is connected direct current neutral line;The second drive reference pin of lower bridge arm switch device is connected direct current negative bus, can reduce the quantity of power tube, reduce conduction loss.

The application discloses a kind of multistage trench multi-channel integrated schottky diode's MISFET, comprising: gallium oxide substrate, drain, gallium oxide epitaxial layer, source;Gallium oxide epitaxial layer upper portion is equipped with including M≥2 level sub-trench multistage trench, the opening distance of first level sub-trench to M level sub-trench successively reduces;High resistance zone is equipped in gallium oxide epitaxial layer between multistage trench and the bottom of multistage trench, and N type low resistance zone is equipped on high resistance zone except the bottom of M level sub-trench;Schottky diode is integrated in M level sub-trench;Sub-trench bottom and sidewall except M level are deposited with gate dielectric layer, gate electrode is deposited on the surface of gate dielectric layer, and gate electrode and source are covered with interlayer dielectric layer.The application reduces the electric field at the surface of device, reduces the dependence of device on gate dielectric material thickness, while reducing the forward conduction resistance and third quadrant conduction resistance of device, improves the voltage resistance and reliability of gallium oxide MISFET device.

The invention provides a bus fault protection circuit, and relates to the technical field of integrated circuits, the bus fault protection circuit comprises a power supply end, a bus pin end, a comparator, a first voltage sampling circuit, a second voltage sampling circuit and an output driving branch; the output driving branch comprises an output driving tube and a protection transistor; the first voltage sampling circuit, the second voltage sampling circuit and the comparator are configured as follows: when the voltage value of the bus pin end is smaller than or equal to the voltage value of the power supply end, the output end of the comparator outputs a first level signal to the control electrode of the protection transistor based on the comparison result of the first sampling voltage and the second sampling voltage; the protection transistor is driven to be conducted; when the voltage value of the bus pin end is larger than the voltage value of the power supply end, the output end of the comparator outputs a second level signal to the control electrode of the protection transistor based on the comparison result of the first sampling voltage and the second sampling voltage so as to drive the protection transistor to be turned off, and fault high-voltage protection can be effectively carried out on the transmitter bus.

A SiC-bidirectional GaN-based heterogeneous high-power-density T-type three-level converter system belongs to the technical field of power electronics, and comprises an input module, a T-type three-level topology main circuit, a control module, a heat dissipation management module and an output module, and the input module, the T-type three-level topology main circuit, the control module, the heat dissipation management module and the output module are connected in sequence. By combining the advantages of SiC and GaN heterogeneous power devices, the problems of non-uniform power device loss, large junction temperature deviation, insufficient system reliability and the like in the existing T-type three-level converter system are solved. According to the system, the power density and the conversion efficiency of the converter are improved, so that the system is kept stable under high-frequency operation, and the system is suitable for high-requirement application scenes such as electric traffic, energy storage systems and new energy power generation.

The present invention relates to a trench-type power device and a preparation method, in particular to a trench-type power device and a preparation method capable of improving breakdown characteristics. According to the technical solution provided by the present invention, a trench-type power device capable of improving breakdown characteristics, the trench-type power device comprises: a semiconductor substrate of a first conductivity type; an active region prepared in the central region of the semiconductor substrate, comprising a plurality of cells connected in parallel, wherein the cells in the active region adopt a trench structure, and the bottom of the trench of the cell trench is located below the second conductivity type base region across the active region; a first conductivity type carrier storage layer is arranged in the second conductivity type base region, and the first conductivity type carrier storage layer contacts the outer side wall of the corresponding cell trench. The present invention improves the breakdown characteristics of the power device, reduces the conduction loss of the power device, increases the switching speed, and effectively reduces the conduction voltage drop.

The application provides a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a back layer of a first conductive type which is composed of a buffer layer of the first conductive type and a freewheeling heavy doped region of the first conductive type under the deep trench field plate, a trench gate and a deep trench field plate which penetrate a body region of a second conductive type and extend into a substrate layer of the first conductive type; and the trench gate which also penetrates the heavy doped region of the first conductive type has a depth smaller than that of the deep trench field plate. The deep trench field plate which is short-circuited with the emitter and arranged on both sides of the trench gate can accumulate a large number of holes when the deep trench field plate is turned on, so that the on-state voltage drop is reduced. Meanwhile, the deep trench field plate optimizes the compromise relationship between the FRD breakdown voltage and the on-state voltage in the RC-IGBT with a vertical electric field distribution, so that the working loss of the RC-IGBT in the freewheeling state is reduced. In addition, the deep trench field plate can quickly extract the carriers in the depletion layer in the freewheeling state, so that the current released in the reverse recovery is reduced, and the peak current in the reverse recovery is reduced.

This utility model discloses a step-down charging module for a solar charger, comprising: a photovoltaic input terminal; a multi-stage input filter network disposed at the photovoltaic input terminal; a P-channel MOSFET switch connected to the photovoltaic input terminal; a first Schottky diode (D2); a controller (U4); a second Schottky diode (D1) connected between the output terminal of the first Schottky diode (D2) and ground; an energy storage inductor (LX3); a current sampling resistor (RCS) connected in series between the energy storage inductor (LX3) and the battery terminal; output filter capacitors (C32, C33) connected between the battery terminal and ground; and an RC absorption network connected between the output terminal of the first Schottky diode (D2) and ground. This utility model has the following advantages: this step-down charging module for a solar charger features high efficiency, high reliability, low noise, and high-precision charging control.

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a semiconductor substrate, an epitaxial layer is formed on the surface of the semiconductor substrate, and a contact doping region is formed in the epitaxial layer; the shielding doped regions are located in the epitaxial layer on the two sides of the contact doped region, and the doping type of the shielding doped regions is opposite to that of the contact doped region; the well region is located in the epitaxial layer at the bottom of the contact doped region, the doping type of the well region is opposite to that of the contact doped region, and the depth of the shielding doped region is larger than that of the well region and larger than that of the contact doped region; the trench gate structures are located on the two sides of the shielding doped region and penetrate through part of the shielding doped region to be connected with the well region and the contact doped region, and the depth of the trench gate structures is larger than that of the well region and smaller than that of the shielding doped region. The MOSFET unit structure can solve the problems that an existing MOSFET unit structure is not high in reliability and low in integration level.

The invention provides a SiC groove type JFET (junction field effect transistor) integrated with an SBD (Schottky barrier diode). The drain metal, the N + substrate region, the N-drift region, the JFET channel region and the N + source region are sequentially arranged from bottom to top; the JFET channel region is located on the upper surface of the N-drift region; the P + region is located on the upper surface of the N-drift region; the N + source region is located on the upper surfaces of the N channel region, the left P + region and the right P + region; the gate metal layer is located on the upper surface of the left P + region; the source electrode metal layer is divided into two parts, the top source electrode metal layer is located on the upper surface of the N + source region, and the right side source electrode metal layer is located on the outer surface of the right side P + region and the upper surface of the SBD through-flow region. The phase electrode coupling area is reduced, the gate-drain capacitance and the gate-drain charge are reduced, the switching speed is higher, and the switching loss is lower; when the device works in a third quadrant, the Schottky barrier diode is introduced, the turn-on voltage is greatly reduced, the conduction loss is greatly reduced, SBD conduction is unipolar conduction, the bipolar degeneration effect is avoided, and the reverse recovery characteristic is excellent.

The invention discloses a semiconductor power device and an electronic device. The semiconductor power device comprises a substrate, a drift region of a first conduction type, a base region of a second conduction type, an active gate and a first carrier storage region of the first conduction type, wherein the base body is provided with a first surface and a second surface which are opposite; the drift region is arranged in the substrate and is positioned between the first surface and the second surface; the base region is arranged on one side of the drift region facing the first surface; an emitter region of a first conductive type and a contact region of a second conductive type are arranged in the base region; the emitter region and the contact region are positioned on two sides of the active gate; the active gate penetrates through the base region and extends to the drift region; the first conduction type first carrier storage regions are arranged on one side, facing the base region, in the drift region and are positioned on two sides of the active gate; part of the drift region penetrates through the first carrier storage region to be in contact with the base region. The turn-off loss of the semiconductor power device is reduced while the conduction voltage drop of the semiconductor power device is reduced.

The invention discloses an insulated gate bipolar transistor and a preparation method thereof, and relates to the technical field of semiconductors, the insulated gate bipolar transistor comprises a substrate and a drift layer arranged on the substrate, the drift layer comprises an N-type drift region and a P-type drift region which are arranged in an attached mode, the upper surface of the N-type drift region is flush with the upper surface of the P-type drift region, and the upper surface of the P-type drift region is flush with the upper surface of the N-type drift region. A gate structure and a first blocking region are formed on the upper surface of the N-type drift region, a second blocking region is arranged on the P-type drift region, the first blocking region and the second blocking region are arranged in an attached mode, the doping concentration of the first blocking region is larger than that of the second blocking region, and a P-type base region is arranged on the first blocking region and the second blocking region. And an N-type heavily doped region and a P-type heavily doped region are arranged on the P-type base region. According to the insulated gate bipolar transistor and the preparation method thereof provided by the invention, the turn-off loss can be improved on the basis of reducing the turn-on loss.