44results about How to "Improve the conduction voltage drop" patented technology

The invention belongs to the field of power semiconductors, and particularly provides a SiC power device. The SiC power device comprises a SiC MOSFET and a SiC IGBT. For the SiC MOSFET device integrated with a PN junction body diode, the reverse recovery charge and related loss of the body diode can be greatly reduced, the reverse recovery peak current is reduced, and the EMI noise is reduced; forthe SiC MOSFET device integrated with an N-type Schottky diode or an integrated heterojunction diode, the voltage drop during reverse conduction of the MOSFET can be reduced, and the minority carrierinjection effect is eliminated, so that the conduction loss and reverse recovery loss of the diode are reduced; for the reverse conduction type SiC IGBT device integrated with the PN junction body diode, the reverse recovery charge and related loss of the body diode can be greatly reduced, the reverse recovery peak current is reduced, and the EMI noise is reduced; and moreover, for the reverse conduction type SiC IGBT device integrated with the N-type Schottky diode or the heterojunction diode, the voltage drop during reverse conduction of the reverse conduction IGBT can be reduced, the minority carrier injection effect is eliminated, and the conduction loss and reverse recovery loss of the diode are reduced.

The invention discloses a CSTBT device and a manufacturing method thereof, which belong to the field of semiconductor power devices. A groove gate structure is together formed through introducing a groove split electrode below a gate electrode, a P-type layer is introduced below the groove split electrode, a series diode structure is arranged above the groove split electrode, and the problem of acontradictory relationship existing between the forward conduction performance of the device and the voltage-withstanding performance caused through improving the doping concentration of an N-type charge storage layer in the traditional CSTBT device is solved. The saturation current density is reduced and the short circuit safety working area of the device is improved. The gate capacitance of thedevice is reduced, the switching speed is improved, the switching loss is reduced, and the switching performance of the device is improved. The electric field concentration effects at the bottom of the groove are improved to further improve the breakdown voltage of the device. The carrier enhancement effects at the emitter end of the device are improved, the carrier concentration distribution in the whole N-drift region is improved, and the compromise characteristics between forward conduction voltage drop and turning-off losses are further optimized. Besides, the device manufacturing method is compatible with the manufacturing process of the existing CSTBT device.

The invention discloses a planar gate IGBT (Insulated Gate Bipolar Transistor) chip, which comprises a collector metal electrode, a P+ collector region, an N- drift region, a P- base region, a P+ ohmic contact region, an N+ source region, a gate oxide layer, a polysilicon gate and a gate metal electrode which are arranged successively, and an emitter metal electrode arranged above the P+ ohmic contact region, wherein the polysilicon gate of the planar gate IGBT chip adopts a planar gate structure. The planar gate IGBT chip also comprises a first N-type carrier buried layer and/or a second N-type carrier buried layer. The first N-type carrier buried layer is located below the P- base region. The second N-type carrier buried layer is located below the gate oxide layer and at both sides of the P- base region. The planar gate IGBT chip has the beneficial effects that the compromise relation between conduction pressure drop and turn-off loss of the IGBT is reduced, lower power consumption is realized, and thus the power density, the operating junction temperature and the long-term reliability of the IGBT chip are increased.

Provided is an IGBT and a manufacture method thereof. The IGBT is formed on a semiconductor substrate, and comprises an MOS structure placed at the surface of the semiconductor substrate and a PN junction placed at the bottom of the semiconductor substrate. Multiple grooved structures are placed at the bottom of the semiconductor substrate, penetrate P and N zones of the PN junction, and divide the PN junction into multiple areas. Each grooved structure comprises a metal block at the bottom of the semiconductor substrate and an oxidation layer between the metal block and the semiconductor substrate, and the work function of metal of the metal block is lower than that of a material of the semiconductor substrate. The grooved structures enable that the direction and distribution of electronic current and hole current in the PN junction of the semiconductor substrate are changed, distribution of carriers in the semiconductor substrate can be adjusted by adjusting the grooved structures, and thus, the relation between the connecting voltage drop and turnoff time of the IGBT can be optimized.

The invention discloses a bidirectional IGBT and a manufacturing method therefor, and belongs to the technical field of power semiconductor devices. According to the invention, a split electrode whichis equipotential with a surface metal and a thick dielectric layer located at a peripheral side of the split electrode are introduced to a conventional trench gate structure, and a floating P-type body region is introduced to one side of a split trench gate structure, thereby achieving the symmetric forwarding and reverse on/off characteristics of an IGBT structure under the condition that a threshold voltage and connection of an IGBT device are not affected. The adverse effect caused by the Miller effect is improved, and the drive power consumption is reduced. The current and voltage oscillation and EMI problems are avoided in a start dynamic process of the device. The short-circuit safety working area of the device is improved. The gate capacitance is reduced, the switching speed of thedevice is improved, and the switching loss of the device is reduced. The concentration of an electric field at the bottom of a trench is improved, and the breakdown voltage of the device is improved.The carrier enhancement effect of an emitter electrode is improved, the carrier concentration distribution of the whole N-type drift region is improved, and the compromise between the forwarding conduction voltage drop and switching-off loss is improved.

The invention discloses an insulated gate bipolar transistor, an IPM module, an air conditioner and a manufacturing method of the insulated gate bipolar transistor. The insulated gate bipolar transistor comprises a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface which are arranged relatively; and the insulated gate bipolar transistor also comprises a drift region and an active region formed on the first surface of the semiconductor substrate, and a collector region formed on the second surface of the semiconductor substrate; wherein the collector region comprises a first collector layer, a second collector layer, a third collector layer and a collector metal layer, which are sequentially connected to the drift region along the thicknessdirection of the semiconductor substrate; and the dosage concentration of the third collector layer is greater than the dosage concentration of the second collector layer, and is less than the dosageconcentration of the first collector layer. According to the invention, the conduction voltage drop and the off time of the insulated gate bipolar transistor are reduced at the same time under the circumstances that the dosage concentration is not increased and the lower conduction voltage drop of the insulated gate bipolar transistor is ensured through setting the dosage concentrations of the collector region uneven.

The invention belongs to the technical field of power semiconductor, and specifically relates to a thin SOI short circuit anode LIGBT (Lateral Insulated Gate Bipolar Transistor). Compared with a traditional SOI base LIGBT, the thin SOI short circuit anode LIGBT is characterized in that an N+ anode region which is in parallel with a P+ anode region in the vertical direction, and introducing disjunctively distributed N type islands at one side, approaching a cathode structure, in the P+ anode region (9) and the N+ anode region (10); when a new device in the blockout state, the N type islands are not completely depleted, thus effectively preventing further expansion of a depletion region and preventing break-through and breakdown of the N type islands; when the initial stage is started, an electro current flows by the N type islands and the high resistance drift regions among the adjacent N type islands; and compared with traditional continuous N buffer layers, the disjunctively distributed N type islands can increase the distribution resistance at one side of the anode side to enable the device to enter the bipolar mode under a smaller current. Compared with a traditional LIGBT, the thin SOI short circuit anode LIGBT has the advantages of high speed and low on-off loss. Compared with a traditional short circuit anode LIGBT, the thin SOI short circuit anode LIGBT can eliminate the snapback effect even under a small cell size.

The invention provides a manufacturing method of a semiconductor device. The method comprises the following steps: performing ion irradiation treatment on a back of a silicon substrate to promote an activation rate of anodic impurities of the semiconductor device, improve the breakover voltage drop of the semiconductor device and lower the breakover loss; and forming an extra compound center in the silicon substrate after annealing the silicon substrate through the ion irradiation treatment, thereby reducing the minority carrier lifetime of the semiconductor device and achieving an aim of lowering the switch loss of the semiconductor device. Furthermore, a metal layer is directly deposited on the back of the silicon substrate after injecting the impurity ions into the back of the silicon substrate; and then the annealing process is performed on the silicon substrate, namely, the impurity activation of the semiconductor device and the metal alloy process are integrated, the aims of impurity activation and metal alloying are realized at the same time through the annealing process after the deposition of the metal layer without additionally performing the annealing process after the impurity ion injection; the process step is reduced, and the treatment cost is saved.

The invention relates to a trench type insulated gate bipolar transistor and a preparation method thereof, belonging to the technical field of power semiconductors. A first conductive trench MOSFET isintroduced in a second conductive floating zone of a trench type insulated gate bipolar transistor, a gate electrode of the MOSFET is in short circuit with current conversion metal, so that when thedevice is conducted forwardly, the MOSFET turns off due to low electric potential of the floating zone, electronic current converted by the conversion metal cannot flow out of a leakage electrode through MOSFET, so as not to increase voltage drop of forward conducting; when the device is turned off, MOSFET surface trench electron inverses so as to form an electron flow path due to very high electric potential of the floating zone, so that electron current converted from hole current by the conversion metal can flow out of the leakage electrode through MOSFET, surplus carriers are extracted atfaster speed, off time is shortened and off loss is reduced, and forward conducting and off loss are further balanced. The invention further relates to a preparation method for the trench type insulated gate bipolar transistor.

The invention provides a formation method of an IGBT (Insulated Gate Bipolar Transistor) device, and a structure of an IGBT device. The IGBT device is provided with a plurality of functional cells andredundant cells located between the plurality of functional cells. The formation method of the IGBT device includes the steps: performing an ion implantation process on a semiconductor substrate, ofa first region, for formation of the redundant cells; and performing an oxidation process to form a dielectric layer on the semiconductor substrate of the first region. Therefore, after executing theion implantation process, the oxidation rate of the semiconductor substrate of the first region can be effectively improved, and then the dielectric layer having a higher and more uniform thickness can be formed, and then the capacitance Cgc between a gate and a collector in the IGBT device can be effectively improved. Moreover, the dielectric layer formed by the combination of the ion implantation process and the first oxidation process also has a smaller size, thus reducing the area occupied by the redundant cells, and greatly improving the conduction voltage drop of the IGBT device.

The embodiment of the invention discloses an insulated gate bipolar transistor and a manufacturing method thereof. The insulated gate bipolar transistor comprises a drift region and a body region, wherein the drift region comprises a first doped region and a second doped region, the first doped region and the second doped region are the same in doping type, and the doping concentration of the first doped region is greater than that of the second doped region; the body region different from the drift region in doping type comprises a first part and a second part; the first part is located between the first doped region and an emitter region and is in contact with the first doped region; and the second part is located between the second doped region and the gate region and is in contact withthe second doped region.

The embodiment of the invention discloses an insulated gate bipolar transistor and a manufacturing method thereof. The insulated gate bipolar transistor comprises an emitter region, a body region, a drift region and a collector region which are located in the same predetermined plane, wherein the body region is positioned between the emitter region and the drift region and is in contact with the emitter region and the drift region; the drift region is located between the body region and the collector region and is in contact with the collector region; at least one suppression unit is located in the drift region, comprises a concave surface with an opening facing the emitter region, and is used for suppressing at least part of carriers injected into the drift region to move towards the collector region; wherein the carriers are injected into the drift region from the emitter region, and the suppressed carriers are gathered on the surface of the suppression unit.

The invention discloses a process optimization method of a carrier storage trench gate bipolar transistor structure. By adjusting the injection sequence and the injection energy of the carrier storage layer, the injection efficiency of the carrier storage layer is remarkably improved, the concentration of the carrier storage layer is increased, and the conduction voltage drop and the saturation current of the carrier storage trench gate bipolar transistor are reduced.