10results about How to "Reduce electric field" patented technology

The invention discloses an asymmetric super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the super-junction MOSFET structure comprises a substrate and a cellular structure, the cellular structure comprises: a first column region including an N-type drift region; a second pillar region disposed in the first pillar region and including a pillar region structure and a gate structure disposed on the pillar region structure; the third column region comprises a side wall P column region, the side wall P column region is an ion injection type P column region, and the charge of the side wall P column region is balanced with that of the adjacent N-type drift region; the third column area is arranged between the second column area and the first column area, and the third column area is arranged on one side of the second column area. According to the invention, the charge balance control of the side wall P column region and the corresponding N-type drift region is more accurate through the deep trench ion implantation of the side wall P column region; meanwhile, as the PN junction of the super junction is far away from the etching interface, the electric field at the defect interface is reduced, the reliability of the product is improved, multiple epitaxy is avoided, and the manufacturing cost of the super junction MOSFET is saved.

The invention relates to a trench gate super-junction MOS structure and a preparation method thereof. The trench gate super-junction MOS structure comprises a first conductive type substrate; the first conductive type epitaxial layer is arranged on the front surface of the first conductive type substrate; the second conductive type body region is arranged on the front surface of the first conductive type epitaxial layer and is positioned in the first conductive type epitaxial layer; the number of the second conductive type columns is at least two, and the second conductive type columns extend from the front face of the first conductive type epitaxial layer to the first conductive type epitaxial layer. The trench gate structure is arranged between two adjacent second conductive type columns and extends from the front surface to the back surface of the second conductive type epitaxial layer; the second conductive type doped column is arranged corresponding to the trench gate structure and is arranged on the back surface of the trench gate structure; and the first conductive type source region is arranged on the front surface of the second conductive type body region and is positioned in the second conductive type body region. The semiconductor device has the effects of further reducing the on resistance, reducing the electric field in the gate oxide layer and protecting the gate oxide layer.

The invention discloses a blackening treatment process for the electrical conductivity of a lithium tantalate wafer, belonging to the technical field of crystal materials. The blackening treatment process for the electrical conductivity of a lithium tantalate wafer comprises the following steps: spreading a composite reducing agent on the bottom of a crucible to form a bottom reducing agent layer, placing a lithium tantalate wafer on the bottom reducing agent layer, and then spreading the composite reducing agent on the lithium tantalate wafer to form a top reducing agent layer; introducing nitrogen for heat treatment, taking it out, and obtaining a blackened lithium tantalate wafer; the composite reducing agent comprises spherical copper powder, modified graphene and flaky copper powder in a mass ratio of 1: (0.1-0.2): (0.5-2). A blackening treatment process for the electrical conductivity of a lithium tantalate wafer, the blackening treatment process of the invention can significantly reduce the resistivity of the lithium tantalate wafer, improve the electrical conductivity of the lithium tantalate wafer, and has broad application prospects.

This invention discloses a silicon carbide-based trench MOSFET with an integrated superjunction structure and its fabrication method. The structure includes an n++ type silicon carbide substrate, an n-type drift layer, a p-type channel layer, a p-type shielding layer, a p++ type source region layer, and an n++ type source region layer. The n-type drift layer is disposed on the first surface of the n++ type silicon carbide substrate. A superjunction structure is integrated below the p-type channel layer and the p-type shielding layer. The superjunction structure includes a first n+ pillar region, a p+ pillar region, and a second n+ pillar region. The first n+ pillar region is located in the middle, and p+ pillar regions are provided on both sides of the first n+ pillar region. A second n+ pillar region is provided on the outer side of each of the two p+ pillar regions. A p-type channel layer is provided on the n-type drift layer on both sides of the superjunction structure and the first trench. Adjacent p++ type source region layers and n++ type source region layers are provided on the p-type channel layer. A gate electrode is provided above the p-type shielding layer. A gate oxide layer is provided between the gate electrode, the p-type shielding layer, and the sidewall of the second trench, which reduces the on-resistance and the electric field in the gate oxide layer at the bottom corner of the trench.

The embodiment of the invention provides a low-threshold-voltage Trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof. According to the method, a gate oxide layer (105), gate polycrystalline silicon (106), a P + / N-structure and a plurality of grooves (104) are included; the plurality of grooves (104) are arranged in parallel on the cross section of the low threshold voltage Trench MOSFET device; the gate oxide layer (105) is located on the inner wall of the groove (104); the gate polycrystalline silicon (106) is filled in the groove (104) on the gate oxide layer (105); the P + / N-structures are located on the lower sections outside the grooves (104) and extend to the positions below the grooves (104), and the P + / N-structures are connected to the outer walls of the two adjacent grooves (104). The P + / N-structure is located at the lower section outside the trench (104) and extends below the trench (104), and a breakdown point during breakdown is located at the P + / N-structure, so that the service life of the device is prolonged, and the reliability of the gate oxide (105) is improved.

The application discloses a process chamber, an upper electrode device thereof and a semiconductor process equipment. The upper electrode device comprises a radio frequency coil (11) and an adjustable capacitor (12). The radio frequency coil (11) is used for being wound outside a shielding cylinder (70) of the process chamber, and the shielding cylinder (70) is used for being sleeved outside a plasma generating cavity (20) of the process chamber. The adjustable capacitor (12) is connected in series with the radio frequency coil (11), and the adjustable capacitor (12) is used for being adjusted to different capacitance values in an ignition stage and a reaction stage of the process chamber. The above scheme can solve the problems of ignition difficulty and plasma bombardment on a dielectric window, and can also relieve the problem of abnormal discharge caused by the adoption of a lifting structure of the radio frequency coil.

This invention discloses a semiconductor device and its fabrication method. The semiconductor device includes: a substrate; a multilayer epitaxial layer located on one side of the substrate; the multilayer epitaxial layer including a barrier layer on the side away from the substrate; an isolation layer, a source, a gate, and a drain located on the side of the barrier layer away from the substrate, with the gate located between the source and the drain; the gate including a gate bottom surface near the substrate, the gate bottom surface including a first bottom surface portion and a second bottom surface portion; wherein, the isolation layer is located between the second bottom surface portion and the drain, the isolation layer is in contact with the gate, and the isolation layer is in contact with the multilayer epitaxial layer. The semiconductor device provided by this invention can improve the high electric field distribution on the side of the gate near the drain, and improve the reliability of the device under high temperature and high pressure.

The invention discloses a power device and a manufacturing method of the power device. The power device comprises a semiconductor substrate and a plurality of gate structures, wherein a well region and a drift region are formed in the semiconductor substrate; the gate structures are formed on the semiconductor substrate, each gate structure is in bridge connection with the well region and the drift region, each gate structure comprises a first gate and a second gate, the work functions of the first gate and the second gate are different, the first gate is located on the well region, the second gate is located on the drift region, and the first gate is in contact with the second gate; the gate structure composed of the first gate and the second gate which are different in work function is arranged on the semiconductor substrate, so that the gate structure is in bridge connection with the well region and the drift region, the overall work function difference between the gate structure and the semiconductor substrate is reduced, the voltage endurance capability of the power device is effectively improved, and the hot carrier injection life of the power device is effectively prolonged.

The application relates to a terminal structure and a preparation method of a power device. In a terminal region, a depletion stop ring is arranged in the direction of a second conductive type VLD region of a main junction, wherein the depletion stop ring is distributed in the terminal region at least in the second conductive type VLD region; for any depletion stop ring, a plurality of interval distributed depletion stop grooves are arranged, and the groove bottom of the depletion stop groove is below the second conductive type VLD region; for any depletion stop groove, in-groove conductive polysilicon filled in the depletion stop groove and in-groove low dielectric insulator covering the inner wall of the depletion stop groove are arranged, and the in-groove conductive polysilicon is insulated and separated from the inner wall of the depletion stop groove through the in-groove low dielectric insulator. The application can effectively avoid the surface breakdown of the VLD region, eliminate the influence of the periphery of the main junction and the deviation of the injection dose of a production line machine on the breakdown voltage, and improve the reliability of the terminal.

The present disclosure relates to the technical field of semiconductor technology, and relates to a semiconductor structure, a forming method thereof and a memory. The semiconductor structure comprises a substrate, a word line structure, a conductive contact structure and a buffer layer, wherein: the substrate comprises an active region, the active region comprises a channel region and a source region and a drain region distributed on both sides of the channel region respectively, and the channel region has a word line trench; the word line structure is located in the word line trench; the conductive contact structure is connected with the top of the drain region; and the buffer layer is located between the conductive contact structure and the word line structure. The semiconductor structure can reduce leakage, improve device reliability and reduce standby power consumption.