CMOS (Complementary Metal-Oxide-Semiconductor) transistor and stress memory treatment method thereof

Abstract

The invention discloses a CMOS (Complementary Metal-Oxide-Semiconductor) transistor and a stress memory treatment method thereof. The method comprises the following steps of: providing a substrate with a formed CMOS transistor, wherein the lower surface of the substrate is provided with a silicon oxide layer corresponding to the inner layer of the side wall of a grid of the CMOS transistor and a silicon nitride layer corresponding to the outer layer of the side wall of the grid; sequentially depositing a buffer oxide layer and a stress silicon nitride layer on the upper surface of the CMOS transistor; removing the stress silicon nitride layer on the upper surface of a PMOS (P-channel Metal Oxide Semiconductor) transistor and annealing the substrate if the CMOS transistor comprises a NMOS (N-channel Metal Oxide Semiconductor) transistor and the PMOS transistor; directly annealing the substrate if the CMOS transistor comprises the NMOS transistor; and removing the stress silicon nitride layer on the upper surface of the NMOS transistor and the buffer oxide layer and keeping the silicon oxide layer and the silicon nitride layer, corresponding to the side wall of the grid, on the lower surface of the substrate. The stress memory treatment method in the invention is favorable for decreasing the occurrence probability of PID (Proportion Integration Differentiation) and saving cost, and is simple.

Description

technical field [0001] The invention relates to the technical field of semiconductor device manufacturing, in particular to a stress memory processing method for a CMOS transistor and the CMOS transistor. Background technique [0002] Plasma processing has been widely used in the field of semiconductor device manufacturing. However, during the manufacturing process, the plasma will accumulate on the gate 1' of the device (see figure 1 ), when the accumulated plasma charge reaches a certain threshold amount, the electric field on the gate oxide layer 3' between the gate 1' and the substrate 2' will break down the gate oxide layer 3' and damage the device, this The phenomenon is called PID (Plasma Induced Damage, plasma induced damage). [0003] PID is more serious in the 65G (Generic) process than in the 65LL (Low Leakage) process, mainly because the 65G process requires more plasma treatment processes, such as the SMT (Stress Memorization Technology, stress memory technol...

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Problems solved by technology

However, CMOS transistors processed by SMT are more likely and more likely to be affected by PID, resulting in affected product stability and yield

[0006] In the United States Invention Patent Application Publication No. US20090224326A1 published on September 10, 2009, a method of using a protection circuit to reduce PID is disclosed, but obviously, adding a protection circuit will increase the area of ​​the entire integrated circuit, which is not suitable for Development Trend of IC Miniaturization

There are also some other attempts to reduce the PID phenomenon after the SMT process in the prior art, such as reducing the deposition temperature of the stress silicon nitride layer in the SMT, and converting the process of depositing the buffer oxide layer from LDSRO (Low Deposition Rate Silicon Rich Oxide, low Speed ​​deposition of silicon-rich oxide) to SACVD (Sub-Atmospheric Chemical Vapor Deposition, sub-atmospheric chemical vapor deposition), or change the etching bias of the stressed silicon nitride layer, etc., but a large number of experimental results show that the effects of the above methods are not Not ideal, the probability of PID in CMOS transistors after SMT is still high

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