Method for manufacturing PMOS transistor

Abstract

The invention provides a method for manufacturing a PMOS transistor. First of all, a second groove is formed through etching in a stress filling layer which is about to be predoped to prepare a source region and a drain region, the side wall of the second groove below a gate area being adjacent to a reserved part of a lightly doped source leakage extension area before the stress filling layer is formed, and afterwards, the second groove is filled so as to form an adjustment layer whose doping concentration is higher than that of the stress filling layer so that at the time when a source-drain area is prevented from generating break-through currents, the Ge and B doping concentrations on the surfaces of the source region and the drain region are improved; on one hand, the lost B doping impurities in the reserved part of the lightly doped source leakage extension area are supplemented, the B doping concentration of the lightly doped source leakage extension area is increased, the resistance of a channel region, the source region and the drain region is reduced, the electric field of the channel region is reduced, and the working currents are improved; and on the other hand, the stress applied to the channel region by the source region and the drain region is enhanced, the carrier mobility of the device channel region is improved, and the working currents of the PMOS transistor are increased.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices and relates to a method for manufacturing a PMOS transistor. Background technique [0002] With the increasing scale of integrated circuits and the rapid development of IC technology, the feature size of devices in integrated circuits is getting smaller and smaller. Metal-oxide-semiconductor (MOS) transistors are a major driving force in the evolution of semiconductor devices to high density and small size. When the manufacturing process of MOS transistors progresses to the micron level, the channel length and width of MOS transistors continue to shrink. When the length of the channel region is reduced to a certain value, the source / drain depletion regions are too close , will lead to an undesired punch through (punch through) current, resulting in a short channel effect (Short Channel Effect), but also a hot carrier effect (Hot Carrier Effect), which will cause the transistor to fa...

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Problems solved by technology

[0008] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for manufacturing a PMOS transistor, which is used to solve the problem in the prior art caused by the loss of B-doped impurities in the lightly doped source and drain extension regions. The problem with the increase in the resistance of the source and drain regions

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