18 results about "Hot carrier effect" patented technology

The application relates to the fields of microelectronic packaging and novel display technology, and discloses a packaging method suitable for a hybrid device packaging structure of a MicroLED, which comprises the following steps: preparing a wide-bandgap semiconductor driving chip, a logic control chip and a light-emitting pixel chip; transferring and fixing the wide-bandgap semiconductor driving chip, the logic control chip and the light-emitting pixel chip on the surface of a carrier plate in a coplanar mode; depositing a dielectric layer on the surface of the carrier plate to expose electrode contacts; manufacturing metal wires to build an internal electrical interconnection structure and lead out a peripheral interface; coating a packaging material on the surface of the carrier plate to insulate and coat the internal electrical interconnection structure; curing and cutting to separate an independent pixel packaging body; and assembling the pixel packaging body to a display panel substrate and connecting the peripheral interface to a global power supply network. The application suppresses the hot carrier effect under high-temperature working conditions, solves the problem of thermal failure, reduces the parasitic capacitance of high-frequency driving interconnection, removes potential failure products before macroscopic mounting, and improves the assembly yield of a display panel array.

Embodiments of the present application provide a semiconductor device, comprising: a substrate; a first well and a second well disposed in the substrate and adjacent to each other; an isolation structure disposed on the first well; a first field plate disposed on the isolation structure; a gate structure across the first well and the second well, and an opening between the first field plate and the gate structure, the opening exposing an edge of the isolation structure close to the gate structure; a drain structure disposed in the first well; and a source structure disposed in the second well, reducing or preventing hot carrier effect.

The application provides a manufacturing method of a semiconductor device, before an active region manufacturing process, a substrate region to be manufactured into a high-voltage transistor is subjected to groove etching to form at least a gate oxide groove and a first depth adjusting groove and define an active region horn, the depth of the first depth adjusting groove is used to increase the bottom depth of a shallow trench isolation structure for isolating a source / drain region and a channel region of the high-voltage transistor, the breakdown voltage of the high-voltage transistor is increased, and by ion implantation and oxidation on the active region horn, a relatively thick first gate oxide layer is formed, the problem of the thin gate oxide layer of the high-voltage transistor at the top corner of the active region is solved, the leakage at the top corner of the active region is reduced, the hot carrier effect and the gate-induced drain leakage are reduced, and the first gate oxide layer can also be used as a barrier layer to block the lateral diffusion of oxygen in the process of forming a second gate oxide layer, thereby improving the beak effect on the source / drain region of the high-voltage transistor.

This invention provides a method for manufacturing a semiconductor device. Before the active region manufacturing process, trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least spaced-apart gate oxide trenches and a first depth adjustment trench. This increases the bottom depth of the shallow trench isolation structure used to isolate the source / drain region and the channel region of the high-voltage transistor by utilizing the depth of the first depth adjustment trench, thereby increasing the charge path of the high-voltage transistor, increasing its breakdown voltage, and improving the performance of the high-voltage transistor. Furthermore, the active region convex angle between the gate oxide trench and the shallow trench outside it thickens the edge of the thick gate oxide layer, which helps to reduce leakage current at the apex of the active region of the thick gate oxide layer, solving the problem of the thick gate oxide layer being thin at the apex of the active region. This reduces the hot carrier effect and gate-induced drain leakage current, further improving the voltage withstand capability of the high-voltage transistor in the semiconductor device of this invention.

The invention discloses a semiconductor device and a semiconductor device manufacturing method. The semiconductor device comprises a semiconductor substrate, a drain electrode, a source electrode and a grid electrode, the grid electrode comprises at least one layer of polycrystalline silicon; a source region corresponding to the source electrode and a drain region corresponding to the drain electrode are arranged in the semiconductor substrate, and a channel region is arranged between the source region and the drain region; the grid electrode is arranged on the channel region; gate oxide layers are arranged at the connection position of the grid electrode and the channel region and the connection position of the grid electrode and the source electrode; the surface of the gate and the surface of the source are at the same height, and the surface of the gate is higher than the surface of the drain and forms a step structure. By means of the technical scheme, the hot carrier effect and the short channel effect can be improved, and the electrical performance of the semiconductor device is improved.

The invention provides an easy-to-drive input / output device structure and a manufacturing method thereof. The structure comprises a substrate, a grid electrode, a source-drain heavily doped region and a lightly doped region. The device is asymmetrically arranged, and the lightly doped region is only arranged on one side of the drain electrode. The manufacturing method comprises the following steps: forming isolation and a well region on a substrate; only forming a lightly doped region in the drain region by adopting a non-self-alignment process; forming a grid electrode covering a part of the lightly doped region; and forming a source-drain heavily doped region by taking the grid as a mask. According to the invention, through asymmetric LDD design and grid electrode overlapping, punch-through risk is reduced under a small source-drain spacing, a hot carrier effect is inhibited, specific on-resistance and driving current are optimized, device reliability is improved, and preparation of a 4V working voltage device can be realized based on a 5V process platform.

The application relates to the technical field of semiconductors, in particular to a semiconductor structure for improving HCI effect and a manufacturing method thereof. The method comprises the following steps: providing a substrate, including a semiconductor substrate, a substrate oxide layer and a hard mask layer which are sequentially stacked; a shallow trench corresponding to the position of a gate electrode is formed in the semiconductor substrate; the end part of the substrate oxide layer close to the shallow trench is etched and removed; after etching, the side surface of the substrate oxide layer close to the shallow trench is inwardly retracted to form a pit, the pit opening intersects with the surface of the hard mask layer; the shallow trench is filled to obtain an isolation layer; the substrate oxide layer and the isolation layer are combined to form a hole at the pit position; the hard mask layer is removed, a notch is formed at the position where the hole intersects with the hard mask layer, and the hole is communicated with the external environment through the notch; a gate material layer is deposited on the surface of the substrate oxide layer, the gate material enters the hole along the notch during deposition, and a control gate body is formed by filling. The preparation process is simple, the hot carrier effect of the device can be improved, and the service life of the device is prolonged.

The application provides a method, device, medium and equipment for determining a worst bias point of hot carrier effect, the method comprising: constructing a hot carrier effect model of an FDSOI device; determining parameter values of each model parameter in the hot carrier effect model, the model parameters comprising: a time power law, a first fitting parameter, a second fitting parameter, a process parameter, a threshold voltage, a drain voltage and a saturation drain voltage; creating an input netlist according to simulation requirements; simulating the hot carrier effect model based on the input netlist to determine a worst bias point of hot carrier effect; thus, the HCI effect of the FDSOI device can be simulated under the condition that each parameter (except the gate voltage) of the hot carrier effect model is known, the corresponding simulation result (the degradation amount of the threshold voltage) under different gate voltages is obtained, the worst bias point is determined according to the simulation result, and the performance of the FDSOI device can be effectively improved.

The invention discloses an array substrate, a display panel and a display device.An active layer of the array substrate comprises a channel region, a source electrode connecting region and a drain electrode connecting region, the source electrode connecting region and the drain electrode connecting region are located on the two opposite sides of the channel region, a source electrode is connected with the source electrode connecting region, a drain electrode is connected with the drain electrode connecting region, and the active layer is provided with at least one through hole; the orthographic projection of the through hole on the substrate is at least partially located in the orthographic projection range of the channel region on the substrate or the orthographic projection range of the drain electrode connection region on the substrate; holes are punched in the channel region or the drain electrode connecting region of the active layer so as to disperse a transverse electric field, reduce the hot carrier effect and improve the performance of the display panel.

The invention discloses a wide-temperature-range deep N-well SiC LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method of the wide-temperature-range deep N-well SiC LDMOS device, and relates to the technical field of semiconductor devices. Then forming a drift layer containing a deep N well structure, a channel region, a body electrode region, a source-drain region and a key doped region of a top doped region in the epitaxial layer through a multi-time selective ion implantation process, and growing a field oxide layer, a gate oxide layer and a polycrystalline silicon field plate on the surface of the device; and finally preparing a body electrode, a source electrode, a gate electrode, a drain electrode and an isolation electrode through a metal deposition and patterning process. The drift layer of the deep N-well structure is formed through ion implantation, the drift layer, the top doping layer and the epitaxial layer form a double-RESURF structure, electric field modulation is achieved, electric field distribution at high temperature can be remarkably optimized, the hot carrier effect is restrained, and therefore the performance of an LDMOS device in high-temperature application is improved.

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure for improving the HCI effect and a manufacturing method thereof, and the method comprises the steps: providing a substrate which comprises a semiconductor substrate, a substrate oxide layer and a hard mask layer which are stacked in sequence; a shallow trench corresponding to the position of the grid electrode is formed in the semiconductor substrate; etching to remove the end part of one side, close to the shallow trench, of the substrate oxide layer, after etching, the side surface of one side, close to the shallow trench, of the substrate oxide layer shrinks inwards to form a pit, and an opening of the pit intersects with the surface of the hard mask layer; filling the shallow trench to obtain an isolation layer, wherein the substrate oxide layer and the isolation layer encircle at the pit to form a hole; the hard mask layer is removed, a notch is formed in the intersection position of the hole and the hard mask layer, and the hole is communicated with the external environment through the notch; and depositing a gate material layer on the surface of the substrate oxide layer, enabling the gate material to enter the hole along the gap during deposition, and filling to form a control gate body. The preparation process is simple, the hot carrier effect of the device can be improved, and the service life of the device is prolonged.

The LDMOS device structurally comprises a first field oxide structure located in a drift region, the first field oxide structure is provided with a first side wall and a second side wall which are opposite to each other, the first side wall is step-shaped, the second side wall is inclined, and the included angle between the second side wall and the bottom of the first field oxide structure is an obtuse angle; the gate structure is located on the surface of the substrate, part of the gate structure is located on the body region, and the other part of the gate structure is located on the drift region; the source region is positioned in the body region on one side of the gate structure; the first field oxide structure is located between the drain region and the gate structure, the first side wall is close to the gate structure, and the second side wall is close to the drain region, so that the breakdown voltage can be improved, the hot carrier effect can be inhibited, local electric field concentration can be weakened, and the reliability of the device can be improved. And the reliability of the device is improved on the whole.

The application discloses a MOSFET structure and a preparation method thereof, and belongs to the technical field of semiconductors; the MOSFET structure is composed of a plurality of mutually-parallel MOS cells, and a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source and a gate; the application sets a lightly-doped N layer in the middle of an N drift layer, and cooperates with the design of arc-shaped side-symmetrical P-layers on both sides, so that the electric field distribution in the device is effectively optimized; the lightly-doped N layer widens the depletion region between the channel and the drain, weakens the penetration of the drain electric field to the channel, the arc-shaped side-symmetrical P-layers are in direct contact with the N substrate layer to form a lateral field limiting ring, the electric field concentration is further dispersed, the drain-induced barrier lowering effect and the hot carrier effect are reduced, the control ability of the gate to the channel is enhanced, and thus the problems of the increase of subthreshold swing and the threshold voltage drift are inhibited, and the switch controllability of the device is improved.

The invention provides a laterally diffused metal oxide semiconductor transistor and a manufacturing method thereof. The transistor includes a substrate, a gate structure, a source region, and a drain region. The key point is that a groove is formed in the substrate, and the source electrode region is at least partially formed in the groove. According to the invention, the grooves are formed in the source electrode region, so that the transmission path of current carriers is prolonged, the control capability of the grid electrode is enhanced, and the peak value of a high electric field near the drain electrode is effectively alleviated. Therefore, the structure can obviously inhibit the hot carrier effect and reduce the substrate current, so that the long-term working reliability and the service life of the device are improved, and the structure is particularly suitable for the high-reliability application fields of automotive electronics, power management chips and the like.

The application provides a vertical cavity surface emitting laser chip, which comprises a substrate and, from bottom to top, a buffer layer, an N-type DBR layer, a first SCH layer, a second SCH layer, a quantum well structure layer, a third SCH layer, an oxidation structure layer, a P-type DBR layer and a P-type contact layer, wherein a tunneling layer is prepared between the first SCH layer and the quantum well structure layer, the band gap of the tunneling layer is larger than that of the quantum well structure layer, carriers are transmitted to the tunneling layer through the N-type DBR layer and the first SCH layer, and then are injected into the quantum well structure layer in a tunneling mode to be transmitted in a tunneling mode. The application increases the tunneling layer between the SCH layer and the quantum well structure layer, and optimizes the thickness of the barrier layer in the quantum well structure layer, so that the carriers are injected into the quantum well structure layer in a tunneling mode and are transmitted in a tunneling mode between the quantum well layer and the barrier layer, thereby improving the carrier transmission effect and the hot carrier effect and increasing the differential gain, and finally realizing high modulation bandwidth.

The invention relates to a high-voltage semiconductor device and a manufacturing method thereof, the high-voltage semiconductor device comprises a substrate, an N-type drift region, a high-voltage N well region, a P-type body region, a source electrode and a grid electrode, and the N-type drift region is arranged on the substrate; the high-voltage N well region, the P-type body region and the source electrode are arranged in the N-type drift region, and the P-type body region is connected with the source electrode; the grid electrode is arranged on the upper surface of the N-type drift region, and the high-voltage N well region, the P-type body region and the source electrode are arranged close to the upper surface of the N-type drift region. The design of the high-voltage N-well region can better control charge distribution, and is beneficial to uniformizing an electric field, reducing stray capacitance in the device and reducing a hot carrier effect, thereby improving the reliability of the device in long-term use; in addition, the high-voltage N-well region allows a more compact device layout, which means that more functions can be integrated on the same silicon wafer area.

The application provides a forming method of a semiconductor device, comprising the following steps: providing a substrate; performing P-well ion implantation of a first active region; forming a first gate layer on the substrate of the first active region; forming a second gate layer on the substrate of a second active region; performing maskless N-type drain light-doped ion implantation; performing N-well ion implantation and P-type drain light-doped ion implantation of the second active region under the same mask. The N-well ion implantation and the P-type drain light-doped ion implantation share the same mask under a low-cost and high-performance platform processing; after the etching of the gate layer, the maskless N-type drain light-doped ion implantation is performed under the condition that the photoresist layer after the etching of the gate layer is reserved, so that the gate layer is prevented from being punched by the N-type light-doped ion implantation. The mask for forming the N-well and the N-type drain light-doped is saved. Under the two LDD ion implantation processes, the hot carrier effect performance of the NMOS tube is ensured, the substrate leakage current is reduced, and the reliability test is passed.

The invention relates to a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the steps of providing a semiconductor material layer; forming a first mask layer, wherein the first mask layer forms a first opening exposing the first region of the semiconductor material layer and at least shields the second region of the semiconductor material layer; performing a first ion implantation process on the first region based on the first mask layer to form a first drift region of the first conductive type; forming a second mask layer which forms a second opening exposing the second area and at least shields the first area; performing a second ion implantation process on the second region based on the second mask layer to form a first well region of the first conductive type; the second injection concentration of the second ion injection process is greater than the first injection concentration of the first ion injection process; forming a second drift region of a second conductive type; a first source region and a first drain region are respectively formed in the first well region and the second drift region. Therefore, the influence on the threshold voltage is reduced while the hot carrier effect is improved.