3results about How to "Good gating ability" patented technology

The application discloses a kind of copolymer organic semiconductor devices based on isolation and interconnection and preparation method, including substrate, photoetching blocking layer, insulating isolation layer, N organic field effect transistor and N-1 interconnection line;Photoetching blocking layer includes isolation layer and inorganic dielectric layer;Isolation layer is opened with N longitudinal through isolation groove along length direction;Inorganic dielectric layer includes lower dielectric layer and upper dielectric layer;Lower dielectric layer is located in N isolation, and upper dielectric layer is laid on the top of isolation layer and lower dielectric layer;Each organic field effect transistor includes semiconductor layer, source, drain and gate;Semiconductor layer is laid in the isolation groove at the bottom of corresponding lower dielectric layer section, and its material is organic copolymer.The application effectively utilizes isolation groove and photoetching blocking layer, and the semiconductor layer of different semiconductor materials is wrapped and isolated, so as to realize the integration of different organic field effect transistors on the same substrate, and the organic field effect transistor can realize effective interconnection.

This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode. The channel structure includes a stack of multiple nanosheets, a gate electrode surrounding the nanosheets, and a cavity. The cavity is located at least between the channel structure and the substrate. The cavity is formed by the channel structure, the source electrode, the drain electrode, and the substrate surrounding the cavity. In other words, the cavity is located below the channel structure, the source electrode, and the drain electrode, without any contacting film layers, thus forming a fully floating structure. This can significantly improve the gate control performance of the semiconductor device, reduce the subthreshold swing of the semiconductor device, reduce leakage current and parasitic capacitance, increase the drive current, and improve the performance of the semiconductor device.

This invention discloses a gallium oxide field-effect transistor and its fabrication method, relating to the field of gallium oxide device technology. The gallium oxide field-effect transistor includes, from bottom to top, a drain, a gallium oxide substrate, a gallium oxide epitaxial layer, a gallium oxide current blocking layer, and an n-type electrode. + Type-n highly doped gallium oxide layer; n + The surface of the highly doped gallium oxide layer has grooves, the bottom of which abuts into the gallium oxide epitaxial layer; it also includes: a gallium oxide gate dielectric layer located on the bottom wall and sidewalls of the grooves and n + On a portion of the surface of a highly doped gallium oxide layer; the gate, located on the surface of the gallium oxide gate dielectric layer; the source, located on the n-type... + On the surface of a highly doped gallium oxide layer, this invention effectively solves the problem of a large number of dangling bonds failing to form due to lattice mismatch between the silicon oxide or aluminum oxide gate dielectric layer and gallium oxide, reduces the interface state density between the gate dielectric layer and gallium oxide, and effectively improves characteristics such as gate leakage current and threshold voltage drift.