Two-dimensional material/semiconductor hetero-junction tunneling transistor and preparation method thereof
A two-dimensional material and semiconductor technology, applied in the field of nanoelectronics, can solve problems such as difficult to achieve high doping, achieve low power consumption, large on-state current, and increase the effect of on-state current
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[0054] The present invention will be further described below by example. It should be noted that the purpose of the disclosed embodiments is to help further understand the present invention, but those skilled in the art can understand that various replacements and modifications are possible without departing from the spirit and scope of the present invention and the appended claims of. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the protection scope of the present invention is subject to the scope defined in the claims.
[0055] A specific example of the preparation method of the present invention includes Figure 3 to Figure 10 Process steps shown:
[0056] 1) Using a bulk silicon wafer with a crystal orientation of (100) as the semiconductor substrate (1), using ion implantation BF 2 + P-type doping is carried out on the semiconductor substrate by the method, the doping energy is 40KeV, and the region other than...
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