According to one embodiment of the present invention, a method of operation of a memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to a plurality of
source lines comprises: a step of applying a first
voltage to a selected word line connected to a selected
memory cell among a plurality of word lines; a step of applying a second
voltage to a selected
bit line connected to a selected
memory cell among a plurality of bit lines; and a step of applying a ground
voltage to a plurality of
source lines, non-selected word lines among a plurality of word lines, and non-selected bit lines among a plurality of bit lines, wherein the first voltage is greater than the ground voltage and the second voltage is less than the ground voltage, and each of the plurality of memory cells includes a ferroelectric tunnel field-effect
transistor (FeTFET) element.