6 results about "Tunnel field-effect transistor" patented technology

According to one embodiment of the present invention, a method of operation of a memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to a plurality of source lines comprises: a step of applying a first voltage to a selected word line connected to a selected memory cell among a plurality of word lines; a step of applying a second voltage to a selected bit line connected to a selected memory cell among a plurality of bit lines; and a step of applying a ground voltage to a plurality of source lines, non-selected word lines among a plurality of word lines, and non-selected bit lines among a plurality of bit lines, wherein the first voltage is greater than the ground voltage and the second voltage is less than the ground voltage, and each of the plurality of memory cells includes a ferroelectric tunnel field-effect transistor (FeTFET) element.

The present application relates to Si 1‑x Ge x / Si heterojunction gate oxide layer ladder channel double gate tunnel field effect transistor; the purpose is to further improve the on-state current and on-off current ratio of double gate TFET (DGTFET) and reduce the subthreshold swing on the basis of relieving the bipolar effect problem of double gate TFET (DGTFET); it comprises a drain region, a channel region and a source region, the channel region is a ladder structure, the thin end of the channel region is connected with the source region, and the thick end of the channel region is connected with the drain region; both sides of the channel region are provided with ladder structure low-k gate oxide layers matched with the shape of the channel region, the step surface of the low-k gate oxide layer is located on the left side of the step surface of the channel region, and the thickness of the thin end of the low-k gate oxide layer is smaller than the thickness of the thick end of the low-k gate oxide layer; both sides of the thin end of the low-k gate oxide layer are provided with high-k gate oxide layers with the same length; the low-k gate oxide layer is prepared by using low-k dielectric material, and the high-k gate oxide layer is prepared by using high-k dielectric material; the source region is prepared by using Si 1‑x Ge x , the channel region and the drain region are prepared by using silicon.

Asymmetry may be used to tune electrical properties of tunnel field effect transistors (TFETs). An exemplary TFET includes a gate stack disposed over a semiconductor layer, a source disposed in the semiconductor layer, and a drain disposed in the semiconductor layer. The gate stack includes a gate electrode disposed over a gate dielectric. The gate stack is disposed between the source and the drain. The source has a first conductivity type, and the drain has a second conductivity type different than the first conductivity type. The gate stack is asymmetric. For example, the gate stack has an asymmetric gate dielectric, an asymmetric gate electrode, asymmetric gate footing, asymmetric sidewalls, or combinations thereof. In some embodiments, the source and the drain have asymmetric profiles. In some embodiments, the semiconductor layer is a semiconductor fin, and the gate stack wraps the semiconductor fin.

Tunnel field effect transistor, TFET (400, 500, 1400, 1500, 1600), comprising: an active homotransition region formed above a substrate, wherein the active homotransition region comprises: a doped source region, an undoped channel region, a wrapped drain underlap region, and a doped drain region; and a gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b) and a gate dielectric layer formed on the undoped channel area between the source area and the wound drain overlap area.

The application provides a tunnel field effect transistor and a forming method thereof. The tunnel field effect transistor comprises a semiconductor substrate, a metal gate structure located on the surface of the semiconductor substrate, a side wall located on the side wall of the metal gate structure, a source and a drain respectively located in the semiconductor substrate on both sides of the metal gate structure, and a heavily doped region located in the semiconductor substrate below the channel of the tunnel field effect transistor. The doping type of the heavily doped region is the same as that of the source, and the doping concentration of the heavily doped region is higher than that of the source. The tunnel field effect transistor and the forming method thereof can significantly improve the driving current of the tunnel field effect transistor.

Hybrid FETs and methods of forming such hybrid FETs are disclosed. An example hybrid FET includes a channel region, a first region, a second region, a third region, and two gates. A gate may wrap around a portion of the channel region. The channel region may be over a first substrate (e.g., a substrate on which the channel region is formed) but cross a second substrate. The channel region is shared by a MOSFET and a TFET. The first region and second region constitute the source and drain of the MOSFET and are doped with dopants of the same type. The first region and third region constitute the source and drain of the TFET and are doped with dopants of opposite types. The third region may be placed at the opposite side of the second substrate from the first region and the second region.