Line-tunneling tunnel field-effect transistor (TFET) and manufacturing method

Abstract

A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gat electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit under 35 U.S.C. §119(e) of U.S. provisional application Ser. No. 61 / 488,934, filed May 23, 2011, and claims the benefit under 35 U.S.C. §119(a)-(d) of European application No. 11173950.4, filed Jun. 14, 2011, the disclosures of which are hereby expressly incorporated by reference in their entirety and are hereby expressly made a portion of this application.FIELD OF THE INVENTION[0002]The embodiments relate to the field of semiconductor devices and nanotechnology. More specifically, the embodiments relate to tunnel field effect transistors (TFET) where the tunnelling effect is based on band-to-band tunnelling. Furthermore the embodiments relate to a method for manufacturing a semiconductor device, more particularly to a method for fabricating tunnel field effect transistors. More specifically the fabrication method relates to but is not limited to standard planar technology, double gate technology, FINFE...

AI Technical Summary

Benefits of technology

[0064]It is an advantage of the present invention that the spread of the onset voltage Vonset (i.e., the gate voltage at which BTBT tunneling occurs) with variations in the source-drain voltage VDS can be reduced significantly especially for semiconductor devices According to certain embodiments with small gate dielectric thickness (i.e., smaller equivalent oxide thickness EOT).

[0065]For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0066]The above and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Problems solved by technology

One of the problems due to the scaling down of CMOS transistors is that the power consumption keeps increasing.

This is partly because leakage currents are increasing (e.g., due to short channel effects) and because it becomes difficult to decrease the supply voltage.

However, all-silicon TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier.

Images