44 results about "Doping profile" patented technology

In embodiments a component includes a semiconductor layer sequence having a p-side semiconductor layer, an n-side semiconductor layer and an active zone located therebetween, wherein the active zone has a multiple quantum well structure including a plurality of quantum barrier layers and quantum well layers, the quantum barrier layers and the quantum well layers being arranged alternately along a vertical direction, wherein the active zone has at least one recess having facets extending obliquely to a main surface of the active zone, the recess being opened towards the p-side semiconductor layer, wherein, at least within the recess, the quantum barrier layers are n-doped and have a non-constant doping profile so that the component is configured to increase transport negatively charged charge carriers, from the n-side semiconductor layer towards the p-side semiconductor layer, based on the non-constant doping profile, and wherein, from the n-side semiconductor layer towards the p-side semiconductor layer, dopant concentrations of the quantum barrier layers gradually increase.

The invention discloses a multi-dimensional doped profile optimized ultrathin body MOSFET device and a preparation process thereof, and belongs to the technical field of semiconductor devices, the multi-dimensional doped profile optimized ultrathin body MOSFET device comprises a plurality of MOS cells which are parallel to one another, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell, side symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, the side symmetric P-layers are of rectangular outlines, and the top ends of the side symmetric P-layers make contact with the grid electrode; in the first embodiment, the laterally symmetrical P-layer and the N drift layer form a PN junction, a transverse depletion region is generated during reverse bias, the transverse electric field range is expanded, and local electric field concentration is avoided.

The invention relates to an electro-optical Mach-Zehnder modulator (1) comprising an input divider, first and second main waveguides (10p, 20p), and an output combiner (3). It also includes a first coplanar RF line (30) associated with the first main waveguide (10p). Finally, it includes a first additional waveguide (10a), not coupled to the input divider (2) and the output combiner (3), and having a positioning relative to a central track (33), a dimensioning and a doping profile symmetrical to those of the first main waveguide (10p), with respect to a plane of symmetry (Ps), orthogonal to the main plane (XY), parallel to the first main (10p) and additional (10a) waveguides, and passing through a center of the central track (33).

The invention discloses a charge compensation MOSFET with a graded epitaxial distribution and a method of manufacturing the same. A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type separating the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source region and the body region and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in the separate trench. The drift region has a generally linearly tapered first doping profile that increases from the body region toward a bottom of the trench including the field electrode, and a tapered second doping profile that increases from an end of the first doping profile toward the drain region at a greater ratio than the first doping profile.

An integrated circuit (IC) device including one or more corrugated channel structures formed in or over a semiconductor substrate, where a corrugated channel structure includes a first sidewall, a second sidewall and a top surface. In an example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the first sidewall to the second sidewall.

A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source / drain feature within a source / drain region adjacent to the dummy gate. In some cases, the source / drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source / drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

This invention provides an image sensor, a pixel structure, and a method for manufacturing the same. The pixel structure includes a photoelectric conversion region disposed in a semiconductor substrate and a conductive plate disposed above it. The conductive plate covers a first region of the photoelectric conversion region and induces a hole accumulation layer on its surface by receiving a bias signal, achieving electrical pinning. A doped pinning layer is disposed in a second region outside the projection range of the conductive plate, achieving physical pinning, wherein the doping concentration of the surface doping profile of the first region is lower than that of the second region. Through the synergistic effect of electric field modulation and doping modulation, a stable potential distribution is formed on the surface of the photoelectric conversion region, effectively suppressing dark current. Because high-concentration doping is avoided in the first region, the impact of doping compensation on the potential well is reduced, thereby maintaining a large charge storage space even under pixel miniaturization conditions, improving the full-well capacity and the dynamic range and signal-to-noise ratio of the image sensor.

This technology includes a vertical cell array transistor (VCAAT) with improved floating body effect. The array includes one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The array includes one or more channels extending vertically substantially orthogonal to the first and second horizontal directions such that the bit lines intersect the source / drain regions of the multiple channels and the word lines intersect the gate regions of the multiple channels. The array includes a case where the source / drain region has a first section adjacent to the source / drain junction and a second section adjacent to the channel body, and the first section has a higher doping concentration than the second section.

A semiconductor device includes a semiconductor body having a first major surface. A trench formed in the semiconductor body extends from the first major surface into the semiconductor body along a first direction, and includes a field dielectric positioned between a field electrode and the semiconductor body. A thickness of the field dielectric increases along the first direction from a first thickness at a first distance from the first major surface to a second thickness at a second distance from the first major surface. A difference between the second and first distances along the first direction is at most 20% of a total height of the field electrode. The second thickness is at least 1.1 times the first thickness. A drift region has a doping profile along the first direction, with a slope that changes along the first direction between the first and second distances from the first major surface.

A MEMS (microelectromechanical system) resonator (150) comprising a substrate (105), a resonator element (100), and a cavity (110). The resonator element (100) is separated from the substrate (105) by said cavity (110), and the resonator element (100) comprises a layer of single-crystalline silicon (101). The layer of single-crystalline silicon (101) is doped with phosphorus atoms to obtain a specific doping profile.

A bipolar transistor and a manufacturing method are disclosed. The bipolar transistor includes a collector region having a first doped portion located in a substrate and a second doped portion overlying and contacting a region of the first doped portion. The collector region has a doping profile having a peak at a first portion and decreasing from the peak to a second portion.

Ti-doped sapphire on arbitrary substrates is provided by Ti-doping an undoped sapphire wafer, then layer transferring part of the resulting doped surface region to another substrate. The Ti-doping can be laterally uniform or laterally patterned. Improved control over the vertical doping uniformity and / or lateral doping contrast can be provided by appropriately positioning the top and bottom surfaces of the layer to be transferred relative to the doping profile. For well-characterized doping profiles this can be done by defining the depths of the top and bottom surfaces of the layer to be transferred, since the characterization can relate doping concentration to depth.

A semiconductor structure is provided. The semiconductor structure includes a substrate with a first dopant concentration, a barrier layer, an epitaxial layer with a second dopant concentration and a plurality of doped regions. The barrier layer is formed on the substrate and has a first conductivity type with a gradient doping profile. The barrier layer has a higher dopant concentration level at a middle portion of the barrier layer and has a lower dopant concentration level at a top of the barrier layer and at a bottom of the barrier layer. The epitaxial layer is formed on the barrier layer. The plurality of doped regions are formed on the epitaxial layer. The higher dopant concentration level is greater than the first dopant concentration and is also greater than the second dopant concentration.

This utility model discloses a tunneling oxide passivation contact structure for a solar cell and a solar cell. The tunneling oxide passivation contact structure includes a substrate having a light-incident surface and a back-light surface disposed opposite to each other. The back-light surface is provided with, from the side closest to the substrate to the side furthest from the substrate, a first tunneling oxide layer, a lightly doped layer, a heavily doped carbon-doped layer, a second tunneling oxide layer, and a heavily doped undoped carbon layer. The total thickness of the heavily doped carbon-doped layer and the heavily doped undoped carbon layer is 30-140 nm. This utility model provides a tunneling oxide passivation contact structure for a solar cell. By setting a distributed doping structure of lightly doped layer / heavily doped carbon-doped layer / second tunneling oxide layer / heavily doped undoped carbon layer, it optimizes carrier transport and interface passivation, improves contact stability and resistance to silver ion erosion, and has advantages such as controllable doping profile and strong process compatibility, significantly improving cell performance.

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having retrograde doping concentration in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a retrograde doping profile in which a doping concentration is highest at a junction of the base and the collector and decreases through a portion of the collector to about 95% less to about 99.5% less. Such bipolar transistors can be implemented, for example, in power amplifiers.

An integrated circuit (IC) device including one or more corrugated channel structures formed in or over a semiconductor substrate, wherein a corrugated channel structure includes a first sidewall, a second sidewall, and a top surface. In one example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the first sidewall to the second sidewall.

The present disclosure describes a method to form silicon germanium (SiGe) source / drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.

The application discloses a kind of multi-dimensional doped profile optimization type ultra-thin body MOSFET device and preparation process thereof, belong to semiconductor device technical field, including by a plurality of mutually juxtaposed MOS cell is formed, single MOS cell includes drain, semiconductor epitaxial layer, source and gate;The semiconductor epitaxial layer includes N substrate layer, N drift layer, P+ layer, N well layer and P well layer, the middle of N drift layer of single MOS cell is equipped with lightly doped N layer, the inside of single MOS cell and located N drift layer left and right sides are equipped with side symmetry P- layer, the side symmetry P- layer is rectangular profile, and the top of side symmetry P- layer is in contact with the gate;In embodiment one, side symmetry P- layer and N drift layer form PN junction, produce lateral depletion region when reverse bias, expand lateral electric field range, avoid local electric field concentration.

The present technology includes vertical cell array transistor (VCAAT) with improved floating body effect. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source / drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source / drain region has a first section adjacent to a source / drain junction and a second section adjacent to a channel body, where the first section has a doping concentration that greater than a doping concentration of the second section.

The invention relates to a method for depositing an SiC layer, wherein an NH3-containing first doping gas flow (D1), a second N2-containing doping gas flow (D2), a C2H4-containing first growth gas flow (Q1) and an HCLS3-containing second growth gas flow (Q2) flow in a horizontal direction over a heated substrate. The two doping gas flows (D1, D2) are fed, in a manner controlled separately from one another, into a process chamber (2) through gas inlet zones (4, 5, 6) arranged vertically one above the other. The mass flows of the doping gas flows (D1, D2) or the vertical position of the gas inlet zones (4, 5, 6) through which the two doping gas flows (D1, D2) flow are selected such that they generate first and second doping profiles (a, b) which are oppositely curved in relation to one another and therefore by way of a beneficial selection of the ratio of the doping gas flows (D1, D2) and an additional argon feed, a homogeneous dopant profile can be achieved in the deposited layer.

The invention relates to a split gate semiconductor with non-uniform trench oxide. A metal oxide semiconductor field effect transistor (MOSFET) includes a plurality of parallel trenches. Each such trench includes a first electrode coupled to a gate terminal of the MOSFET and a second electrode physically and electrically isolated from the first electrode. The second electrode is located below the first electrode in the trench. The second electrode includes at least two different widths at different depths below the major surface of the MOSFET. A trench may be formed in the epitaxial layer. The epitaxial layer may have a non-uniform doping profile relative to a depth below a major surface of the MOSFET. The second electrode may be electrically coupled to a source terminal of the MOSFET.

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device, which may be applied to the field of semiconductor technology. The semiconductor device includes: a first source / drain layer, a channel layer and a second source / drain layer sequentially provided in a vertical direction on a substrate, where the channel layer is connected between the first source / drain layer and the second source / drain layer, and the channel layer has a doping profile along the vertical direction, in which a middle portion of the channel layer has a high doping concentration and end portions of the channel layer have a low doping concentration; and a body contact connected to the middle portion of the channel layer, where the middle portion of the channel layer has a height in the vertical direction greater than a height of the body contact in the vertical direction.

The application provides a semiconductor electrical property testing method and testing device. The method comprises: obtaining a semiconductor micro-Hall testing structure comprising at least one doping element; measuring the electrical parameter of the testing structure; removing a thin layer with a specific thickness from the testing structure by secondary ion mass spectrometry, and performing atomic composition analysis on the removed material; again measuring the electrical parameter of the testing structure; repeating the two steps until the distribution information of the doping concentration of the active doping element and the initial doping element in the testing structure is obtained, and calculating the distribution information of the doping efficiency of the testing structure according to the distribution information of the doping concentration. The application can combine the electrical property with the doping concentration, obtain the distribution information of the semiconductor electrical property and the doping concentration, deduce the distribution of the doping efficiency, and remove the thin layer controllably by the secondary ion mass spectrometry technology, so that the semiconductor doping profile information with higher precision is obtained.

The present technology includes vertical cell array transistor (VCAAT) with improved floating body effect. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source / drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source / drain region has a first section adjacent to a source / drain junction and a second section adjacent to a channel body, where the first section has a doping concentration that greater than a doping concentration of the second section.

A light sensitive semiconductor structure comprises:a substrate;a doped upper region of said substrate having a first type of doping;a first implant region located below and being in direct contact with said doped upper region, said first implant region having a second type of doping so that a pn-junction is located between said doped upper region and said first implant region; anda second implant region located below said first implant region and having said second type of doping, and wherein a peak in a doping profile of said second type of doping is located in said second implant region.

A silicon-photonic optical modulator includes an optical input; and an optical waveguide that is connected to the optical input and that is configured to propagate quasi-transverse-magnetic (quasi-TM) polarized light. The optical waveguide is configured as a rib waveguide that includes a rib arranged on a slab. The rib includes at least one dopant. An average concentration of the at least one dopant in a vertical doping profile in a lowermost portion of the rib is larger than an average concentration of the at least one dopant in the vertical doping profile in an uppermost portion of the rib. The uppermost portion of the rib has a height that is between 20% and 80% of a height of the rib waveguide. The lowermost portion of the rib includes a remainder of the rib below the uppermost portion.

To provide an electro-optic modulator in silicon photonics which can achieve a higher bandwidth and / or lower loss than other electro-optical modulators.SOLUTION: A silicon-photonic optical modulator includes: an optical input; and an optical waveguide that is connected to the optical input and that is configured to propagate quasi-transverse-magnetic (quasi-TM) polarized light. The optical waveguide is configured as a rib waveguide that includes a rib arranged on a slab. The rib includes at least one dopant. An average concentration of the at least one dopant in a vertical doping profile in a lowermost portion of the rib is larger than an average concentration of the at least one dopant in the vertical doping profile in an uppermost portion of the rib. The uppermost portion of the rib has a height that is between 20% and 80% of a height of the rib waveguide. The lowermost portion of the rib includes a remainder of the rib below the uppermost portion.SELECTED DRAWING: Figure 1

The invention relates to a method for depositing an SiC layer, wherein an NH3-containing first doping gas flow (D1), a second N2-containing doping gas flow (D2), a C2H4-containing first growth gas flow (Q1) and an HCLS3-containing second growth gas flow (Q2) flow in a horizontal direction over a heated substrate. The two doping gas flows (D1, D2) are fed, in a manner controlled separately from one another, into a process chamber (2) through gas inlet zones (4, 5, 6) arranged vertically one above the other. The mass flows of the doping gas flows (D1, D2) or the vertical position of the gas inlet zones (4, 5, 6) through which the two doping gas flows (D1, D2) flow are selected such that they generate first and second doping profiles (a, b) which are oppositely curved in relation to one another and therefore by way of a beneficial selection of the ratio of the doping gas flows (D1, D2) and an additional argon feed, a homogeneous dopant profile can be achieved in the deposited layer.

An integrated circuit (IC) device including one or more corrugated channel structures formed in or over a semiconductor substrate, where a corrugated channel structure includes modified first and second sidewalls and a modified top surface. In an example, the corrugated channel structure is provided with a substantially uniform distribution profile of a dopant across a horizontal plane from the modified first sidewall to the modified second sidewall.