9 results about "Pn diode" patented technology

The application provides a PN diode based on a non-doped single crystal substrate and a preparation method thereof. ‑ a GaN layer, a p + GaN layer and an anode metal layer; wherein the non-doped single crystal structure comprises a non-doped drift layer on a front surface and an ion implantation layer on a back surface, the ion implantation layer is in contact with the cathode metal layer as a substrate of the PN diode, and the non-doped drift layer is in contact with the p ‑ GaN layer to form a PN junction. The PN diode based on the non-doped single crystal substrate and the preparation method thereof have the advantages of simplifying the preparation process, reducing the manufacturing cost, reducing the interface pollution, and improving the electrical performance and long-term reliability of the device.

This invention provides a GaNHEMT device structure with anti-destructive breakdown function, comprising: a substrate, wherein a first nucleation layer and a GaN buffer layer are sequentially formed on the substrate along a direction away from the substrate; a pN diode, the pN diode including a p+ doped region and an N+ doped region respectively formed in a first region and a second region on the surface of the GaN buffer layer, and an anode and a cathode respectively formed on the p+ doped region and the N+ doped region; wherein the first region and the second region are opposite sides along the surface of the GaN buffer layer; and a GaNHEMT device formed on the GaN buffer layer; wherein the breakdown voltage of the pN diode is lower than the breakdown voltage of the GaNHEMT device. This invention solves the problem that GaNHEMT devices will undergo destructive breakdown when a large voltage or continuous high-voltage stress is applied between the source and drain of the GaNHEMT device, thereby improving the reliability of the GaNHEMT device.

This invention discloses a method for achieving JTE junction termination in a GaN vertical structure pn diode, belonging to the field of wide bandgap semiconductor materials. The invention involves hydrogen plasma treatment near the etch boundary of the heavily doped p-type GaN layer, causing H ions to form Mg-H complexes with Mg acceptors in the heavily doped p-type GaN layer. Simultaneously, thermal annealing is used to diffuse H ions within the heavily doped p-type GaN, creating a gradually varying hole concentration gradient from the main junction region to the junction edge, thereby achieving JTE junction termination. Compared to existing junction termination technologies, this invention involves no etching, low damage, and effectively weakens the electric field accumulation effect, improving the device's breakdown voltage.

The present application provides a technique for suppressing current degradation of a GaN device having a pn junction like a pn diode. A manufacturing method for a gallium nitride laminated substrate for manufacturing a device having a pn junction includes the following steps: preparing an n-type gallium nitride single crystal substrate having a diameter of 50 mm or more and a low-index crystal plane closest to a main surface being a (0001) plane; growing an n-type gallium nitride single crystal layer on the substrate; performing dehydrogenation treatment on the laminated substrate on which the n-type gallium nitride single crystal layer is grown; growing a p-type gallium nitride single crystal layer on the laminated substrate on which the dehydrogenation treatment is performed; and further performing dehydrogenation treatment on the laminated substrate on which the p-type gallium nitride single crystal layer is grown.

The invention relates to a fast recovery MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, and belongs to the technical field of power devices. The epitaxial layer is arranged on the substrate; at least two body regions are arranged in the epitaxial layer, and a partition structure is formed between the two body regions; an active region and an accumulation type channel are arranged in the body region, and the accumulation type channel is located on one side close to the partition structure; the gate structures are arranged on the epitaxial layer, and the number of the gate structures is at least two; the source dielectric layer is arranged on the partition structure and covers the accumulation type channel and the partition structure; the source dielectric layer is located between the two gate structures; and the source electrode is arranged on the source region and the source dielectric layer. According to the invention, the partition structure, the accumulation type channel and the source dielectric layer are arranged, so that the accumulation type channel is opened when the voltage of the source electrode and the voltage of the drain electrode are greater than a threshold value, thereby inhibiting the opening of a parasitic PN diode, and achieving high reliability and low loss while guaranteeing high voltage resistance and high frequency performance.

A non-volatile memory device includes: an insulation layer; a PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a writing wire which is conductive and is electrically connected to the anode end of the PN diode; a memory unit on the PN diode, the memory unit being electrically connected to a cathode end of the PN diode; and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the PN diode to write the data into the memory unit.

A semiconductor device includes a PN diode; a drain region; a source region; a gate region formed between the drain region and the source region; a first p-type guard ring and a NP guard ring surrounding the PN diode. The NP guard ring includes a n-type guard ring and a second p-type guard ring; a drain Silicon Controlled Rectified (SCR) formed in the drain region and including a highly-doped n-type drain region (N+ drain region) and a highly-doped p-type drain region (P+ drain region), the drain SCR electrically connected to a high voltage; a first guard ring SCR formed in the first p-type guard ring and including a first highly doped n-type region (first N+ region) and a first highly doped p-type region (first P+ region); and a second guard ring SCR formed in the NP guard ring and including a second N+ region and a second P+ region.

A non-volatile memory device includes: an insulation layer; a PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a writing wire which is conductive and is electrically connected to the anode end of the PN diode; a memory unit on the PN diode, the memory unit being electrically connected to a cathode end of the PN diode; and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the PN diode to write the data into the memory unit.

A semiconductor structure includes a region of semiconductor material of a first conductivity type. A doped region of a second conductivity type is within the region of semiconductor material at a first depth. A semiconductor device is in a first portion of the region of semiconductor material and includes a first current carrying region of the second conductivity type and a second current carrying region. A PN diode is in a second portion of the region of semiconductor material and includes a cathode region of the second conductivity type and anode region of the first conductivity type. The cathode region is coupled to the first current carrying region, the anode region is coupled to the doped region, and the doped region is configured to electrically isolate the semiconductor device from region of semiconductor material below the doped region in response to a forward bias applied to the semiconductor device.