20 results about "Pn diode" patented technology

The application discloses a multi-port electrostatic protection MOS structure, and belongs to the field of semiconductor devices and manufacturing. In the multi-port electrostatic protection MOS structure, a NPN current channel and a PN Diode current channel formed by a power supply anode, a power supply cathode and an I / O port are used to realize all-round protection between the power supply anode, the power supply cathode and the I / O port. In addition, compared with a plurality of ESD devices corresponding to an I / O port to a power supply cathode, an I / O port to a power supply anode and a power supply anode to a power supply cathode in the prior art, the application can realize the above multi-port electrostatic protection requirement through a single electrostatic protection MOS structure, thereby reducing the number of ESD devices and further saving the chip area.

The application provides a PN diode based on a non-doped single crystal substrate and a preparation method thereof. ‑ a GaN layer, a p + GaN layer and an anode metal layer; wherein the non-doped single crystal structure comprises a non-doped drift layer on a front surface and an ion implantation layer on a back surface, the ion implantation layer is in contact with the cathode metal layer as a substrate of the PN diode, and the non-doped drift layer is in contact with the p ‑ GaN layer to form a PN junction. The PN diode based on the non-doped single crystal substrate and the preparation method thereof have the advantages of simplifying the preparation process, reducing the manufacturing cost, reducing the interface pollution, and improving the electrical performance and long-term reliability of the device.

This invention provides a GaNHEMT device structure with anti-destructive breakdown function, comprising: a substrate, wherein a first nucleation layer and a GaN buffer layer are sequentially formed on the substrate along a direction away from the substrate; a pN diode, the pN diode including a p+ doped region and an N+ doped region respectively formed in a first region and a second region on the surface of the GaN buffer layer, and an anode and a cathode respectively formed on the p+ doped region and the N+ doped region; wherein the first region and the second region are opposite sides along the surface of the GaN buffer layer; and a GaNHEMT device formed on the GaN buffer layer; wherein the breakdown voltage of the pN diode is lower than the breakdown voltage of the GaNHEMT device. This invention solves the problem that GaNHEMT devices will undergo destructive breakdown when a large voltage or continuous high-voltage stress is applied between the source and drain of the GaNHEMT device, thereby improving the reliability of the GaNHEMT device.

This invention discloses a method for achieving JTE junction termination in a GaN vertical structure pn diode, belonging to the field of wide bandgap semiconductor materials. The invention involves hydrogen plasma treatment near the etch boundary of the heavily doped p-type GaN layer, causing H ions to form Mg-H complexes with Mg acceptors in the heavily doped p-type GaN layer. Simultaneously, thermal annealing is used to diffuse H ions within the heavily doped p-type GaN, creating a gradually varying hole concentration gradient from the main junction region to the junction edge, thereby achieving JTE junction termination. Compared to existing junction termination technologies, this invention involves no etching, low damage, and effectively weakens the electric field accumulation effect, improving the device's breakdown voltage.

A silicon-based electro-optical modulator based on a micro-ring structure and a modulation method thereof, the silicon-based micro-ring modulator comprising a straight waveguide and a ring waveguide adjacent to the straight waveguide, the ring waveguide comprising multiple modulation sections, the modulation sections adopting a depletion-type PN diode structure, and the P-type doped regions of two adjacent modulation sections being respectively located on the inner and outer sides of the micro-ring, and the N-type doped regions being opposite. Specifically, if the P-type doped region of the modulation section is located on the inner side of the micro-ring and the N-type doped region is located on the outer side of the micro-ring, then the P-type doped region of the PN junction of the adjacent modulation section is located on the outer side of the micro-ring and the N-type doped region is located on the inner side of the micro-ring. The two adjacent modulation sections are connected in series through a metal electrode distributed above the heavily doped region. The silicon-based micro-ring electro-optical modulator provided by the application reduces the junction capacitance through the segmented series connection of the PN junction, improves the bandwidth of the silicon-based micro-ring modulator, and is conducive to realizing higher-rate signal modulation.

The present disclosure relates to hybrid metal-oxide semiconductor capacitors with enhanced phase tuning, the disclosed embodiments improve the efficiency of phase tuning for optical devices such as hybrid semiconductor-on-metal capacitors (MOSCAPs) III-V / Si micro-ring lasers. The present disclosure integrates silicon devices into the waveguide structure of the optical devices disclosed herein, for example, waveguide resistor heaters, waveguide PIN diodes, and waveguide PN diodes. In some examples, these optical devices are MOSCAPs formed by a dielectric layer between two semiconductor layers, which achieve a small phase tuning via plasma dispersion and / or carrier dispersion effects that occur depending on the polarity of the bias voltage. According to the embodiments disclosed herein, the plasma dispersion and / or carrier dispersion effects are enhanced by heating, carrier injection, and / or additional plasma dispersion based on the disclosed silicon devices integrated into the waveguide.

The present application provides a technique for suppressing current degradation of a GaN device having a pn junction like a pn diode. A manufacturing method for a gallium nitride laminated substrate for manufacturing a device having a pn junction includes the following steps: preparing an n-type gallium nitride single crystal substrate having a diameter of 50 mm or more and a low-index crystal plane closest to a main surface being a (0001) plane; growing an n-type gallium nitride single crystal layer on the substrate; performing dehydrogenation treatment on the laminated substrate on which the n-type gallium nitride single crystal layer is grown; growing a p-type gallium nitride single crystal layer on the laminated substrate on which the dehydrogenation treatment is performed; and further performing dehydrogenation treatment on the laminated substrate on which the p-type gallium nitride single crystal layer is grown.

The invention relates to a fast recovery MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof, and belongs to the technical field of power devices. The epitaxial layer is arranged on the substrate; at least two body regions are arranged in the epitaxial layer, and a partition structure is formed between the two body regions; an active region and an accumulation type channel are arranged in the body region, and the accumulation type channel is located on one side close to the partition structure; the gate structures are arranged on the epitaxial layer, and the number of the gate structures is at least two; the source dielectric layer is arranged on the partition structure and covers the accumulation type channel and the partition structure; the source dielectric layer is located between the two gate structures; and the source electrode is arranged on the source region and the source dielectric layer. According to the invention, the partition structure, the accumulation type channel and the source dielectric layer are arranged, so that the accumulation type channel is opened when the voltage of the source electrode and the voltage of the drain electrode are greater than a threshold value, thereby inhibiting the opening of a parasitic PN diode, and achieving high reliability and low loss while guaranteeing high voltage resistance and high frequency performance.

A non-volatile memory device includes: an insulation layer; a PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a writing wire which is conductive and is electrically connected to the anode end of the PN diode; a memory unit on the PN diode, the memory unit being electrically connected to a cathode end of the PN diode; and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the PN diode to write the data into the memory unit.

An ESD protection diode includes two pairs of PN diodes in a semiconductor substrate (10), the two pairs of PN diodes being respectively formed of P-type and N-type diffusion layers (23, 24; 31, 32). The ESD protection diode includes a lateral bipolar transistor disposed between the two pairs of PN diodes in the semiconductor substrate, and the lateral transistor includes an P-type diffusion layer (25) having a polarity different from that of each terminal connected to an anode electrode (1), and the P-type and N-type diffusion layers (23, 24; 31, 32) The lateral bipolar transistor includes the first and second P-type diffusion layers (23, 24) connected to the anode electrode (1), the third P-type diffusion layers (25) formed between the first and second P-type diffusion layers (23, 24) and connected to a cathode electrode (2), and the first and second N-type diffusion layers (31, 32) formed in an N-type well (11) in the semiconductor substrate (10).

The application discloses a gallium oxide Pn diode based on a self-center-to-fourth-corner gradual P-type doping concentration structure and a preparation method, and mainly solves the problem that the prior art seriously increases the forward conduction resistance and power consumption of a device while improving the reverse breakdown voltage of the device. From bottom to top, the gallium oxide Pn diode comprises a cathode ohmic metal (1), a gallium oxide substrate (2), a gallium oxide drift layer (3), a P-type semiconductor layer (4), a high-doping-concentration P-type semiconductor layer (5) and an anode (6), wherein the P-type semiconductor layer is formed by sequentially depositing a plurality of semiconductor materials with different doping concentrations on the gallium oxide drift layer in the order of gradually increasing doping concentration from the center to the periphery, so as to reduce the peak electric field at the edge of the gallium oxide drift layer and the interior of the P-type semiconductor layer, form a good ohmic contact, and realize the reduction of the conduction resistance of the device while improving the reverse breakdown voltage of the device. The gallium oxide Pn diode improves the figure of merit of the gallium oxide device and can be used in electronic systems.

The invention relates to an integrated multi-device chip and package. A protection device is disclosed that may include a semiconductor substrate and a thyristor-type device formed within the semiconductor substrate, where the thyristor-type device extends from a first major surface of the semiconductor substrate to a second major surface of the semiconductor substrate. The protection device may include a first PN diode formed within a semiconductor substrate; and a second PN diode formed within the semiconductor substrate, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode.

A semiconductor device includes a PN diode; a drain region; a source region; a gate region formed between the drain region and the source region; a first p-type guard ring and a NP guard ring surrounding the PN diode. The NP guard ring includes a n-type guard ring and a second p-type guard ring; a drain Silicon Controlled Rectified (SCR) formed in the drain region and including a highly-doped n-type drain region (N+ drain region) and a highly-doped p-type drain region (P+ drain region), the drain SCR electrically connected to a high voltage; a first guard ring SCR formed in the first p-type guard ring and including a first highly doped n-type region (first N+ region) and a first highly doped p-type region (first P+ region); and a second guard ring SCR formed in the NP guard ring and including a second N+ region and a second P+ region.

The present invention provides a three-dimensional gallium nitride-based PN diode and a method for preparing the same. The three-dimensional gallium nitride-based PN diode comprises: a three-dimensional substrate having a plurality of device regions spaced apart on its outer surface, a plurality of devices correspondingly arranged on each device region, and an interconnecting dielectric layer covering the device surface and the non-device region of the three-dimensional substrate; each device comprises a first dielectric layer arranged on the surface of the three-dimensional substrate, and an n-type dielectric layer arranged on the side of the first dielectric layer facing away from the three-dimensional substrate. ‑ ‑GaN layer, set on n ‑ The p-GaN layer has a cathode on the side facing away from the 3D substrate, and a p-GaN layer, and an anode on the p-GaN layer, also facing away from the 3D substrate. The interconnect dielectric layer is fixed with a number of interconnect metals, connecting the corresponding anodes between devices via the interconnect metals, and also connecting the corresponding cathodes between devices via the interconnect metals. The diodes of this invention have excellent heat dissipation from the 3D substrate, a high degree of diode integration, superior electrical performance, a wider range of application scenarios, and improved device performance and lifespan.

The present invention discloses a fin-type gallium oxide PN diode with high withstand voltage and low on-resistance and a preparation method thereof, which mainly solves the problems of low breakdown voltage and high on-resistance of existing similar devices. The device comprises, from bottom to top, a cathode (1), a gallium oxide substrate (2), an n-type gallium oxide epitaxial layer (3), a semiconductor layer (4), and an anode (5). A plurality of grooves are etched on the gallium oxide epitaxial layer to form a fin-type structure (6). The semiconductor layer is made of p-type semiconductor material and is completely deposited outside the fin-type structure so as to form a PN junction diode with the gallium oxide epitaxial layer. An angle of 20° to 60° is set between the 001 crystal orientation of the gallium oxide substrate and the orientation of the fin-type structure. By changing the angle, the breakdown voltage of the device is increased. The doping carrier concentration of the gallium oxide epitaxial layer is 10 15 ~10 17 cm ‑3 The invention has the advantages of high breakdown voltage and low on-resistance and can be used in high-voltage and high-power power electronic systems.

The present invention, entitled "Integrated Multi-Device Chip and Package," discloses a protection device that may include a semiconductor substrate and a thyristor-type device formed within the semiconductor substrate, wherein the thyristor device extends from a first major surface of the semiconductor substrate to a second major surface of the semiconductor substrate. The protection device may include a first PN diode formed within the semiconductor substrate; and a second PN diode formed within the semiconductor substrate, wherein the thyristor-type device is electrically arranged in series between the first and second PN diodes.

A non-volatile memory device includes: an insulation layer; a PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a writing wire which is conductive and is electrically connected to the anode end of the PN diode; a memory unit on the PN diode, the memory unit being electrically connected to a cathode end of the PN diode; and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the PN diode to write the data into the memory unit.

A semiconductor structure includes a region of semiconductor material of a first conductivity type. A doped region of a second conductivity type is within the region of semiconductor material at a first depth. A semiconductor device is in a first portion of the region of semiconductor material and includes a first current carrying region of the second conductivity type and a second current carrying region. A PN diode is in a second portion of the region of semiconductor material and includes a cathode region of the second conductivity type and anode region of the first conductivity type. The cathode region is coupled to the first current carrying region, the anode region is coupled to the doped region, and the doped region is configured to electrically isolate the semiconductor device from region of semiconductor material below the doped region in response to a forward bias applied to the semiconductor device.

The present invention discloses a photoelectric in-situ active pixel sensor, wherein a device unit structure is formed on a hybrid substrate, wherein the hybrid substrate is composed of an SOI substrate and a semiconductor substrate. The device unit structure includes a MOS transistor and a photosensitive structure. The MOS transistor is formed on the semiconductor top layer of the SOI substrate, and the channel region of the MOS transistor is composed of the semiconductor top layer. The photosensitive structure includes an embedded PN diode, which includes a first electrode region heavily doped with a first conductivity type formed in the surface region of the semiconductor epitaxial layer, and a second electrode region composed of the semiconductor epitaxial layer and the semiconductor top layer at the bottom of the first electrode region. The first interface at the bottom of the dielectric buried layer at the bottom of the MOS transistor serves as a photogenerated carrier collection end. The first electrode region is connected to a first electrode composed of a front metal layer through a contact hole. The present invention also discloses a method for manufacturing a photoelectric in-situ active pixel sensor. The present invention can expand the depletion region and increase the separation and migration rate of photogenerated carriers.

A non-volatile memory element having a PN diode. The non-volatile memory element includes: an insulating layer that is electrically insulating; a PN diode formed in a monocrystalline silicon layer on the insulating layer; a write wire that is conductive and electrically connected to the front end of the PN diode; a memory cell located on the PN diode and electrically connected to the rear end of the PN diode; and a select wire located on the memory cell and electrically connected to the memory cell; wherein, when the non-volatile memory element is selected to write data, a current flows through the PN diode to write the data into the memory cell.