18 results about "Noise margin" patented technology

The invention discloses an anti-radiation SPH-14T SRAM (Static Random Access Memory) circuit and an anti-radiation SPH-14T SRAM chip combining polarity reinforcement and source isolation technologies, which are designed by adopting a polarity reinforcement principle that transistors of the same type have a single flip characteristic under spatial heavy ion bombardment, and the stability of redundant nodes S0 and S1 is ensured by utilizing the design method. And therefore, the anti-overturning capability of nodes in the circuit is enhanced. Secondly, the stability of a node Q and a node QB is improved through multiplexing of a pull-up PMOS tube and the source isolation technology, meanwhile, the circuit uses four transmission transistors for reading and writing, in the data writing process, a bit line writes data into an internal node QQB and an internal node S0S1 at the same time through transmission transistors N7, N8, N9 and N10, so that the data is more easily written into a storage node, and the stability of the storage node is improved. Therefore, the design greatly improves the data writing speed and noise margin (SNM) of the unit, and a simulation result shows that compared with the existing five SRAM units, the SPH-14T unit disclosed by the invention has more prominent advantages in the writing speed aspect and the noise margin aspect compared with other five SRAMs.

The embodiment of the invention provides a static memory and a read-write method thereof. The static memory includes: a memory cell; a word line; the word selection signal driving circuit comprises a first switch sub-circuit, a gradual change sub-circuit and a second switch sub-circuit, and the first switch sub-circuit is configured to write a first selection signal of an operation signal line into a first node under the control of an effective signal of a first control signal line; the gradual change sub-circuit is configured to enable the first level line and the second level line to be conducted based on the signal of the first node under the condition that the first control signal line provides an invalid signal, and discharge a first selection signal of the first node, so that the first node generates a gradual change second selection signal; and the second switch sub-circuit is configured to provide a slowly changing second selection signal to the word line under the control of an effective signal of a second control signal line. According to the invention, the noise margin of the read operation can be improved, and the read stability is improved.

The present invention relates to a CMOS SRAM cell having a trench structure and, more specifically, to a CMOS SRAM cell having a trench structure, the CMOS SRAM cell being manufactured using a vertical MOSFET of a trench structure having a gate, a source, and a drain that form a vertical structure, such that there is a current flow in an active region between trench gate electrodes and vertical source and drain regions, and thus being capable of exhibiting various advantages with respect to density, operating frequency, noise margin, current handling capacity, power consumption, and manufacturing steps, compared to a conventional CMOS SRAM cell having a planar structure.

The invention discloses a limit cycle oscillation suppression system and suppression method applied to a particle accelerator power supply, and solves the problem of limit cycle oscillation caused by mismatching of the duty ratio resolution of a PWM wave output by a controller and the sampling resolution of an ADC in the control of the existing particle accelerator power supply. On the basis of a digital communication architecture formed by connecting a DSP and an FPGA, extra hardware facilities are not needed, an HRPWM module of the DSP is used for outputting high-precision digital PWM waves to be matched with a sigma-delta modulator and a modulation strategy, noise margin is separated, the duty ratio of the power supply of the particle accelerator is modulated in an error feedback mode, and the duty ratio of the power supply of the particle accelerator is adjusted. The problem of limit cycle oscillation caused by mismatching of the high-precision ADC sampling resolution and the PWM wave duty ratio resolution can be effectively suppressed, the power output quality of the particle accelerator is improved, and the hardware cost is reduced.

The invention belongs to the technical field of phase-locked loops and filters, and particularly relates to an active loop filter for a low-jitter phase-locked loop. The pulse signal selection circuit and the signal transmission circuit provide stable input for the operational amplifier circuit; a resistance-capacitance circuit which cooperates with the operational amplifier circuit to realize frequency selection and amplitude control of the input signal; and the operational amplifier circuit is used for enhancing the amplitude of the output signal of the charge pump and converting the current signal into a stable voltage signal. The signal transmission circuit can reduce burrs and overshoot of signals, is good in voltage transmission characteristic, high in noise margin, high in anti-interference capability and low in power consumption, and can provide stable signals as input of an operational amplifier, so that the jitter performance of a phase-locked loop is optimized.

Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., −25° C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.

The invention discloses a charge sharing type SRAM (Static Random Access Memory) write auxiliary circuit and a control method thereof, the SRAM write auxiliary circuit comprises a first storage array, a second storage array and the charge sharing type write auxiliary circuit, the first storage array and the second storage array are respectively used for storing data, and storage units in the first storage array and the second storage array are arranged in the same way. When writing operation is carried out on the SRAM, dynamic adjustment of the power supply voltage of the storage unit for carrying out the writing operation in the storage array is realized through the charge sharing type writing auxiliary circuit, and the writing noise margin of the SRAM under low voltage can be improved, so that the power consumption of the SRAM is reduced; and for the storage unit which is not enabled, the power supply voltage of the storage unit is kept stable and unchanged, and data destruction is prevented. According to the invention, the writing stability of the SRAM under low voltage can be improved, and lower system working voltage can be supported and realized in a storage system realized by using the SRAM, so that the power consumption of the whole system is reduced.

To address noise impact on functional testing of logic cell of a circuit design, load adaptive processing is provided. The processing includes obtaining a plurality of noise margin data curves for different potential capacitive load on a logic cell. The processing includes performing noise impact on functional testing of a logic cell instance within the circuit design. The performing includes selecting a noise margin data curve of the plurality of curves based on a capacitive load of the logic cell instance of the circuit design, and determining whether the logic cell instance fails the noise impact on the functional testing based on comparing a noise pulse at the logic cell instance with the selected noise margin data curve. Further, the processing includes initiating one or more actions to facilitate resolution of the failure of the logic cell instance based on the logic cell instance of the circuit design failing the noise impact on the functional testing.

The application relates to a PLM-14T anti-radiation SRAM memory cell circuit. The PLM-14T anti-radiation SRAM memory cell circuit comprises ten NMOS transistors N1-N10 and four PMOS transistors P1-P4; P1 and P2 and P3 and P4 are cross-coupled, N1 and N2 correspond to P1 and P2 as pull-down tubes, N3 and N4 correspond to P3 and P4 as pull-down tubes, and N5 and N6 constitute a feedback loop for regulating a storage node; a main storage node Q and QB are connected with a bit line BL and BLB through N7 and N8 respectively, and a redundant storage node S1 and S0 are connected with the bit line BL and BLB through N9 and N10 respectively. The storage node of the application adopts a double pull-down loop to play a feedback regulation role, and the anti-flipping capability of the circuit storage node is enhanced. Meanwhile, the circuit uses four transfer transistors for reading and writing, and the data writing speed and the write noise margin of the unit are improved.

A test system implemented method is for measuring the noise margin of a repeating signal under test (SUT). The method includes determining a digitizer noise of a digitizer channel of the test system, and applying the repeating SUT to the digitizer channel of the test system. An oversampled equivalent-time waveform representation of the repeating SUT is acquired, and then a filtered waveform representation is obtained. A noise margin om of the repeating SUT is determine in accordance with the equation σm=(σc2+σi2−σd2)1 / 2, where σc is a standard deviation of a maximum amount of gaussian noise that can added to the filtered waveform representation without its symbol error rate (SER) exceeding a target value, σi is a standard deviation of the digitizer noise, and σd is a standard deviation of the noise components removed to obtain the filter waveform representation.

The invention discloses an SRAM total dose effect modeling simulation method based on an FDSOI device, and relates to the technical field of integrated circuits. According to the SRAM total dose effect modeling simulation method based on the FDSOI device, the state of the FDSOI device after total dose irradiation simulation is stored so as to be used for total dose effect simulation of an SRAM circuit; according to the method, the influence of the total dose effect on electrical parameters such as threshold voltage, mutual coupling capacitance and parasitic resistance of devices in a circuit can be comprehensively considered, so that more accurate result analysis is carried out on parameters such as noise margin of the SRAM under the irradiation condition, and the method can overcome the limitation of existing circuit-level simulation. The simulation directly carried out in TCAD can avoid errors caused by an existing circuit-level simulation device model, so that the simulation result is more accurate.

The application discloses a kind of SRAM total dose effect modeling simulation methods based on FDSOI device, it is related to integrated circuit technical field, the SRAM total dose effect modeling simulation methods based on FDSOI device of the embodiment of the application, the FDSOI device state after total dose irradiation simulation is saved to be used for the total dose effect simulation of SRAM circuit, the influence of total dose effect on the threshold voltage, mutual coupling capacitance, parasitic resistance etc. Electrical parameters of device in circuit can be considered comprehensively, so that the noise margin etc. Parameter of SRAM under irradiation condition is more accurate result analysis, this method can overcome the limitation of existing circuit level simulation.In TCAD directly carried out simulation can avoid the error caused by the device model of existing circuit level simulation, so that simulation result is more accurate.

This invention relates to the field of integrated circuit design technology, and more specifically, to a MOSFET-TFET hybrid 11T-SRAM cell circuit with high write noise margin, and a module employing this 11T-SRAM cell circuit layout. The 11T-SRAM cell circuit of this invention fully utilizes the advantages of TFET transistors at low voltages—better switching characteristics and lower subthreshold swing—and employs a break-lock latch structure to improve the cell's write noise margin. By using an NTFET transistor whose drain voltage is always no lower than the source voltage as the transfer control transistor, not only is the SRAM cell's write capability improved, but the forward bias current of the TFET device is also eliminated, reducing the cell's static power consumption.

This application relates to a write auxiliary circuit, a memory, and an electronic device. The write auxiliary circuit includes: a logic switching circuit configured such that its input terminal is connected to a power supply voltage, and its control terminal receives a level control signal to provide different voltages; an inverting amplifier configured such that its non-inverting input terminal is grounded, its inverting input terminal is connected to the output terminal of the logic switching circuit, and its output terminal is connected to the bit line and the inverted bit line to reduce the bit line potential; and a resistor selector configured such that its input terminal is connected to the inverting input terminal of the inverting amplifier, its control terminal receives a resistor control signal, and its output terminal is connected to the output terminal of the inverting amplifier to provide different feedback resistor values. By achieving a negative voltage output through the operational amplifier circuit, the gamma ratio and write quiescent noise margin are increased, effectively improving the write capability of the SRAM.

The application discloses an SRAM noise margin analysis method and device, system and storage medium, and relates to the technical field of integrated circuits. The application creatively finds that, on a Bit distribution diagram, points of read-write test passing are often distributed around a line segment, so that the noise margin corresponding to the entire SRAM can be defined on a straight line. The application firstly acquires read-write test results, read noise margin and write noise margin of each Bit in the SRAM to be tested, then obtains a Bit distribution diagram, adopts a straight line fitting mode to fit all points on the Bit distribution diagram, and obtains a fitting line, which corresponds to the straight line of the noise margin corresponding to the entire SRAM; finally, the noise margin line segment of the SRAM to be tested is obtained from the fitting line according to the read-write test results of each Bit, so that the noise margin corresponding to the SRAM to be tested can be reliably analyzed.

The application relates to a static random access memory and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, forming a shallow trench isolation structure and an active region on the substrate, wherein the active region of a transfer tube and the active region of a pull-down tube are perpendicular to each other in the channel direction; performing well ion implantation on the active region, forming a gate structure, and then performing light-doped drain ion implantation; respectively performing pocket ion implantation on the transfer tube and the pull-down tube, so that the transfer tube and the pull-down tube obtain different channel doping distributions; and finally forming a complete static random access memory unit. According to the application, the active region channel directions of the transfer tube and the pull-down tube are designed to be perpendicular to each other, and the pocket ion implantation with an inclined angle is combined, the independent regulation and control of the channel doping of the two types of transistors is realized by using the difference of the shadow effect, and therefore, under the premise of not increasing the number of transistors and the number of mask layers, a more optimal current ratio and a higher read-write noise margin are obtained.

A process angle detection method and system, device, and storage medium, the process angle detection method is used to obtain the worst process angle of an SRAM unit device, the SRAM unit device includes a pull-up transistor, a pull-down transistor, and a transmission gate transistor, including: obtaining electrical data of multiple SRAM unit devices, and the electrical data of the pull-up transistor, the pull-down transistor, and the transmission gate transistor in the same SRAM unit device constitute a first data group; using multiple first data groups to establish a three-dimensional normal distribution model, the shape of the three-dimensional normal distribution model is an ellipsoid; extracting multiple groups of test data groups corresponding to the surface position of the ellipsoid from the first data group; simulating multiple groups of test data groups to obtain multiple corresponding write noise tolerances; extracting the test data group corresponding to the minimum value of the multiple write noise tolerances as the worst process angle. The present invention improves the accuracy of process angle detection.

The invention discloses a design method for optimizing a circuit by inserting a buffer. The method comprises the following steps of: (1) carrying out logic synthesis through a standard cell library to generate a reference circuit; (2) counting drive and load combination pairs actually appearing in the reference circuit, and generating a unit pair statistical table; (3) noise margin distribution of each unit pair is calculated through Monte Carlo simulation, and a noise margin table is generated; (4) determining an optimized unit pair according to a preset noise margin threshold value; (5) inserting a buffer between the unit pairs to be optimized to generate an optimized circuit; according to the invention, the noise margin of the circuit system is improved, so that the yield is improved.