6 results about "Noise margin" patented technology

Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., −25° C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.

The invention discloses a charge sharing type SRAM (Static Random Access Memory) write auxiliary circuit and a control method thereof, the SRAM write auxiliary circuit comprises a first storage array, a second storage array and the charge sharing type write auxiliary circuit, the first storage array and the second storage array are respectively used for storing data, and storage units in the first storage array and the second storage array are arranged in the same way. When writing operation is carried out on the SRAM, dynamic adjustment of the power supply voltage of the storage unit for carrying out the writing operation in the storage array is realized through the charge sharing type writing auxiliary circuit, and the writing noise margin of the SRAM under low voltage can be improved, so that the power consumption of the SRAM is reduced; and for the storage unit which is not enabled, the power supply voltage of the storage unit is kept stable and unchanged, and data destruction is prevented. According to the invention, the writing stability of the SRAM under low voltage can be improved, and lower system working voltage can be supported and realized in a storage system realized by using the SRAM, so that the power consumption of the whole system is reduced.

The application relates to a PLM-14T anti-radiation SRAM memory cell circuit. The PLM-14T anti-radiation SRAM memory cell circuit comprises ten NMOS transistors N1-N10 and four PMOS transistors P1-P4; P1 and P2 and P3 and P4 are cross-coupled, N1 and N2 correspond to P1 and P2 as pull-down tubes, N3 and N4 correspond to P3 and P4 as pull-down tubes, and N5 and N6 constitute a feedback loop for regulating a storage node; a main storage node Q and QB are connected with a bit line BL and BLB through N7 and N8 respectively, and a redundant storage node S1 and S0 are connected with the bit line BL and BLB through N9 and N10 respectively. The storage node of the application adopts a double pull-down loop to play a feedback regulation role, and the anti-flipping capability of the circuit storage node is enhanced. Meanwhile, the circuit uses four transfer transistors for reading and writing, and the data writing speed and the write noise margin of the unit are improved.

This application relates to a write auxiliary circuit, a memory, and an electronic device. The write auxiliary circuit includes: a logic switching circuit configured such that its input terminal is connected to a power supply voltage, and its control terminal receives a level control signal to provide different voltages; an inverting amplifier configured such that its non-inverting input terminal is grounded, its inverting input terminal is connected to the output terminal of the logic switching circuit, and its output terminal is connected to the bit line and the inverted bit line to reduce the bit line potential; and a resistor selector configured such that its input terminal is connected to the inverting input terminal of the inverting amplifier, its control terminal receives a resistor control signal, and its output terminal is connected to the output terminal of the inverting amplifier to provide different feedback resistor values. By achieving a negative voltage output through the operational amplifier circuit, the gamma ratio and write quiescent noise margin are increased, effectively improving the write capability of the SRAM.

The application discloses an SRAM noise margin analysis method and device, system and storage medium, and relates to the technical field of integrated circuits. The application creatively finds that, on a Bit distribution diagram, points of read-write test passing are often distributed around a line segment, so that the noise margin corresponding to the entire SRAM can be defined on a straight line. The application firstly acquires read-write test results, read noise margin and write noise margin of each Bit in the SRAM to be tested, then obtains a Bit distribution diagram, adopts a straight line fitting mode to fit all points on the Bit distribution diagram, and obtains a fitting line, which corresponds to the straight line of the noise margin corresponding to the entire SRAM; finally, the noise margin line segment of the SRAM to be tested is obtained from the fitting line according to the read-write test results of each Bit, so that the noise margin corresponding to the SRAM to be tested can be reliably analyzed.

The invention discloses a design method for optimizing a circuit by inserting a buffer. The method comprises the following steps of: (1) carrying out logic synthesis through a standard cell library to generate a reference circuit; (2) counting drive and load combination pairs actually appearing in the reference circuit, and generating a unit pair statistical table; (3) noise margin distribution of each unit pair is calculated through Monte Carlo simulation, and a noise margin table is generated; (4) determining an optimized unit pair according to a preset noise margin threshold value; (5) inserting a buffer between the unit pairs to be optimized to generate an optimized circuit; according to the invention, the noise margin of the circuit system is improved, so that the yield is improved.