179 results about "Noise margin" patented technology

A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.

Methods and apparatus for maintaining the maximum achievable data rate on a DSL line, up to and including a rate to which a user subscribes is described. Performance monitoring is conducted on the DSL line on an ongoing basis to determine noise margins in each direction. Each noise margin is compared against pre-determined decreasing/increasing thresholds to determine whether the line characteristics dictate a data rate change without loss of synchronization. The invention supports dynamic provisioning changes including application driven service level change requests, e.g., new bandwidth-on demand services. In some embodiments, a combination of existing and new embedded operations channel (EOC) messages are used to implement the modem data rate changes. New EOC messages may be implemented using some of the reserved and/or vendor proprietary Opcodes currently permitted. Modem assigned data rate changes are implemented without a disruption of service, e.g., without the need for re-initialization and/or re-synchronization.

The present invention relates to a semiconductor memory device. According to the present invention, a delay circuit is constructed in order for a refresh operation and a normal operation to have different delay paths such that a minimum tRAS (Active to Precharge command period) delay time of the refresh operation to which tRFC (Auto Referesh to Active/Auto Referesh command period) is applied is longer than a minimum tRAS delay time of a normal operation to which tRC (Active to Active/Auto Refresh command period) is applied. Thus, a greater noise margin is secured in tRFC in a refresh operation being the worst situation of a DRAM. Accordingly, the probability that fail can occur is reduced and the yield upon test is thus improved.

A junction FET having a large gate noise margin is provided. The junction FET comprises an n⁻ layer forming a drift region of the junction FET formed over a main surface of an n⁺ substrate made of silicon carbide, a p⁺ layer forming a gate region formed in contact with the n⁻ layer forming the drift region and a gate electrode provided in an upper layer of the n⁺ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n⁺ substrate and electrically connecting the p⁺ layer forming the gate region and the gate electrode.

Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.

Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. These performance advantages allow a noise margin target to be achieved using simpler component codes and a much shorter interleaver than was needed when using prior art codes such as Turbo codes. Decoders are also provided. Both encoding and decoding complexity can be lowered, and interleavers can be made much shorter, thereby shortening the block lengths needed in receiver elements such as equalizers and other decision-directed loops. Also, other advantages are provided such as the elimination of a error floor present in prior art serially-concatenated codes. That allows the present invention to achieve much higher performance at lower error rates such as are needed in optical communication systems.

Methods, systems, and computer program products adaptively apply a target noise margin to a DSL loop to establish a DSL data rate on the DSL loop. A method involves receiving performance data associated with a quantity of errors detected over a period of time on the DSL loop and adjusting the target noise margin for the DSL loop based on the performance data. The target noise margin is inversely associated with the DSL data rate that can be established and is adjusted in order to maximize the DSL data rate while minimizing the quantity of errors detected over the period of time. Thus, embodiments of the present invention allow a maximum data rate that can be sustained on a DSL loop without an excessive quantity of errors.

The present invention utilizes external synchronization to generate a completely standardized or functionally standardized optical transmission unit of level k (OTUk[V]) signal providing less jitter and wander build-up through a network of optical transport network (OTN) elements. This increases noise margins of transported signals and payloads. The present invention provides stratum-level synchronization utilizing a standards-based approach. In one embodiment of the present invention, rate adapters are included to provide m/n scaling of OTUk[V] signals to rates common in SONET and SDH synchronizers to provide line and loop distribution of timing through OTUk[V] signals. The present invention provides a choice of external synchronization sources including building integrated timing source (BITS), line, and loop timing sources. In another exemplary embodiment, the present invention provides multiple external references and automated timing protection switching for redundancy and reliability.

The present invention provides digital subscriber line noise mitigation techniques, and applications thereof. In an embodiment, the present invention provides a toolbox of methods and techniques for mitigating the effects of noise in xDSL systems. These methods and techniques are controllable and locatable at one or both ends of a DSL communication link (e.g., within a central office transceiver unit or a remote transceiver unit). These novel methods and techniques include: (1) per tone noise margin modification, (2) data framer constraints modification, (3) improved noise measurements; (4) more robust on-line reconfiguration processes, (5) worst case noise monitoring, (6) induced bit rate limitations, and (7) distortion noise mitigation. These methods and techniques are particularly useful for mitigating the effects of time-varying noise and impulse noise.

A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

A sense amplifier, system and methods for increasing a noise margin of the sense amplifier are contemplated herein. In general, the sense amplifier includes a pair of cascode transistors coupled in parallel between a power supply node and a sense line of the sense amplifier. The sense amplifier also includes a precharge node coupled to the power supply node through a first precharge transistor, and a sense node coupled to the power supply node through a second precharge transistor. The sense amplifier described herein functions to separate the sense node from the precharge node with the pair of cascode transistors, which in turn, increases the noise margin of the sense amplifier by decoupling the sense node from any voltage fluctuations that may be present on the sense line during a sensing state.

Systems and methods for power and bidirectional data transmission using a plurality of wires. A multiphase digital signal is downlinked from a main unit to a remote unit over the plurality of wires and is converted to a DC power signal used to power the remote unit. Uplink data is sent from the remote to the main over one selected wire during a predetermined time period for an uplink transmission by amplitude modulating the received digital signal at the remote. During an uplink, the output impedance of the line driver in the main unit connected to the wire selected for the uplink is increased to allow for the uplink amplitude modulation. The modulated signal is maintained within the noise margins of the digital circuits in the main and remote units.

Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. These performance advantages allow a noise margin target to be achieved using simpler component codes and a much shorter interleaver than was needed when using prior art codes such as Turbo codes. Decoders are also provided. Both encoding and decoding complexity can be lowered, and interleavers can be made much shorter, thereby shortening the block lengths needed in receiver elements such as equalizers and other decision-directed loops. Also, other advantages are provided such as the elimination of a error floor present in prior art serially-concatenated codes. That allows the present invention to achieve much higher performance at lower error rates such as are needed in optical communication systems.

Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.

Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. These performance advantages allow a noise margin target to be achieved using simpler component codes and a much shorter interleaver than was needed when using prior art codes such as Turbo codes. Decoders are also provided. Both encoding and decoding complexity can be lowered, and interleavers can be made much shorter, thereby shortening the block lengths needed in receiver elements such as equalizers and other decision-directed loops. Also, other advantages are provided such as the elimination of a error floor present in prior art serially-concatenated codes. That allows the present invention to achieve much higher performance at lower error rates such as are needed in optical communication systems.

Disclosed is an isolated power conversion system for providing a function of isolated power conversion by converting an AC power into a DC output power, and a rectifying unit, a transformer, a switching transistor, a first pulse width modulation (PWM) controller, a second PWM controller, an output unit and a signal blocking unit are included. The signal blocking unit is employed as a connection interface between the first and second PWM controllers to provide digital signal for communication. Noise margin and stability of electrical operation are improved to avoid malfunction. Overall, the present invention greatly enhances stability of power conversion and secures quality of electrical signal.

A voltage booting circuit for booting the switching signal applied to a column access passgate is employed to reduce the voltage drop across the passgate. Reduction of the voltage dropped across the passgate results in faster read and write times and improved noise margin. In one application the booted voltage is used only during a write operation, but not during a read. In another application, the booted voltage is used during both operations.

Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.