High-reliability static storage cell and application method thereof

Abstract

The invention discloses a high-reliability static storage cell and an application method thereof. The high-reliability static storage cell comprises a first pull-up transistor PU-1, a second pull-up transistor PU-2, a first pull-down transistor PD-1, a second pull-down transistor PD-2, a first read access transistor RPG-1, a second read access transistor RPG-2, a first write access transistor WPG-1 and a second write access transistor WPG-2, wherein the grids of the first read access transistor RPG-1 and the second read access transistor RPG-2 are connected on a read access control signal RD, and the first write access transistor WPG-1 and the second write access transistor WPG-2 are connected on a write access control signal WR. By applying the storage cell and the application method thereof, the problems that a read noise margin is increasingly serious due to that a process is improved and a power supply voltage is reduced and the noise margin and single event upset are maintained can be solved, and the reliability of the static storage cell is improved.

Description

Technical field: [0001] The invention belongs to the field of static memory, and relates to a static memory unit, in particular to a highly reliable static memory unit. Background technique: [0002] As CMOS process feature sizes and power supply voltages continue to decrease, CMOS devices face significant reliability challenges. For the static memory unit, its noise tolerance, whether it is reading or writing or maintaining, decreases with the decrease of the power supply voltage, which affects its reliability. In addition, as the feature size decreases, the influence factors of process changes are continuously strengthened, especially for small-sized transistors such as memory cells, the driving capability characteristics change range is wider, and the noise margin is reduced, making the yield of static memory arrays difficult. improve. [0003] Since the voltage of the storage node increases during the read operation of the transistor, the noise margin is reduced. There...

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Problems solved by technology

[0004] The technical problem solved by the present invention is to suppress the increasingly severe read noise margin due to technological progress and lower power supply voltage, maintain the noise margin and single event flipping problems, and improve the reliability of static memory cells

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