Stable SRAM bitcell design utilizing independent gate FinFET

A static random access and memory technology, applied in static memory, transistors, digital memory information, etc., can solve the problems of deterioration of remaining parameters and lack of improvement

Active Publication Date: 2013-07-10
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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[0018] While the technique provides improvement in one or both of these parameters, it co

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  • Stable SRAM bitcell design utilizing independent gate FinFET
  • Stable SRAM bitcell design utilizing independent gate FinFET
  • Stable SRAM bitcell design utilizing independent gate FinFET

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Embodiment Construction

[0038] Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments. Alternative embodiments may be devised without departing from the scope of the present invention. Additionally, well-known elements of various embodiments will not be described in detail or will be omitted so as not to obscure the relevant details of the various embodiments.

[0039] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments" does not require that all embodiments include the discussed feature, advantage or mode of operation.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms "a", "an" and "the" ...

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Abstract

Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

Description

technical field [0001] The disclosed embodiments relate to static random access memory (SRAM) bit cells. More specifically, exemplary embodiments relate to highly stable SRAM cells using independent gate fin field effect transistor (FinFET) (IG-FinFET) architectures. Background technique [0002] SRAM is typically used in applications where speed and low power are considerations. SRAM cells are fast and do not require dynamic updates, as in the case of dynamic random access memory (DRAM) cells. The structure of a conventional SRAM cell includes two cross-coupled inverters typically formed by four complementary metal-oxide-semiconductor field-effect transistors (complementary MOSFETs or CMOS transistors). Cross-coupled inverters form a basic storage element with two stable states representing complementary binary values ​​"0" and "1". Two additional transistors (referred to as "access transistors") are used to control access to the storage element during read and write ope...

Claims

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Application Information

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IPC IPC(8): G11C11/412H01L21/8244H01L27/11
CPCY10T29/49117G11C11/4125H10B10/12G11C5/063G11C7/18G11C7/22G11C11/412G11C11/417
Inventor 金圣克康明谷朴贤国宋森秋穆罕默德·阿布-拉赫马韩秉莫格立新王忠泽
Owner QUALCOMM INC
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