Stable SRAM bitcell design utilizing independent gate FinFET

Abstract

Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

Description

technical field [0001] The disclosed embodiments relate to static random access memory (SRAM) bit cells. More specifically, exemplary embodiments relate to highly stable SRAM cells using independent gate fin field effect transistor (FinFET) (IG-FinFET) architectures. Background technique [0002] SRAM is typically used in applications where speed and low power are considerations. SRAM cells are fast and do not require dynamic updates, as in the case of dynamic random access memory (DRAM) cells. The structure of a conventional SRAM cell includes two cross-coupled inverters typically formed by four complementary metal-oxide-semiconductor field-effect transistors (complementary MOSFETs or CMOS transistors). Cross-coupled inverters form a basic storage element with two stable states representing complementary binary values ​​"0" and "1". Two additional transistors (referred to as "access transistors") are used to control access to the storage element during read and write ope...

AI Technical Summary

Problems solved by technology

[0018] While the technique provides improvement in one or both of these parameters, it comes at the expense of deterioration and / or lack of improvement in the remaining parameters

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