446 results about "Correlated double sampling" patented technology

An image sensor and method, which includes a switching device for establishing a connection between at least one column line and one of at least two analog-to-digital converter blocks, where at least one of the at least two analog-to-digital converter blocks is connectable to at least two rows of a plurality of unit pixels. An image sensor and method, where, if a row line is odd, column outputs from odd column lines of an active pixel sensor array are connected to a first correlated double sampling block and column outputs from even column lines of the active pixel sensor array are connected to a second correlated double sampling block and if the row line is even, column outputs from odd column lines of the active pixel sensor array are connected to the second correlated double sampling block and column outputs from even column lines of the active pixel sensor array are connected to the first correlated double sampling block. An image sensor and method where a first subset of a plurality of unit pixels are connected to a first correlated double sampling block and a second subset of the plurality of unit pixels are connected to a second correlated double sampling block, where the first subset of the plurality of unit pixels are blue and red pixels and the second subset of the plurality of unit pixels are green pixels. A circuit and method for reducing fixed pattern noise.

The invention brings forward a sensing circuit to sense micro currents and voltages of a device to be sensed. OLED display equipment comprises: a pixel circuit and the sensing circuit. The sensing circuit is connected to the pixel circuit through sensing lines. The sensing circuit comprises: an amplifier, a first capacitor, a first switch, a second switch, a third switch, a fourth switch, a correlated double sampling (CDS) circuit, and an analog-digital converter (ADC).

An image sensor comprises an active pixel sensor (APS) array, a first analog-to-digital converter (ADC), and a ramp signal generator. The APS array has includes a plurality of pixels of arranged in a second order two-dimensional matrix, and wherein the APS array generates a reset signal and an image signal for each pixel of selected columns. The first ADC has includes correlated double sampling (CDS) circuits for each column of the APS array, and wherein the first ADC generates a digital code corresponding to the difference between the reset signal and the image signal using an output ramp signal that is applied to the CDS circuits for each column. The ramp generator generates the output ramp signal in which a low illumination portion and a high illumination portion have different slopes.

A multi-stage circuit that includes a number of stages, with at least one stage being of a first type and at least one stage being of a second type. Each stage receives either a circuit input signal or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each first type (or second type) stage operates based on one or more clock signals having a frequency of fS (or fS / N), where fS is the sampling frequency and N is an integer greater than one. Each first type stage may be implemented with a correlated double-sampling circuit, an auto-zeroing circuit, or a chopper stabilization circuit. Each second type stage may be implemented with a multi-sampling (i.e., double-sampling or higher order sampling) circuit. The multi-stage circuit may be designed to implement a lowpass filter, a DELTASIGMA ADC, or some other circuit.

A column analog-to-digital conversion apparatus includes a first correlated double sampling (CDS) and comparison unit of a CDS and comparison circuit for generating a first comparison result signal in response to a first pixel output signal and a ramp signal, a second CDS and comparison unit of the CDS and comparison circuit for generating a second comparison result signal in response to the first pixel output signal and the ramp signal in a sub-sampling mode, and a data buffer for determining a code value of a most significant bit (MSB) based on the second comparison result signal, determining code values of remaining lower bits based on a counting value outputted from a counter, and generating a digital code including the MSB and the remaining lower bits.