88 results about "Cmos pixels" patented technology

A circuit and method measure the output voltage of a CMOS pixel in a manner that substantially reduces all columnar pattern noise due to mismatches in the signal processing circuits including the correlated double sampling amplifiers and A/D converters. The circuit includes a test switch, operatively connected between a reference voltage source and a correlated double sampling amplifier, for applying a test voltage from the reference voltage source when the state of the test switch is ON to the correlated double sampling amplifier. The reference voltage source produces a voltage corresponding to a full-scale voltage level to enable the determination of a gain error in the correlated double sampling amplifier and/or A/D converter; a voltage corresponding to ground to enable the determination of an offset error in the correlated double sampling amplifier and/or A/D converter; and a plurality of analog voltages ranging from analog ground to a full-scale voltage level to enable the determination of non-linearity errors in the A/D converter.

A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact.

An improved CMOS pixel with a combination of analog and digital readouts to provide a large pixel dynamic range without compromising low-light performance using a comparator to test the value of an accumulated charge at a series of exponentially increasing exposure times. The test is used to stop the integration of photocurrent once the accumulated analog voltage has reached a predetermined threshold. A one-bit output value of the test is read out of the pixel (digitally) at each of the exponentially increasing exposure periods. At the end of the integration period, the analog value stored on the integration capacitor is read out using conventional CMOS active pixel readout circuits.

A method of sensing radiation in a pixel includes applying a transfer clock signal, applying a pixel reset clock signal, and applying a pixel reset voltage. The applying a transfer clock signal applies the transfer clock signal to a gate electrode of a transfer gate transistor. The applying a pixel reset clock signal applies the pixel reset clock signal to a gate electrode of the pixel reset transistor. The applying a pixel reset voltage applies the pixel reset voltage to a drain of the pixel reset transistor. The method further includes switching the transfer clock signal to a high state, switching the pixel reset clock signal to a high state, switching the pixel reset voltage to a low state, switching the pixel reset voltage to a high state, and switching the pixel reset clock signal to a low state at a beginning of an integration cycle.

An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

A method for determining a pixel output value of an imager; the imager having a plurality of pixels, a reset switch associated with each pixel and a select switch associated with each pixel; due to incident illumination upon a pixel of the imager after a reset period. The method captures a first pixel output value when the reset switch is OFF during a reset period and the select switch is ON during a reset period and captures a second pixel output value when the select switch is ON near an end of an integration period. If the second pixel output value is captured when the select switch is ON near an end of a first integration period, the first pixel output value may be captured when the reset switch is OFF during a reset period preceding the first integration period and the select switch is ON during a reset period preceding the first integration period. Moreover, if the second pixel output value is captured when the select switch is ON near an end of a first integration period, the first pixel output value may be captured when the reset switch is OFF during a reset period immediately following the first integration period and the select switch is ON during a reset period immediately following the first integration period.

A pixel includes five transistors, a photodetector and a storage node. A first transistor is coupled between the photodetector and the storage node. A second transistor includes a second transistor source and a second transistor drain. The second transistor source is coupled to the storage node. The second transistor drain is coupled to an output drain voltage. A third transistor includes a third transistor drain. The third transistor is coupled between the photodetector and a pixel reset voltage. The third transistor drain is coupled to the pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

The invention discloses an X-ray detector and a manufacturing method thereof. The X-ray detector comprises an interconnection substrate, bonding interconnection, a photovoltaic conversion device chip and a CMOS pixel reading chip, wherein the bonding interconnection penetrates through the interconnection substrate and is exposed out of the two main surfaces of the interconnection substrate, the photovoltaic conversion device chip is bonded with one main surface of the interconnection substrate, the CMOS pixel reading chip is bonded with the other main surface of the interconnection substrate, and a bonding pad of the photovoltaic conversion device chip is electrically connected with a bonding pad of the CMOS pixel reading chip through the bonding interconnection. According to the X-ray detector, working processes can be simplified, and reliability and yield can be improved.

A CMOS pixel is disclosed. The CMOS pixel includes a semiconductor substrate; a sense node formed in the semiconductor substrate and positioned substantially in the center of the CMOS pixel; a transfer gate formed about the sense node; and at least one photodiode formed about the transfer gate. A reset transistor, a source follower transistor, and a row select transistor are located substantially to one side of the CMOS pixel substantially adjacent to the photodiode. The sense node is operable to be floating. An implant may be formed about the photodiode configured to step potential in a direction toward the sense node.

A method of operating a CMOS pixel is disclosed. The CMOS pixel includes a photodiode (PPD), a transfer gate coupled to the PPD, and an anti-blooming drain coupled to the transfer gate. A potential barrier is formed between a potential well underlying the PPD and the transfer gate. Charge is accumulated in the potential well in response to electromagnetic radiation during a first integration time. Excess charge is removed from the potential well to the anti-blooming drain that exceeds the first potential barrier. A size of the potential barrier is increased. Charge is accumulated in the potential well during a second integration time.

A CMOS image sensor is disclosed. The CMOS image sensor includes a semiconductor substrate having a surface. An epitaxial layer is grown on the surface. A p-type CMOS pixel formed substantially in the epitaxial layer. In one version of the CMOS image sensor, there exists a net n-type dopant concentration profile in the semiconductor substrate and the epitaxial layer which has a maximum value at a predetermined distance from the surface and which decreases monotonically on both sides of the profile from the maximum value within the semiconductor substrate and the epitaxial layer. In another version of the CMOS image sensor, there exists a net n-type dopant concentration profile in the semiconductor substrate and the epitaxial layer which has a maximum value at the surface and which decreases monotonically with increasing distance from the surface within the semiconductor substrate and the epitaxial layer.

An image sensor having a two-dimensional array of CMOS pixel sensors, a row decoder and a column decoder is disclosed. The two-dimensional array of CMOS pixel sensors is organized as a plurality of rows and columns that are addressed with the aid of row and column decoders. At least one of the column decoder or the row decoder is located between two of the rows or two of the columns, respectively. X-rays are converted to light that is detected by the image sensor by a layer of scintillation material that overlies the two-dimensional array. The internally located decoder or decoders facilitate sensors in which the two-dimensional array includes a rectangular array having a chamfered corner such that rows or columns that extend into the chamfered corner have lengths that are less than rows or columns, respectively, that do not extend into the corners.

A method of operating a CMOS pixel is disclosed. The CMOS pixel includes a photodiode (PPD), a transfer gate coupled to the PPD, and an anti-blooming drain coupled to the transfer gate. A potential barrier is formed between a potential well underlying the PPD and the transfer gate. Charge is accumulated in the potential well in response to electromagnetic radiation during a first integration time. Excess charge is removed from the potential well to the anti-blooming drain that exceeds the first potential barrier. A size of the potential barrier is increased. Charge is accumulated in the potential well during a second integration time.

The invention relates to a digital-analog hybrid integrated circuit design field and provides an asynchronous CMOS pixel circuit with a light adaptive threshold voltage adjustment mechanism. The objectives of the invention are to maintain the advantages of high dynamic range and low fixed-model noise of a circuit, and compress time for measuring light intensity in a relatively small range, and improve the response speed of the circuit. In order to achieve the above objectives, the following technical schemes are adopted: the asynchronous CMOS pixel circuit with the light adaptive threshold voltage adjustment mechanism is composed of a light intensity change detection unit (CD), an exposure measurement unit (EM) using a PWM mode and a VrefL reference voltage switching unit; and output signals Rst of the output end R of the change detection unit are connected with the input end Reset of the exposure measurement unit and the input end T1 of the VrefL reference voltage switching unit and are respectively used for controlling signals of measurement initiating of the exposure measurement unit and controlling the evaluation of light intensity. The asynchronous CMOS pixel circuit with the light adaptive threshold voltage adjustment mechanism of the invention is mainly applied to the digital-analog hybrid integrated circuit design.

The invention relates to an active CMOS pixel structure comprising: at least one photoelectric conversion zone (NPD) defined by n-doping of the substrate, said zone accumulating an amount of charge during an exposure to light and comprising a p-doped surface zone (PIN); and at least one MOS transfer transistor (TX), the gate of said transfer transistor (TX) being electrically insulated from the substrate and being used to control transfer of said charge from said photoelectric conversion zone (NPD) to said floating diffusion node (FD), in which the gate of said transfer transistor (TX) partially covers said p-doped surface zone (PIN), and said photoelectric conversion zone (NPD) extends under said gate of said transfer transistor (TX) at least as far as the end of the p-doped surface zone (PIN).

The embodiment of the invention provides a laminated complementary metal oxide semiconductor image sensor and an image processing method. The laminated complementary metal oxide semiconductor image sensor includes: two laminated pixel units alternately arranged; the two laminated pixel units comprise photodiode PD columns of three sizes, wherein two layers of PD columns are respectively arranged on each laminated pixel unit in the two laminated pixel units; wherein the two layers of photodiode PD columns comprise PD columns of two sizes, the sizes of the PD columns of each layer in the two layers of PD columns are the same, and the two laminated pixel units utilize the PD columns of the three sizes to absorb RGB three-color light respectively and convert optical signals corresponding to the RGB three-color light into electric signals corresponding to the RGB three-color light; the CMOS pixel reading circuits are connected with the output ends of the two laminated pixel units, each layer of PD column is connected with one CMOS pixel reading circuit, and the CMOS pixel reading circuits are used for amplifying electric signals and reading the electric signals.

The embodiment of the application provides a CMOS image sensor, an image processing method and a storage medium. The CMOS image sensor comprises triangular pixel units arranged in a hexagonal array and a CMOS pixel readout circuit connected with the triangular pixel units, wherein each triangular pixel unit is internally provided with a photodiode PD column and uses the photodiode PD column to absorb RGB monochromatic light and convert a corresponding optical signal into an electric signal, and the CMOS pixel readout circuit is used for amplifying and reading out the electric signals.

An imaging array having a plurality of pixels is disclosed. Each pixel includes a photodetector that converts light to charge, a floating diffusion node, a first amplification stage connected to the floating diffusion node, and a select gate that connects the pixel to a second amplification stage. The first and second amplification stages form a current mirror. The first amplification stage includes a buried channel device. In one aspect of the present invention, the current minor has an overall voltage gain of between 0.9 and 1.1. In another aspect of the invention, the second amplification stage is shared by a plurality of pixels.

The invention provides a CMOS pixel unit and a signal collection method thereof. The CMOS pixel unit is characterized in that a positive electrode of a photosensitive diode is connected with a negative electrode of a power source, a strong light processing circuit is connected with a drain electrode of a first NMOS tube and a source electrode of a second NMOS tube and is used for adding a storage capacitance for an electric signal when the photosensitive diode is irradiated by strong light, the positive electrode of an array current source is connected with the drain electrode of a third NMOS tube and serves as a signal output end of the high-dynamic CMOS pixel unit, the negative electrode of the array current source is connected with the negative electrode of the power source, the source electrode of the first NMOS tube is connected with the negative electrode of the photosensitive diode and is used for conducting the photosensitive diode, the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the positive electrode of the power source and is used for realizing restoration of an output signal, and the source electrode of the third NMOS tube is connected with a strong light processing circuit and is used for realizing selective connection of each pixel unit and an array output end.