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1607 results about "Rectangular array" patented technology

A rectangular array is an array of two (or more) dimensions separated by comma. You can think of a rectangular array as a table, where the first dimension is the number of rows and the second dimension is the number of columns keeping in mind that every row is the same length.

Rapid Ink-Charging Of A Dry Ink Discharge Nozzle

The present teachings relate to methods and apparatus for depositing one or more materials (e.g., one or more films, such as one or more solids) on one or more substrates, which may form part of an OLED or other type(s) of display. In some embodiments, the disclosure relates to apparatus and methods for depositing ink on one or more substrates. The apparatus can include, for example, one or more chambers for receiving ink, and plural orifices configured in the one or more chambers which are adapted for ejecting droplets of the ink; a discharge nozzle comprising an array of micro-pores (e.g., configured in a rectangular array), with each micro-pore having an inlet port and an outlet port, and the discharge nozzle receiving plural quantities (e.g., droplets) of ink from the chamber(s) via the orifices at the inlet ports and dispensing the ink from the outlet ports. The droplets of ink can be received at unique, spaced-apart locations on the inlet ports of the discharge nozzle. In some embodiments, a single liquid ink-holding chamber, which includes plural orifices (e.g., three), receives ink in liquid form having a plurality of suspended particles, and droplets of the ink are ejected substantially simultaneously from the chamber to respective, spaced-apart locations on the discharge nozzle; and the discharge nozzle evaporates the carrier liquid and deposits the solid particles on one or more substrates.
Owner:KATEEVA

Difunctional device integrating wave plate based on medium meta-surface and optical device

The invention discloses a wave plate based on a medium meta-surface, a beam deflector and a difunctional device integrating the wave plate and a focusing lens. The devices work in a communication waveband, silicon is adopted as a dielectric material, and a substrate is made from silicon dioxide. The devices are characterized in that the brick shape of the silicon material serves as the design ofa unit structure, and a plurality of brick-shaped structures conforming to required phase gradient are arranged according to two-dimensional crystal lattice periodicity to form a rectangular array; the thickness of silicon nano-bricks of the unit structures with medium meta-surfaces is 0.9 microns. The transmitted phase difference of an x-line deflection light component and a y-line deflection light component of incident light is controlled by adjusting the length and width of the unit structures while the deflector or the focusing lens is achieved before phase wave control, and accordingly functions of the wave plate are achieved. Compared with existing devices, the devices are simple in structure, and the deflection efficiency is improved to 80%. Compared with existing wave plates and optical devices which are used in a stacked way, processing and manufacturing inconvenience is overcome, and integration and miniaturization of the optical devices are facilitated.
Owner:DONGGUAN UNIV OF TECH

Block level routing architecture in a field programmable gate array

An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16x16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16x16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16x16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Block (EB) 3x3 switch matrix. A second side of each EB 3x3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3x3 switch matrix may be coupled to the leads on the second side of second EB3x3 switch matrix by BC criss-cross extension.
Owner:ACTEL CORP

Ventilated moistureproof switch cabinet

The invention provides a ventilated moistureproof switch cabinet comprising a cabinet body, a base and a top cover, wherein the cabinet body is in a cuboid structure; the base is in a quadrangular frustum pyramid; the top cover is in a triangular prism structure; the cabinet body is arranged on the top of the base; the top cover is positioned on the top of the cabinet body; a hydraulic jacking device is arranged between the top cover and the cabinet body; a plurality of ventilation holes are formed in the top of the cabinet body and are distributed along a rectangular array; a double-opening door is formed in the front end of the cabinet body; two cooling fans are arranged on the left side surface of the cabinet body and are distributed in an up-down manner; a ventilation and cooling mechanism is arranged on the right side surface of the cabinet body; a control system is arranged in the cabinet body; a dust prevention filtering net is positioned at the inner side of the ventilation and cooling mechanism on the right side surface of the cabinet body; a plurality of cooling holes are formed between the two cooling fans on the left side surface of the cabinet body. The ventilated moistureproof switch cabinet is good in cooling and moistureproof effects, reliable to work, long in service life and capable of achieving automatic cooling and moistureproof effects.
Owner:STATE GRID CORP OF CHINA +1

Block symmetrization in a field programmable gate array

An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16x16 tiles arranged in a rectangular array and enclosed by I / O blocks on the periphery. On each of the four sides of a B16x16 tile, and also associated with each of the I / O blocks is a freeway routing channel. A B16x16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF . Each of the LUT3s have first, second, and third inputs and a single output. Each of the LUT2s have first and second inputs and a single output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are muliplexed to the input of DFF, and symmetrized with the output of the DFF to form first and second outputs of each of the clusters.
Owner:MICROSEMI SOC
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